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swr: Use the default behavior of ALLOW_MAPPED_BUFFERS.
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/format/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "frontend/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 snprintf(buf, sizeof(buf), "SWR (LLVM " MESA_LLVM_VERSION_STRING ", %u bits)",
73 lp_native_vector_width);
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static bool
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return false;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return false;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return false;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return false;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return false;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside gallium frontends.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return false;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return false;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return false;
142 }
143
144 if (bind & PIPE_BIND_VERTEX_BUFFER) {
145 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) {
146 return false;
147 }
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC ||
151 format_desc->layout == UTIL_FORMAT_LAYOUT_FXT1)
152 {
153 return false;
154 }
155
156 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
157 format != PIPE_FORMAT_ETC1_RGB8) {
158 return false;
159 }
160
161 if ((bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) &&
162 ((bind & PIPE_BIND_DISPLAY_TARGET) == 0)) {
163 /* Disable all 3-channel formats, where channel size != 32 bits.
164 * In some cases we run into crashes (in generate_unswizzled_blend()),
165 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
166 * In any case, disabling the shallower 3-channel formats avoids a
167 * number of issues with GL_ARB_copy_image support.
168 */
169 if (format_desc->is_array &&
170 format_desc->nr_channels == 3 &&
171 format_desc->block.bits != 96) {
172 return false;
173 }
174 }
175
176 return TRUE;
177 }
178
179 static int
180 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
181 {
182 switch (param) {
183 /* limits */
184 case PIPE_CAP_MAX_RENDER_TARGETS:
185 return PIPE_MAX_COLOR_BUFS;
186 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
187 return SWR_MAX_TEXTURE_2D_SIZE;
188 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
189 return SWR_MAX_TEXTURE_3D_LEVELS;
190 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
191 return SWR_MAX_TEXTURE_CUBE_LEVELS;
192 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
193 return MAX_SO_STREAMS;
194 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
195 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
196 return MAX_ATTRIBUTES * 4;
197 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
198 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
199 return 1024;
200 case PIPE_CAP_MAX_VERTEX_STREAMS:
201 return 4;
202 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
203 return 2048;
204 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
205 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
206 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
207 case PIPE_CAP_MIN_TEXEL_OFFSET:
208 return -8;
209 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
210 case PIPE_CAP_MAX_TEXEL_OFFSET:
211 return 7;
212 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
213 return 4;
214 case PIPE_CAP_GLSL_FEATURE_LEVEL:
215 return 330;
216 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
217 return 140;
218 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
219 return 16;
220 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
221 return 64;
222 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
223 return 65536;
224 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
225 return 1;
226 case PIPE_CAP_MAX_VIEWPORTS:
227 return KNOB_NUM_VIEWPORTS_SCISSORS;
228 case PIPE_CAP_ENDIANNESS:
229 return PIPE_ENDIAN_NATIVE;
230
231 /* supported features */
232 case PIPE_CAP_NPOT_TEXTURES:
233 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
234 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
235 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
236 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
237 case PIPE_CAP_VERTEX_SHADER_SATURATE:
238 case PIPE_CAP_POINT_SPRITE:
239 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
240 case PIPE_CAP_OCCLUSION_QUERY:
241 case PIPE_CAP_QUERY_TIME_ELAPSED:
242 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
243 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
244 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
245 case PIPE_CAP_TEXTURE_SWIZZLE:
246 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
247 case PIPE_CAP_INDEP_BLEND_ENABLE:
248 case PIPE_CAP_INDEP_BLEND_FUNC:
249 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
250 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
251 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
252 case PIPE_CAP_DEPTH_CLIP_DISABLE:
253 case PIPE_CAP_PRIMITIVE_RESTART:
254 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
255 case PIPE_CAP_TGSI_INSTANCEID:
256 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
257 case PIPE_CAP_START_INSTANCE:
258 case PIPE_CAP_SEAMLESS_CUBE_MAP:
259 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
260 case PIPE_CAP_CONDITIONAL_RENDER:
261 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
262 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
263 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
264 case PIPE_CAP_USER_VERTEX_BUFFERS:
265 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
266 case PIPE_CAP_QUERY_TIMESTAMP:
267 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
268 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
269 case PIPE_CAP_DRAW_INDIRECT:
270 case PIPE_CAP_UMA:
271 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
272 case PIPE_CAP_CLIP_HALFZ:
273 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
274 case PIPE_CAP_DEPTH_BOUNDS_TEST:
275 case PIPE_CAP_CLEAR_TEXTURE:
276 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
277 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
278 case PIPE_CAP_CULL_DISTANCE:
279 case PIPE_CAP_CUBE_MAP_ARRAY:
280 case PIPE_CAP_DOUBLES:
281 case PIPE_CAP_TEXTURE_QUERY_LOD:
282 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
283 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
284 case PIPE_CAP_QUERY_SO_OVERFLOW:
285 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
286 return 1;
287
288 /* MSAA support
289 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
290 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
291 case PIPE_CAP_TEXTURE_MULTISAMPLE:
292 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
293 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
294 case PIPE_CAP_FAKE_SW_MSAA:
295 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
296
297 /* fetch jit change for 2-4GB buffers requires alignment */
298 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
299 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
300 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
301 return 1;
302
303 /* unsupported features */
304 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
305 case PIPE_CAP_PCI_GROUP:
306 case PIPE_CAP_PCI_BUS:
307 case PIPE_CAP_PCI_DEVICE:
308 case PIPE_CAP_PCI_FUNCTION:
309 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
310 return 0;
311 case PIPE_CAP_MAX_GS_INVOCATIONS:
312 return 32;
313 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
314 return 1 << 27;
315 case PIPE_CAP_MAX_VARYINGS:
316 return 32;
317
318 case PIPE_CAP_VENDOR_ID:
319 return 0xFFFFFFFF;
320 case PIPE_CAP_DEVICE_ID:
321 return 0xFFFFFFFF;
322 case PIPE_CAP_ACCELERATED:
323 return 0;
324 case PIPE_CAP_VIDEO_MEMORY: {
325 /* XXX: Do we want to return the full amount of system memory ? */
326 uint64_t system_memory;
327
328 if (!os_get_total_physical_memory(&system_memory))
329 return 0;
330
331 return (int)(system_memory >> 20);
332 }
333 default:
334 return u_pipe_screen_get_param_defaults(screen, param);
335 }
336 }
337
338 static int
339 swr_get_shader_param(struct pipe_screen *screen,
340 enum pipe_shader_type shader,
341 enum pipe_shader_cap param)
342 {
343 if (shader == PIPE_SHADER_VERTEX ||
344 shader == PIPE_SHADER_FRAGMENT ||
345 shader == PIPE_SHADER_GEOMETRY
346 || shader == PIPE_SHADER_TESS_CTRL ||
347 shader == PIPE_SHADER_TESS_EVAL
348 )
349 return gallivm_get_shader_param(param);
350
351 // Todo: compute
352 return 0;
353 }
354
355
356 static float
357 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
358 {
359 switch (param) {
360 case PIPE_CAPF_MAX_LINE_WIDTH:
361 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
362 case PIPE_CAPF_MAX_POINT_WIDTH:
363 return 255.0; /* arbitrary */
364 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
365 return 0.0;
366 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
367 return 0.0;
368 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
369 return 16.0; /* arbitrary */
370 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
371 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
372 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
373 return 0.0f;
374 }
375 /* should only get here on unhandled cases */
376 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
377 return 0.0;
378 }
379
380 SWR_FORMAT
381 mesa_to_swr_format(enum pipe_format format)
382 {
383 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
384 /* depth / stencil */
385 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
386 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
387 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
388 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
389 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
390
391 /* alpha */
392 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
393 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
394 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
395 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
396
397 /* odd sizes, bgr */
398 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
399 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
400 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
401 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
402 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
403 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
404 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
405 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
406 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
407
408 /* rgb10a2 */
409 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
410 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
411 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
412 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
413 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
414
415 /* rgb10x2 */
416 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
417
418 /* bgr10a2 */
419 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
420 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
421 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
422 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
423 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
424
425 /* bgr10x2 */
426 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
427
428 /* r11g11b10 */
429 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
430
431 /* 32 bits per component */
432 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
433 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
434 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
435 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
436 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
437
438 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
439 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
440 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
441 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
442
443 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
444 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
445 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
446 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
447
448 {PIPE_FORMAT_R32_UINT, R32_UINT},
449 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
450 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
451 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
452
453 {PIPE_FORMAT_R32_SINT, R32_SINT},
454 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
455 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
456 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
457
458 /* 16 bits per component */
459 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
460 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
461 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
462 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
463 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
464
465 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
466 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
467 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
468 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
469
470 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
471 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
472 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
473 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
474
475 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
476 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
477 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
478 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
479
480 {PIPE_FORMAT_R16_UINT, R16_UINT},
481 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
482 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
483 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
484
485 {PIPE_FORMAT_R16_SINT, R16_SINT},
486 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
487 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
488 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
489
490 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
491 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
492 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
493 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
494 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
495
496 /* 8 bits per component */
497 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
498 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
499 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
500 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
501 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
502 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
503 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
504 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
505
506 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
507 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
508 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
509 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
510
511 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
512 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
513 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
514 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
515
516 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
517 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
518 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
519 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
520
521 {PIPE_FORMAT_R8_UINT, R8_UINT},
522 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
523 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
524 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
525
526 {PIPE_FORMAT_R8_SINT, R8_SINT},
527 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
528 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
529 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
530
531 /* These formats are valid for vertex data, but should not be used
532 * for render targets.
533 */
534
535 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
536 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
537 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
538 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
539
540 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
541 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
542 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
543 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
544
545 /* These formats have entries in SWR but don't have Load/StoreTile
546 * implementations. That means these aren't renderable, and thus having
547 * a mapping entry here is detrimental.
548 */
549 /*
550
551 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
552 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
553 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
554 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
555 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
556
557 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
558 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
559
560 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
561 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
562 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
563
564 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
565 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
566 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
567
568 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
569 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
570 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
571 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
572
573 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
574 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
575 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
576 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
577 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
578 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
579 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
580 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
581
582 {PIPE_FORMAT_I8_UINT, I8_UINT},
583 {PIPE_FORMAT_L8_UINT, L8_UINT},
584 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
585
586 {PIPE_FORMAT_I8_SINT, I8_SINT},
587 {PIPE_FORMAT_L8_SINT, L8_SINT},
588 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
589
590 */
591 };
592
593 auto it = mesa2swr.find(format);
594 if (it == mesa2swr.end())
595 return (SWR_FORMAT)-1;
596 else
597 return it->second;
598 }
599
600 static bool
601 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
602 {
603 struct sw_winsys *winsys = screen->winsys;
604 struct sw_displaytarget *dt;
605
606 const unsigned width = align(res->swr.width, res->swr.halign);
607 const unsigned height = align(res->swr.height, res->swr.valign);
608
609 UINT stride;
610 dt = winsys->displaytarget_create(winsys,
611 res->base.bind,
612 res->base.format,
613 width, height,
614 64, NULL,
615 &stride);
616
617 if (dt == NULL)
618 return false;
619
620 void *map = winsys->displaytarget_map(winsys, dt, 0);
621
622 res->display_target = dt;
623 res->swr.xpBaseAddress = (gfxptr_t)map;
624
625 /* Clear the display target surface */
626 if (map)
627 memset(map, 0, height * stride);
628
629 winsys->displaytarget_unmap(winsys, dt);
630
631 return true;
632 }
633
634 static bool
635 swr_texture_layout(struct swr_screen *screen,
636 struct swr_resource *res,
637 bool allocate)
638 {
639 struct pipe_resource *pt = &res->base;
640
641 pipe_format fmt = pt->format;
642 const struct util_format_description *desc = util_format_description(fmt);
643
644 res->has_depth = util_format_has_depth(desc);
645 res->has_stencil = util_format_has_stencil(desc);
646
647 if (res->has_stencil && !res->has_depth)
648 fmt = PIPE_FORMAT_R8_UINT;
649
650 /* We always use the SWR layout. For 2D and 3D textures this looks like:
651 *
652 * |<------- pitch ------->|
653 * +=======================+-------
654 * |Array 0 | ^
655 * | | |
656 * | Level 0 | |
657 * | | |
658 * | | qpitch
659 * +-----------+-----------+ |
660 * | | L2L2L2L2 | |
661 * | Level 1 | L3L3 | |
662 * | | L4 | v
663 * +===========+===========+-------
664 * |Array 1 |
665 * | |
666 * | Level 0 |
667 * | |
668 * | |
669 * +-----------+-----------+
670 * | | L2L2L2L2 |
671 * | Level 1 | L3L3 |
672 * | | L4 |
673 * +===========+===========+
674 *
675 * The overall width in bytes is known as the pitch, while the overall
676 * height in rows is the qpitch. Array slices are laid out logically below
677 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
678 * just invalid for the higher array numbers (since depth is also
679 * minified). 1D and 1D array surfaces are stored effectively the same way,
680 * except that pitch never plays into it. All the levels are logically
681 * adjacent to each other on the X axis. The qpitch becomes the number of
682 * elements between array slices, while the pitch is unused.
683 *
684 * Each level's sizes are subject to the valign and halign settings of the
685 * surface. For compressed formats that swr is unaware of, we will use an
686 * appropriately-sized uncompressed format, and scale the widths/heights.
687 *
688 * This surface is stored inside res->swr. For depth/stencil textures,
689 * res->secondary will have an identically-laid-out but R8_UINT-formatted
690 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
691 * texels, to simplify map/unmap logic which copies the stencil values
692 * in/out.
693 */
694
695 res->swr.width = pt->width0;
696 res->swr.height = pt->height0;
697 res->swr.type = swr_convert_target_type(pt->target);
698 res->swr.tileMode = SWR_TILE_NONE;
699 res->swr.format = mesa_to_swr_format(fmt);
700 res->swr.numSamples = std::max(1u, pt->nr_samples);
701
702 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
703 res->swr.halign = KNOB_MACROTILE_X_DIM;
704 res->swr.valign = KNOB_MACROTILE_Y_DIM;
705
706 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
707 * surface sample count. */
708 if (screen->msaa_force_enable) {
709 res->swr.numSamples = screen->msaa_max_count;
710 swr_print_info("swr_texture_layout: forcing sample count: %d\n",
711 res->swr.numSamples);
712 }
713 } else {
714 res->swr.halign = 1;
715 res->swr.valign = 1;
716 }
717
718 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
719 unsigned width = align(pt->width0, halign);
720 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
721 for (int level = 1; level <= pt->last_level; level++)
722 width += align(u_minify(pt->width0, level), halign);
723 res->swr.pitch = util_format_get_blocksize(fmt);
724 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
725 } else {
726 // The pitch is the overall width of the texture in bytes. Most of the
727 // time this is the pitch of level 0 since all the other levels fit
728 // underneath it. However in some degenerate situations, the width of
729 // level1 + level2 may be larger. In that case, we use those
730 // widths. This can happen if, e.g. halign is 32, and the width of level
731 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
732 // be 32 each, adding up to 64.
733 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
734 if (pt->last_level > 1) {
735 width = std::max<uint32_t>(
736 width,
737 align(u_minify(pt->width0, 1), halign) +
738 align(u_minify(pt->width0, 2), halign));
739 }
740 res->swr.pitch = util_format_get_stride(fmt, width);
741
742 // The qpitch is controlled by either the height of the second LOD, or
743 // the combination of all the later LODs.
744 unsigned height = align(pt->height0, valign);
745 if (pt->last_level == 1) {
746 height += align(u_minify(pt->height0, 1), valign);
747 } else if (pt->last_level > 1) {
748 unsigned level1 = align(u_minify(pt->height0, 1), valign);
749 unsigned level2 = 0;
750 for (int level = 2; level <= pt->last_level; level++) {
751 level2 += align(u_minify(pt->height0, level), valign);
752 }
753 height += std::max(level1, level2);
754 }
755 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
756 }
757
758 if (pt->target == PIPE_TEXTURE_3D)
759 res->swr.depth = pt->depth0;
760 else
761 res->swr.depth = pt->array_size;
762
763 // Fix up swr format if necessary so that LOD offset computation works
764 if (res->swr.format == (SWR_FORMAT)-1) {
765 switch (util_format_get_blocksize(fmt)) {
766 default:
767 unreachable("Unexpected format block size");
768 case 1: res->swr.format = R8_UINT; break;
769 case 2: res->swr.format = R16_UINT; break;
770 case 4: res->swr.format = R32_UINT; break;
771 case 8:
772 if (util_format_is_compressed(fmt))
773 res->swr.format = BC4_UNORM;
774 else
775 res->swr.format = R32G32_UINT;
776 break;
777 case 16:
778 if (util_format_is_compressed(fmt))
779 res->swr.format = BC5_UNORM;
780 else
781 res->swr.format = R32G32B32A32_UINT;
782 break;
783 }
784 }
785
786 for (int level = 0; level <= pt->last_level; level++) {
787 res->mip_offsets[level] =
788 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
789 }
790
791 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
792 res->swr.pitch * res->swr.numSamples;
793
794 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
795 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
796 return false;
797
798 if (allocate) {
799 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
800 if (!res->swr.xpBaseAddress)
801 return false;
802
803 if (res->has_depth && res->has_stencil) {
804 res->secondary = res->swr;
805 res->secondary.format = R8_UINT;
806 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
807
808 for (int level = 0; level <= pt->last_level; level++) {
809 res->secondary_mip_offsets[level] =
810 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
811 }
812
813 total_size = res->secondary.depth * res->secondary.qpitch *
814 res->secondary.pitch * res->secondary.numSamples;
815
816 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
817 if (!res->secondary.xpBaseAddress) {
818 AlignedFree((void *)res->swr.xpBaseAddress);
819 return false;
820 }
821 }
822 }
823
824 return true;
825 }
826
827 static bool
828 swr_can_create_resource(struct pipe_screen *screen,
829 const struct pipe_resource *templat)
830 {
831 struct swr_resource res;
832 memset(&res, 0, sizeof(res));
833 res.base = *templat;
834 return swr_texture_layout(swr_screen(screen), &res, false);
835 }
836
837 /* Helper function that conditionally creates a single-sample resolve resource
838 * and attaches it to main multisample resource. */
839 static bool
840 swr_create_resolve_resource(struct pipe_screen *_screen,
841 struct swr_resource *msaa_res)
842 {
843 struct swr_screen *screen = swr_screen(_screen);
844
845 /* If resource is multisample, create a single-sample resolve resource */
846 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
847 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
848
849 /* Create a single-sample copy of the resource. Copy the original
850 * resource parameters and set flag to prevent recursion when re-calling
851 * resource_create */
852 struct pipe_resource alt_template = msaa_res->base;
853 alt_template.nr_samples = 0;
854 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
855
856 /* Note: Display_target is a special single-sample resource, only the
857 * display_target has been created already. */
858 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
859 | PIPE_BIND_SHARED)) {
860 /* Allocate the multisample buffers. */
861 if (!swr_texture_layout(screen, msaa_res, true))
862 return false;
863
864 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
865 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
866 alt_template.bind = PIPE_BIND_RENDER_TARGET;
867 }
868
869 /* Allocate single-sample resolve surface */
870 struct pipe_resource *alt;
871 alt = _screen->resource_create(_screen, &alt_template);
872 if (!alt)
873 return false;
874
875 /* Attach it to the multisample resource */
876 msaa_res->resolve_target = alt;
877
878 /* Hang resolve surface state off the multisample surface state to so
879 * StoreTiles knows where to resolve the surface. */
880 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
881 }
882
883 return true; /* success */
884 }
885
886 static struct pipe_resource *
887 swr_resource_create(struct pipe_screen *_screen,
888 const struct pipe_resource *templat)
889 {
890 struct swr_screen *screen = swr_screen(_screen);
891 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
892 if (!res)
893 return NULL;
894
895 res->base = *templat;
896 pipe_reference_init(&res->base.reference, 1);
897 res->base.screen = &screen->base;
898
899 if (swr_resource_is_texture(&res->base)) {
900 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
901 | PIPE_BIND_SHARED)) {
902 /* displayable surface
903 * first call swr_texture_layout without allocating to finish
904 * filling out the SWR_SURFACE_STATE in res */
905 swr_texture_layout(screen, res, false);
906 if (!swr_displaytarget_layout(screen, res))
907 goto fail;
908 } else {
909 /* texture map */
910 if (!swr_texture_layout(screen, res, true))
911 goto fail;
912 }
913
914 /* If resource was multisample, create resolve resource and attach
915 * it to multisample resource. */
916 if (!swr_create_resolve_resource(_screen, res))
917 goto fail;
918
919 } else {
920 /* other data (vertex buffer, const buffer, etc) */
921 assert(util_format_get_blocksize(templat->format) == 1);
922 assert(templat->height0 == 1);
923 assert(templat->depth0 == 1);
924 assert(templat->last_level == 0);
925
926 /* Easiest to just call swr_texture_layout, as it sets up
927 * SWR_SURFACE_STATE in res */
928 if (!swr_texture_layout(screen, res, true))
929 goto fail;
930 }
931
932 return &res->base;
933
934 fail:
935 FREE(res);
936 return NULL;
937 }
938
939 static void
940 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
941 {
942 struct swr_screen *screen = swr_screen(p_screen);
943 struct swr_resource *spr = swr_resource(pt);
944
945 if (spr->display_target) {
946 /* If resource is display target, winsys manages the buffer and will
947 * free it on displaytarget_destroy. */
948 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
949
950 struct sw_winsys *winsys = screen->winsys;
951 winsys->displaytarget_destroy(winsys, spr->display_target);
952
953 if (spr->swr.numSamples > 1) {
954 /* Free an attached resolve resource */
955 struct swr_resource *alt = swr_resource(spr->resolve_target);
956 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
957
958 /* Free multisample buffer */
959 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
960 }
961 } else {
962 /* For regular resources, defer deletion */
963 swr_resource_unused(pt);
964
965 if (spr->swr.numSamples > 1) {
966 /* Free an attached resolve resource */
967 struct swr_resource *alt = swr_resource(spr->resolve_target);
968 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
969 }
970
971 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
972 swr_fence_work_free(screen->flush_fence,
973 (void*)(spr->secondary.xpBaseAddress), true);
974
975 /* If work queue grows too large, submit a fence to force queue to
976 * drain. This is mainly to decrease the amount of memory used by the
977 * piglit streaming-texture-leak test */
978 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
979 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
980 }
981
982 FREE(spr);
983 }
984
985
986 static void
987 swr_flush_frontbuffer(struct pipe_screen *p_screen,
988 struct pipe_resource *resource,
989 unsigned level,
990 unsigned layer,
991 void *context_private,
992 struct pipe_box *sub_box)
993 {
994 struct swr_screen *screen = swr_screen(p_screen);
995 struct sw_winsys *winsys = screen->winsys;
996 struct swr_resource *spr = swr_resource(resource);
997 struct pipe_context *pipe = screen->pipe;
998 struct swr_context *ctx = swr_context(pipe);
999
1000 if (pipe) {
1001 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1002 swr_resource_unused(resource);
1003 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1004 }
1005
1006 /* Multisample resolved into resolve_target at flush with store_resource */
1007 if (pipe && spr->swr.numSamples > 1) {
1008 struct pipe_resource *resolve_target = spr->resolve_target;
1009
1010 /* Once resolved, copy into display target */
1011 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1012
1013 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1014 PIPE_TRANSFER_WRITE);
1015 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1016 winsys->displaytarget_unmap(winsys, spr->display_target);
1017 }
1018
1019 debug_assert(spr->display_target);
1020 if (spr->display_target)
1021 winsys->displaytarget_display(
1022 winsys, spr->display_target, context_private, sub_box);
1023 }
1024
1025
1026 void
1027 swr_destroy_screen_internal(struct swr_screen **screen)
1028 {
1029 struct pipe_screen *p_screen = &(*screen)->base;
1030
1031 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1032 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1033
1034 JitDestroyContext((*screen)->hJitMgr);
1035
1036 if ((*screen)->pLibrary)
1037 util_dl_close((*screen)->pLibrary);
1038
1039 FREE(*screen);
1040 *screen = NULL;
1041 }
1042
1043
1044 static void
1045 swr_destroy_screen(struct pipe_screen *p_screen)
1046 {
1047 struct swr_screen *screen = swr_screen(p_screen);
1048 struct sw_winsys *winsys = screen->winsys;
1049
1050 swr_print_info("SWR destroy screen!\n");
1051
1052 if (winsys->destroy)
1053 winsys->destroy(winsys);
1054
1055 swr_destroy_screen_internal(&screen);
1056 }
1057
1058
1059 static void
1060 swr_validate_env_options(struct swr_screen *screen)
1061 {
1062 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1063 * copied to scratch space on a draw. Past this, the draw will access
1064 * user-buffer directly and then block. This is faster than queuing many
1065 * large client draws. */
1066 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1067 int client_copy_limit =
1068 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1069 if (client_copy_limit > 0)
1070 screen->client_copy_limit = client_copy_limit;
1071
1072 /* XXX msaa under development, disable by default for now */
1073 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1074
1075 /* validate env override values, within range and power of 2 */
1076 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1077 if (msaa_max_count != 1) {
1078 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1079 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1080 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1081 fprintf(stderr, "must be power of 2 between 1 and %d" \
1082 " (or 1 to disable msaa)\n",
1083 SWR_MAX_NUM_MULTISAMPLES);
1084 fprintf(stderr, "(msaa disabled)\n");
1085 msaa_max_count = 1;
1086 }
1087
1088 swr_print_info("SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1089
1090 screen->msaa_max_count = msaa_max_count;
1091 }
1092
1093 screen->msaa_force_enable = debug_get_bool_option(
1094 "SWR_MSAA_FORCE_ENABLE", false);
1095 if (screen->msaa_force_enable)
1096 swr_print_info("SWR_MSAA_FORCE_ENABLE: true\n");
1097 }
1098
1099
1100 struct pipe_screen *
1101 swr_create_screen_internal(struct sw_winsys *winsys)
1102 {
1103 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1104
1105 if (!screen)
1106 return NULL;
1107
1108 if (!lp_build_init()) {
1109 FREE(screen);
1110 return NULL;
1111 }
1112
1113 screen->winsys = winsys;
1114 screen->base.get_name = swr_get_name;
1115 screen->base.get_vendor = swr_get_vendor;
1116 screen->base.is_format_supported = swr_is_format_supported;
1117 screen->base.context_create = swr_create_context;
1118 screen->base.can_create_resource = swr_can_create_resource;
1119
1120 screen->base.destroy = swr_destroy_screen;
1121 screen->base.get_param = swr_get_param;
1122 screen->base.get_shader_param = swr_get_shader_param;
1123 screen->base.get_paramf = swr_get_paramf;
1124
1125 screen->base.resource_create = swr_resource_create;
1126 screen->base.resource_destroy = swr_resource_destroy;
1127
1128 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1129
1130 // Pass in "" for architecture for run-time determination
1131 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1132
1133 swr_fence_init(&screen->base);
1134
1135 swr_validate_env_options(screen);
1136
1137 return &screen->base;
1138 }