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gallium/swr: Enable some ARB_gpu_shader5 extensions
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "state_tracker/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 snprintf(buf, sizeof(buf), "SWR (LLVM " MESA_LLVM_VERSION_STRING ", %u bits)",
73 lp_native_vector_width);
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static bool
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return false;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return false;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return false;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return false;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return false;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return false;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return false;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return false;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
146 return false;
147 }
148
149 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
150 format != PIPE_FORMAT_ETC1_RGB8) {
151 return false;
152 }
153
154 if ((bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) &&
155 ((bind & PIPE_BIND_DISPLAY_TARGET) == 0)) {
156 /* Disable all 3-channel formats, where channel size != 32 bits.
157 * In some cases we run into crashes (in generate_unswizzled_blend()),
158 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
159 * In any case, disabling the shallower 3-channel formats avoids a
160 * number of issues with GL_ARB_copy_image support.
161 */
162 if (format_desc->is_array &&
163 format_desc->nr_channels == 3 &&
164 format_desc->block.bits != 96) {
165 return false;
166 }
167 }
168
169 return TRUE;
170 }
171
172 static int
173 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
174 {
175 switch (param) {
176 /* limits */
177 case PIPE_CAP_MAX_RENDER_TARGETS:
178 return PIPE_MAX_COLOR_BUFS;
179 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
180 return SWR_MAX_TEXTURE_2D_SIZE;
181 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
182 return SWR_MAX_TEXTURE_3D_LEVELS;
183 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
184 return SWR_MAX_TEXTURE_CUBE_LEVELS;
185 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
186 return MAX_SO_STREAMS;
187 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
188 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
189 return MAX_ATTRIBUTES * 4;
190 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
191 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
192 return 1024;
193 case PIPE_CAP_MAX_VERTEX_STREAMS:
194 return 4;
195 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
196 return 2048;
197 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
198 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
199 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
200 case PIPE_CAP_MIN_TEXEL_OFFSET:
201 return -8;
202 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
203 case PIPE_CAP_MAX_TEXEL_OFFSET:
204 return 7;
205 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
206 return 4;
207 case PIPE_CAP_GLSL_FEATURE_LEVEL:
208 return 330;
209 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
210 return 140;
211 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
212 return 16;
213 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
214 return 64;
215 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
216 return 65536;
217 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
218 return 1;
219 case PIPE_CAP_MAX_VIEWPORTS:
220 return KNOB_NUM_VIEWPORTS_SCISSORS;
221 case PIPE_CAP_ENDIANNESS:
222 return PIPE_ENDIAN_NATIVE;
223 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
224 return 0;
225
226 /* supported features */
227 case PIPE_CAP_NPOT_TEXTURES:
228 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
229 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
230 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
231 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
232 case PIPE_CAP_VERTEX_SHADER_SATURATE:
233 case PIPE_CAP_POINT_SPRITE:
234 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
235 case PIPE_CAP_OCCLUSION_QUERY:
236 case PIPE_CAP_QUERY_TIME_ELAPSED:
237 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
238 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
239 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
240 case PIPE_CAP_TEXTURE_SWIZZLE:
241 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
242 case PIPE_CAP_INDEP_BLEND_ENABLE:
243 case PIPE_CAP_INDEP_BLEND_FUNC:
244 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
245 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
246 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
247 case PIPE_CAP_DEPTH_CLIP_DISABLE:
248 case PIPE_CAP_PRIMITIVE_RESTART:
249 case PIPE_CAP_TGSI_INSTANCEID:
250 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
251 case PIPE_CAP_START_INSTANCE:
252 case PIPE_CAP_SEAMLESS_CUBE_MAP:
253 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
254 case PIPE_CAP_CONDITIONAL_RENDER:
255 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
256 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
257 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
258 case PIPE_CAP_USER_VERTEX_BUFFERS:
259 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
260 case PIPE_CAP_QUERY_TIMESTAMP:
261 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
262 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
263 case PIPE_CAP_DRAW_INDIRECT:
264 case PIPE_CAP_UMA:
265 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
266 case PIPE_CAP_CLIP_HALFZ:
267 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
268 case PIPE_CAP_DEPTH_BOUNDS_TEST:
269 case PIPE_CAP_CLEAR_TEXTURE:
270 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
271 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
272 case PIPE_CAP_CULL_DISTANCE:
273 case PIPE_CAP_CUBE_MAP_ARRAY:
274 case PIPE_CAP_DOUBLES:
275 case PIPE_CAP_TEXTURE_QUERY_LOD:
276 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
277 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
278 return 1;
279
280 /* MSAA support
281 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
282 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
283 case PIPE_CAP_TEXTURE_MULTISAMPLE:
284 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
285 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
286 case PIPE_CAP_FAKE_SW_MSAA:
287 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
288
289 /* fetch jit change for 2-4GB buffers requires alignment */
290 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
291 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
292 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
293 return 1;
294
295 /* unsupported features */
296 case PIPE_CAP_ANISOTROPIC_FILTER:
297 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
298 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
299 case PIPE_CAP_SHADER_STENCIL_EXPORT:
300 case PIPE_CAP_TEXTURE_BARRIER:
301 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
302 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
303 case PIPE_CAP_COMPUTE:
304 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
305 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
306 case PIPE_CAP_TGSI_TEXCOORD:
307 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
308 case PIPE_CAP_TEXTURE_GATHER_SM5:
309 case PIPE_CAP_SAMPLE_SHADING:
310 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
311 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
312 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
313 case PIPE_CAP_SAMPLER_VIEW_TARGET:
314 case PIPE_CAP_VERTEXID_NOBASE:
315 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
316 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
317 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
318 case PIPE_CAP_TGSI_TXQS:
319 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
320 case PIPE_CAP_SHAREABLE_SHADERS:
321 case PIPE_CAP_DRAW_PARAMETERS:
322 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
323 case PIPE_CAP_MULTI_DRAW_INDIRECT:
324 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
325 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
326 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
327 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
328 case PIPE_CAP_INVALIDATE_BUFFER:
329 case PIPE_CAP_GENERATE_MIPMAP:
330 case PIPE_CAP_STRING_MARKER:
331 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
332 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
333 case PIPE_CAP_QUERY_BUFFER_OBJECT:
334 case PIPE_CAP_QUERY_MEMORY_INFO:
335 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
336 case PIPE_CAP_PCI_GROUP:
337 case PIPE_CAP_PCI_BUS:
338 case PIPE_CAP_PCI_DEVICE:
339 case PIPE_CAP_PCI_FUNCTION:
340 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
341 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
342 case PIPE_CAP_TGSI_VOTE:
343 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
344 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
345 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
346 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
347 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
348 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
349 case PIPE_CAP_NATIVE_FENCE_FD:
350 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
351 case PIPE_CAP_FBFETCH:
352 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
353 case PIPE_CAP_INT64:
354 case PIPE_CAP_INT64_DIVMOD:
355 case PIPE_CAP_TGSI_TEX_TXF_LZ:
356 case PIPE_CAP_TGSI_CLOCK:
357 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
358 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
359 case PIPE_CAP_TGSI_BALLOT:
360 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
361 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
362 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
363 case PIPE_CAP_POST_DEPTH_COVERAGE:
364 case PIPE_CAP_BINDLESS_TEXTURE:
365 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
366 case PIPE_CAP_QUERY_SO_OVERFLOW:
367 case PIPE_CAP_MEMOBJ:
368 case PIPE_CAP_LOAD_CONSTBUF:
369 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
370 case PIPE_CAP_TILE_RASTER_ORDER:
371 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
372 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
373 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
374 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
375 case PIPE_CAP_FENCE_SIGNAL:
376 case PIPE_CAP_CONSTBUF0_FLAGS:
377 case PIPE_CAP_PACKED_UNIFORMS:
378 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
379 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
380 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
381 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
382 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
383 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
384 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
385 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
386 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
387 case PIPE_CAP_TGSI_ATOMINC_WRAP:
388 return 0;
389 case PIPE_CAP_MAX_GS_INVOCATIONS:
390 return 32;
391 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
392 return 1 << 27;
393 case PIPE_CAP_MAX_VARYINGS:
394 return 32;
395
396 case PIPE_CAP_VENDOR_ID:
397 return 0xFFFFFFFF;
398 case PIPE_CAP_DEVICE_ID:
399 return 0xFFFFFFFF;
400 case PIPE_CAP_ACCELERATED:
401 return 0;
402 case PIPE_CAP_VIDEO_MEMORY: {
403 /* XXX: Do we want to return the full amount of system memory ? */
404 uint64_t system_memory;
405
406 if (!os_get_total_physical_memory(&system_memory))
407 return 0;
408
409 return (int)(system_memory >> 20);
410 }
411 default:
412 return u_pipe_screen_get_param_defaults(screen, param);
413 }
414 }
415
416 static int
417 swr_get_shader_param(struct pipe_screen *screen,
418 enum pipe_shader_type shader,
419 enum pipe_shader_cap param)
420 {
421 if (shader == PIPE_SHADER_VERTEX ||
422 shader == PIPE_SHADER_FRAGMENT ||
423 shader == PIPE_SHADER_GEOMETRY)
424 return gallivm_get_shader_param(param);
425
426 // Todo: tesselation, compute
427 return 0;
428 }
429
430
431 static float
432 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
433 {
434 switch (param) {
435 case PIPE_CAPF_MAX_LINE_WIDTH:
436 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
437 case PIPE_CAPF_MAX_POINT_WIDTH:
438 return 255.0; /* arbitrary */
439 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
440 return 0.0;
441 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
442 return 0.0;
443 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
444 return 16.0; /* arbitrary */
445 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
446 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
447 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
448 return 0.0f;
449 }
450 /* should only get here on unhandled cases */
451 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
452 return 0.0;
453 }
454
455 SWR_FORMAT
456 mesa_to_swr_format(enum pipe_format format)
457 {
458 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
459 /* depth / stencil */
460 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
461 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
462 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
463 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
464 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
465
466 /* alpha */
467 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
468 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
469 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
470 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
471
472 /* odd sizes, bgr */
473 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
474 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
475 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
476 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
477 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
478 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
479 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
480 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
481 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
482
483 /* rgb10a2 */
484 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
485 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
486 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
487 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
488 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
489
490 /* rgb10x2 */
491 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
492
493 /* bgr10a2 */
494 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
495 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
496 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
497 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
498 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
499
500 /* bgr10x2 */
501 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
502
503 /* r11g11b10 */
504 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
505
506 /* 32 bits per component */
507 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
508 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
509 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
510 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
511 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
512
513 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
514 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
515 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
516 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
517
518 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
519 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
520 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
521 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
522
523 {PIPE_FORMAT_R32_UINT, R32_UINT},
524 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
525 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
526 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
527
528 {PIPE_FORMAT_R32_SINT, R32_SINT},
529 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
530 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
531 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
532
533 /* 16 bits per component */
534 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
535 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
536 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
537 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
538 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
539
540 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
541 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
542 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
543 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
544
545 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
546 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
547 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
548 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
549
550 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
551 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
552 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
553 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
554
555 {PIPE_FORMAT_R16_UINT, R16_UINT},
556 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
557 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
558 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
559
560 {PIPE_FORMAT_R16_SINT, R16_SINT},
561 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
562 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
563 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
564
565 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
566 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
567 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
568 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
569 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
570
571 /* 8 bits per component */
572 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
573 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
574 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
575 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
576 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
577 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
578 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
579 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
580
581 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
582 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
583 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
584 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
585
586 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
587 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
588 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
589 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
590
591 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
592 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
593 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
594 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
595
596 {PIPE_FORMAT_R8_UINT, R8_UINT},
597 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
598 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
599 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
600
601 {PIPE_FORMAT_R8_SINT, R8_SINT},
602 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
603 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
604 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
605
606 /* These formats are valid for vertex data, but should not be used
607 * for render targets.
608 */
609
610 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
611 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
612 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
613 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
614
615 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
616 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
617 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
618 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
619
620 /* These formats have entries in SWR but don't have Load/StoreTile
621 * implementations. That means these aren't renderable, and thus having
622 * a mapping entry here is detrimental.
623 */
624 /*
625
626 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
627 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
628 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
629 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
630 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
631
632 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
633 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
634
635 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
636 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
637 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
638
639 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
640 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
641 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
642
643 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
644 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
645 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
646 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
647
648 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
649 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
650 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
651 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
652 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
653 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
654 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
655 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
656
657 {PIPE_FORMAT_I8_UINT, I8_UINT},
658 {PIPE_FORMAT_L8_UINT, L8_UINT},
659 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
660
661 {PIPE_FORMAT_I8_SINT, I8_SINT},
662 {PIPE_FORMAT_L8_SINT, L8_SINT},
663 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
664
665 */
666 };
667
668 auto it = mesa2swr.find(format);
669 if (it == mesa2swr.end())
670 return (SWR_FORMAT)-1;
671 else
672 return it->second;
673 }
674
675 static bool
676 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
677 {
678 struct sw_winsys *winsys = screen->winsys;
679 struct sw_displaytarget *dt;
680
681 const unsigned width = align(res->swr.width, res->swr.halign);
682 const unsigned height = align(res->swr.height, res->swr.valign);
683
684 UINT stride;
685 dt = winsys->displaytarget_create(winsys,
686 res->base.bind,
687 res->base.format,
688 width, height,
689 64, NULL,
690 &stride);
691
692 if (dt == NULL)
693 return false;
694
695 void *map = winsys->displaytarget_map(winsys, dt, 0);
696
697 res->display_target = dt;
698 res->swr.xpBaseAddress = (gfxptr_t)map;
699
700 /* Clear the display target surface */
701 if (map)
702 memset(map, 0, height * stride);
703
704 winsys->displaytarget_unmap(winsys, dt);
705
706 return true;
707 }
708
709 static bool
710 swr_texture_layout(struct swr_screen *screen,
711 struct swr_resource *res,
712 bool allocate)
713 {
714 struct pipe_resource *pt = &res->base;
715
716 pipe_format fmt = pt->format;
717 const struct util_format_description *desc = util_format_description(fmt);
718
719 res->has_depth = util_format_has_depth(desc);
720 res->has_stencil = util_format_has_stencil(desc);
721
722 if (res->has_stencil && !res->has_depth)
723 fmt = PIPE_FORMAT_R8_UINT;
724
725 /* We always use the SWR layout. For 2D and 3D textures this looks like:
726 *
727 * |<------- pitch ------->|
728 * +=======================+-------
729 * |Array 0 | ^
730 * | | |
731 * | Level 0 | |
732 * | | |
733 * | | qpitch
734 * +-----------+-----------+ |
735 * | | L2L2L2L2 | |
736 * | Level 1 | L3L3 | |
737 * | | L4 | v
738 * +===========+===========+-------
739 * |Array 1 |
740 * | |
741 * | Level 0 |
742 * | |
743 * | |
744 * +-----------+-----------+
745 * | | L2L2L2L2 |
746 * | Level 1 | L3L3 |
747 * | | L4 |
748 * +===========+===========+
749 *
750 * The overall width in bytes is known as the pitch, while the overall
751 * height in rows is the qpitch. Array slices are laid out logically below
752 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
753 * just invalid for the higher array numbers (since depth is also
754 * minified). 1D and 1D array surfaces are stored effectively the same way,
755 * except that pitch never plays into it. All the levels are logically
756 * adjacent to each other on the X axis. The qpitch becomes the number of
757 * elements between array slices, while the pitch is unused.
758 *
759 * Each level's sizes are subject to the valign and halign settings of the
760 * surface. For compressed formats that swr is unaware of, we will use an
761 * appropriately-sized uncompressed format, and scale the widths/heights.
762 *
763 * This surface is stored inside res->swr. For depth/stencil textures,
764 * res->secondary will have an identically-laid-out but R8_UINT-formatted
765 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
766 * texels, to simplify map/unmap logic which copies the stencil values
767 * in/out.
768 */
769
770 res->swr.width = pt->width0;
771 res->swr.height = pt->height0;
772 res->swr.type = swr_convert_target_type(pt->target);
773 res->swr.tileMode = SWR_TILE_NONE;
774 res->swr.format = mesa_to_swr_format(fmt);
775 res->swr.numSamples = std::max(1u, pt->nr_samples);
776
777 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
778 res->swr.halign = KNOB_MACROTILE_X_DIM;
779 res->swr.valign = KNOB_MACROTILE_Y_DIM;
780
781 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
782 * surface sample count. */
783 if (screen->msaa_force_enable) {
784 res->swr.numSamples = screen->msaa_max_count;
785 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
786 res->swr.numSamples);
787 }
788 } else {
789 res->swr.halign = 1;
790 res->swr.valign = 1;
791 }
792
793 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
794 unsigned width = align(pt->width0, halign);
795 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
796 for (int level = 1; level <= pt->last_level; level++)
797 width += align(u_minify(pt->width0, level), halign);
798 res->swr.pitch = util_format_get_blocksize(fmt);
799 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
800 } else {
801 // The pitch is the overall width of the texture in bytes. Most of the
802 // time this is the pitch of level 0 since all the other levels fit
803 // underneath it. However in some degenerate situations, the width of
804 // level1 + level2 may be larger. In that case, we use those
805 // widths. This can happen if, e.g. halign is 32, and the width of level
806 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
807 // be 32 each, adding up to 64.
808 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
809 if (pt->last_level > 1) {
810 width = std::max<uint32_t>(
811 width,
812 align(u_minify(pt->width0, 1), halign) +
813 align(u_minify(pt->width0, 2), halign));
814 }
815 res->swr.pitch = util_format_get_stride(fmt, width);
816
817 // The qpitch is controlled by either the height of the second LOD, or
818 // the combination of all the later LODs.
819 unsigned height = align(pt->height0, valign);
820 if (pt->last_level == 1) {
821 height += align(u_minify(pt->height0, 1), valign);
822 } else if (pt->last_level > 1) {
823 unsigned level1 = align(u_minify(pt->height0, 1), valign);
824 unsigned level2 = 0;
825 for (int level = 2; level <= pt->last_level; level++) {
826 level2 += align(u_minify(pt->height0, level), valign);
827 }
828 height += std::max(level1, level2);
829 }
830 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
831 }
832
833 if (pt->target == PIPE_TEXTURE_3D)
834 res->swr.depth = pt->depth0;
835 else
836 res->swr.depth = pt->array_size;
837
838 // Fix up swr format if necessary so that LOD offset computation works
839 if (res->swr.format == (SWR_FORMAT)-1) {
840 switch (util_format_get_blocksize(fmt)) {
841 default:
842 unreachable("Unexpected format block size");
843 case 1: res->swr.format = R8_UINT; break;
844 case 2: res->swr.format = R16_UINT; break;
845 case 4: res->swr.format = R32_UINT; break;
846 case 8:
847 if (util_format_is_compressed(fmt))
848 res->swr.format = BC4_UNORM;
849 else
850 res->swr.format = R32G32_UINT;
851 break;
852 case 16:
853 if (util_format_is_compressed(fmt))
854 res->swr.format = BC5_UNORM;
855 else
856 res->swr.format = R32G32B32A32_UINT;
857 break;
858 }
859 }
860
861 for (int level = 0; level <= pt->last_level; level++) {
862 res->mip_offsets[level] =
863 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
864 }
865
866 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
867 res->swr.pitch * res->swr.numSamples;
868
869 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
870 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
871 return false;
872
873 if (allocate) {
874 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
875 if (!res->swr.xpBaseAddress)
876 return false;
877
878 if (res->has_depth && res->has_stencil) {
879 res->secondary = res->swr;
880 res->secondary.format = R8_UINT;
881 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
882
883 for (int level = 0; level <= pt->last_level; level++) {
884 res->secondary_mip_offsets[level] =
885 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
886 }
887
888 total_size = res->secondary.depth * res->secondary.qpitch *
889 res->secondary.pitch * res->secondary.numSamples;
890
891 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
892 if (!res->secondary.xpBaseAddress) {
893 AlignedFree((void *)res->swr.xpBaseAddress);
894 return false;
895 }
896 }
897 }
898
899 return true;
900 }
901
902 static bool
903 swr_can_create_resource(struct pipe_screen *screen,
904 const struct pipe_resource *templat)
905 {
906 struct swr_resource res;
907 memset(&res, 0, sizeof(res));
908 res.base = *templat;
909 return swr_texture_layout(swr_screen(screen), &res, false);
910 }
911
912 /* Helper function that conditionally creates a single-sample resolve resource
913 * and attaches it to main multisample resource. */
914 static bool
915 swr_create_resolve_resource(struct pipe_screen *_screen,
916 struct swr_resource *msaa_res)
917 {
918 struct swr_screen *screen = swr_screen(_screen);
919
920 /* If resource is multisample, create a single-sample resolve resource */
921 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
922 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
923
924 /* Create a single-sample copy of the resource. Copy the original
925 * resource parameters and set flag to prevent recursion when re-calling
926 * resource_create */
927 struct pipe_resource alt_template = msaa_res->base;
928 alt_template.nr_samples = 0;
929 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
930
931 /* Note: Display_target is a special single-sample resource, only the
932 * display_target has been created already. */
933 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
934 | PIPE_BIND_SHARED)) {
935 /* Allocate the multisample buffers. */
936 if (!swr_texture_layout(screen, msaa_res, true))
937 return false;
938
939 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
940 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
941 alt_template.bind = PIPE_BIND_RENDER_TARGET;
942 }
943
944 /* Allocate single-sample resolve surface */
945 struct pipe_resource *alt;
946 alt = _screen->resource_create(_screen, &alt_template);
947 if (!alt)
948 return false;
949
950 /* Attach it to the multisample resource */
951 msaa_res->resolve_target = alt;
952
953 /* Hang resolve surface state off the multisample surface state to so
954 * StoreTiles knows where to resolve the surface. */
955 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
956 }
957
958 return true; /* success */
959 }
960
961 static struct pipe_resource *
962 swr_resource_create(struct pipe_screen *_screen,
963 const struct pipe_resource *templat)
964 {
965 struct swr_screen *screen = swr_screen(_screen);
966 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
967 if (!res)
968 return NULL;
969
970 res->base = *templat;
971 pipe_reference_init(&res->base.reference, 1);
972 res->base.screen = &screen->base;
973
974 if (swr_resource_is_texture(&res->base)) {
975 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
976 | PIPE_BIND_SHARED)) {
977 /* displayable surface
978 * first call swr_texture_layout without allocating to finish
979 * filling out the SWR_SURFACE_STATE in res */
980 swr_texture_layout(screen, res, false);
981 if (!swr_displaytarget_layout(screen, res))
982 goto fail;
983 } else {
984 /* texture map */
985 if (!swr_texture_layout(screen, res, true))
986 goto fail;
987 }
988
989 /* If resource was multisample, create resolve resource and attach
990 * it to multisample resource. */
991 if (!swr_create_resolve_resource(_screen, res))
992 goto fail;
993
994 } else {
995 /* other data (vertex buffer, const buffer, etc) */
996 assert(util_format_get_blocksize(templat->format) == 1);
997 assert(templat->height0 == 1);
998 assert(templat->depth0 == 1);
999 assert(templat->last_level == 0);
1000
1001 /* Easiest to just call swr_texture_layout, as it sets up
1002 * SWR_SURFACE_STATE in res */
1003 if (!swr_texture_layout(screen, res, true))
1004 goto fail;
1005 }
1006
1007 return &res->base;
1008
1009 fail:
1010 FREE(res);
1011 return NULL;
1012 }
1013
1014 static void
1015 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
1016 {
1017 struct swr_screen *screen = swr_screen(p_screen);
1018 struct swr_resource *spr = swr_resource(pt);
1019
1020 if (spr->display_target) {
1021 /* If resource is display target, winsys manages the buffer and will
1022 * free it on displaytarget_destroy. */
1023 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1024
1025 struct sw_winsys *winsys = screen->winsys;
1026 winsys->displaytarget_destroy(winsys, spr->display_target);
1027
1028 if (spr->swr.numSamples > 1) {
1029 /* Free an attached resolve resource */
1030 struct swr_resource *alt = swr_resource(spr->resolve_target);
1031 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1032
1033 /* Free multisample buffer */
1034 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1035 }
1036 } else {
1037 /* For regular resources, defer deletion */
1038 swr_resource_unused(pt);
1039
1040 if (spr->swr.numSamples > 1) {
1041 /* Free an attached resolve resource */
1042 struct swr_resource *alt = swr_resource(spr->resolve_target);
1043 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1044 }
1045
1046 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1047 swr_fence_work_free(screen->flush_fence,
1048 (void*)(spr->secondary.xpBaseAddress), true);
1049
1050 /* If work queue grows too large, submit a fence to force queue to
1051 * drain. This is mainly to decrease the amount of memory used by the
1052 * piglit streaming-texture-leak test */
1053 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1054 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1055 }
1056
1057 FREE(spr);
1058 }
1059
1060
1061 static void
1062 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1063 struct pipe_resource *resource,
1064 unsigned level,
1065 unsigned layer,
1066 void *context_private,
1067 struct pipe_box *sub_box)
1068 {
1069 struct swr_screen *screen = swr_screen(p_screen);
1070 struct sw_winsys *winsys = screen->winsys;
1071 struct swr_resource *spr = swr_resource(resource);
1072 struct pipe_context *pipe = screen->pipe;
1073 struct swr_context *ctx = swr_context(pipe);
1074
1075 if (pipe) {
1076 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1077 swr_resource_unused(resource);
1078 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1079 }
1080
1081 /* Multisample resolved into resolve_target at flush with store_resource */
1082 if (pipe && spr->swr.numSamples > 1) {
1083 struct pipe_resource *resolve_target = spr->resolve_target;
1084
1085 /* Once resolved, copy into display target */
1086 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1087
1088 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1089 PIPE_TRANSFER_WRITE);
1090 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1091 winsys->displaytarget_unmap(winsys, spr->display_target);
1092 }
1093
1094 debug_assert(spr->display_target);
1095 if (spr->display_target)
1096 winsys->displaytarget_display(
1097 winsys, spr->display_target, context_private, sub_box);
1098 }
1099
1100
1101 void
1102 swr_destroy_screen_internal(struct swr_screen **screen)
1103 {
1104 struct pipe_screen *p_screen = &(*screen)->base;
1105
1106 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1107 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1108
1109 JitDestroyContext((*screen)->hJitMgr);
1110
1111 if ((*screen)->pLibrary)
1112 util_dl_close((*screen)->pLibrary);
1113
1114 FREE(*screen);
1115 *screen = NULL;
1116 }
1117
1118
1119 static void
1120 swr_destroy_screen(struct pipe_screen *p_screen)
1121 {
1122 struct swr_screen *screen = swr_screen(p_screen);
1123 struct sw_winsys *winsys = screen->winsys;
1124
1125 fprintf(stderr, "SWR destroy screen!\n");
1126
1127 if (winsys->destroy)
1128 winsys->destroy(winsys);
1129
1130 swr_destroy_screen_internal(&screen);
1131 }
1132
1133
1134 static void
1135 swr_validate_env_options(struct swr_screen *screen)
1136 {
1137 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1138 * copied to scratch space on a draw. Past this, the draw will access
1139 * user-buffer directly and then block. This is faster than queuing many
1140 * large client draws. */
1141 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1142 int client_copy_limit =
1143 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1144 if (client_copy_limit > 0)
1145 screen->client_copy_limit = client_copy_limit;
1146
1147 /* XXX msaa under development, disable by default for now */
1148 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1149
1150 /* validate env override values, within range and power of 2 */
1151 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1152 if (msaa_max_count != 1) {
1153 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1154 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1155 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1156 fprintf(stderr, "must be power of 2 between 1 and %d" \
1157 " (or 1 to disable msaa)\n",
1158 SWR_MAX_NUM_MULTISAMPLES);
1159 msaa_max_count = 1;
1160 }
1161
1162 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1163 if (msaa_max_count == 1)
1164 fprintf(stderr, "(msaa disabled)\n");
1165
1166 screen->msaa_max_count = msaa_max_count;
1167 }
1168
1169 screen->msaa_force_enable = debug_get_bool_option(
1170 "SWR_MSAA_FORCE_ENABLE", false);
1171 if (screen->msaa_force_enable)
1172 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1173 }
1174
1175
1176 struct pipe_screen *
1177 swr_create_screen_internal(struct sw_winsys *winsys)
1178 {
1179 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1180
1181 if (!screen)
1182 return NULL;
1183
1184 if (!lp_build_init()) {
1185 FREE(screen);
1186 return NULL;
1187 }
1188
1189 screen->winsys = winsys;
1190 screen->base.get_name = swr_get_name;
1191 screen->base.get_vendor = swr_get_vendor;
1192 screen->base.is_format_supported = swr_is_format_supported;
1193 screen->base.context_create = swr_create_context;
1194 screen->base.can_create_resource = swr_can_create_resource;
1195
1196 screen->base.destroy = swr_destroy_screen;
1197 screen->base.get_param = swr_get_param;
1198 screen->base.get_shader_param = swr_get_shader_param;
1199 screen->base.get_paramf = swr_get_paramf;
1200
1201 screen->base.resource_create = swr_resource_create;
1202 screen->base.resource_destroy = swr_resource_destroy;
1203
1204 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1205
1206 // Pass in "" for architecture for run-time determination
1207 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1208
1209 swr_fence_init(&screen->base);
1210
1211 swr_validate_env_options(screen);
1212
1213 return &screen->base;
1214 }