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[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/format/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "frontend/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 snprintf(buf, sizeof(buf), "SWR (LLVM " MESA_LLVM_VERSION_STRING ", %u bits)",
73 lp_native_vector_width);
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static bool
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return false;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return false;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return false;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return false;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return false;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside gallium frontends.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return false;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return false;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return false;
142 }
143
144 if (bind & PIPE_BIND_VERTEX_BUFFER) {
145 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) {
146 return false;
147 }
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC ||
151 format_desc->layout == UTIL_FORMAT_LAYOUT_FXT1)
152 {
153 return false;
154 }
155
156 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
157 format != PIPE_FORMAT_ETC1_RGB8) {
158 return false;
159 }
160
161 if ((bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) &&
162 ((bind & PIPE_BIND_DISPLAY_TARGET) == 0)) {
163 /* Disable all 3-channel formats, where channel size != 32 bits.
164 * In some cases we run into crashes (in generate_unswizzled_blend()),
165 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
166 * In any case, disabling the shallower 3-channel formats avoids a
167 * number of issues with GL_ARB_copy_image support.
168 */
169 if (format_desc->is_array &&
170 format_desc->nr_channels == 3 &&
171 format_desc->block.bits != 96) {
172 return false;
173 }
174 }
175
176 return TRUE;
177 }
178
179 static int
180 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
181 {
182 switch (param) {
183 /* limits */
184 case PIPE_CAP_MAX_RENDER_TARGETS:
185 return PIPE_MAX_COLOR_BUFS;
186 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
187 return SWR_MAX_TEXTURE_2D_SIZE;
188 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
189 return SWR_MAX_TEXTURE_3D_LEVELS;
190 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
191 return SWR_MAX_TEXTURE_CUBE_LEVELS;
192 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
193 return MAX_SO_STREAMS;
194 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
195 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
196 return MAX_ATTRIBUTES * 4;
197 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
198 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
199 return 1024;
200 case PIPE_CAP_MAX_VERTEX_STREAMS:
201 return 4;
202 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
203 return 2048;
204 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
205 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
206 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
207 case PIPE_CAP_MIN_TEXEL_OFFSET:
208 return -8;
209 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
210 case PIPE_CAP_MAX_TEXEL_OFFSET:
211 return 7;
212 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
213 return 4;
214 case PIPE_CAP_GLSL_FEATURE_LEVEL:
215 return 330;
216 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
217 return 140;
218 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
219 return 16;
220 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
221 return 64;
222 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
223 return 65536;
224 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
225 return 1;
226 case PIPE_CAP_MAX_VIEWPORTS:
227 return KNOB_NUM_VIEWPORTS_SCISSORS;
228 case PIPE_CAP_ENDIANNESS:
229 return PIPE_ENDIAN_NATIVE;
230 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
231 return 0;
232
233 /* supported features */
234 case PIPE_CAP_NPOT_TEXTURES:
235 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
236 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
237 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
238 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
239 case PIPE_CAP_VERTEX_SHADER_SATURATE:
240 case PIPE_CAP_POINT_SPRITE:
241 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
242 case PIPE_CAP_OCCLUSION_QUERY:
243 case PIPE_CAP_QUERY_TIME_ELAPSED:
244 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
245 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
246 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
247 case PIPE_CAP_TEXTURE_SWIZZLE:
248 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
249 case PIPE_CAP_INDEP_BLEND_ENABLE:
250 case PIPE_CAP_INDEP_BLEND_FUNC:
251 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
252 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
254 case PIPE_CAP_DEPTH_CLIP_DISABLE:
255 case PIPE_CAP_PRIMITIVE_RESTART:
256 case PIPE_CAP_TGSI_INSTANCEID:
257 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
258 case PIPE_CAP_START_INSTANCE:
259 case PIPE_CAP_SEAMLESS_CUBE_MAP:
260 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
261 case PIPE_CAP_CONDITIONAL_RENDER:
262 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
263 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
264 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
265 case PIPE_CAP_USER_VERTEX_BUFFERS:
266 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
267 case PIPE_CAP_QUERY_TIMESTAMP:
268 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
269 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
270 case PIPE_CAP_DRAW_INDIRECT:
271 case PIPE_CAP_UMA:
272 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
273 case PIPE_CAP_CLIP_HALFZ:
274 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
275 case PIPE_CAP_DEPTH_BOUNDS_TEST:
276 case PIPE_CAP_CLEAR_TEXTURE:
277 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
278 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
279 case PIPE_CAP_CULL_DISTANCE:
280 case PIPE_CAP_CUBE_MAP_ARRAY:
281 case PIPE_CAP_DOUBLES:
282 case PIPE_CAP_TEXTURE_QUERY_LOD:
283 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
284 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
285 case PIPE_CAP_QUERY_SO_OVERFLOW:
286 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
287 return 1;
288
289 /* MSAA support
290 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
291 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
292 case PIPE_CAP_TEXTURE_MULTISAMPLE:
293 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
294 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
295 case PIPE_CAP_FAKE_SW_MSAA:
296 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
297
298 /* fetch jit change for 2-4GB buffers requires alignment */
299 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
300 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
301 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
302 return 1;
303
304 /* unsupported features */
305 case PIPE_CAP_ANISOTROPIC_FILTER:
306 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
307 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
308 case PIPE_CAP_SHADER_STENCIL_EXPORT:
309 case PIPE_CAP_TEXTURE_BARRIER:
310 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
311 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
312 case PIPE_CAP_COMPUTE:
313 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
314 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
315 case PIPE_CAP_TGSI_TEXCOORD:
316 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
317 case PIPE_CAP_TEXTURE_GATHER_SM5:
318 case PIPE_CAP_SAMPLE_SHADING:
319 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
320 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
321 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
322 case PIPE_CAP_SAMPLER_VIEW_TARGET:
323 case PIPE_CAP_VERTEXID_NOBASE:
324 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
325 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
326 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
327 case PIPE_CAP_TGSI_TXQS:
328 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
329 case PIPE_CAP_SHAREABLE_SHADERS:
330 case PIPE_CAP_DRAW_PARAMETERS:
331 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
332 case PIPE_CAP_MULTI_DRAW_INDIRECT:
333 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
334 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
335 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
336 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
337 case PIPE_CAP_INVALIDATE_BUFFER:
338 case PIPE_CAP_GENERATE_MIPMAP:
339 case PIPE_CAP_STRING_MARKER:
340 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
341 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
342 case PIPE_CAP_QUERY_BUFFER_OBJECT:
343 case PIPE_CAP_QUERY_MEMORY_INFO:
344 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
345 case PIPE_CAP_PCI_GROUP:
346 case PIPE_CAP_PCI_BUS:
347 case PIPE_CAP_PCI_DEVICE:
348 case PIPE_CAP_PCI_FUNCTION:
349 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
350 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
351 case PIPE_CAP_TGSI_VOTE:
352 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
353 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
354 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
355 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
356 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
357 case PIPE_CAP_NATIVE_FENCE_FD:
358 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
359 case PIPE_CAP_FBFETCH:
360 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
361 case PIPE_CAP_INT64:
362 case PIPE_CAP_INT64_DIVMOD:
363 case PIPE_CAP_TGSI_TEX_TXF_LZ:
364 case PIPE_CAP_TGSI_CLOCK:
365 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
366 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
367 case PIPE_CAP_TGSI_BALLOT:
368 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
369 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
370 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
371 case PIPE_CAP_POST_DEPTH_COVERAGE:
372 case PIPE_CAP_BINDLESS_TEXTURE:
373 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
374 case PIPE_CAP_MEMOBJ:
375 case PIPE_CAP_LOAD_CONSTBUF:
376 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
377 case PIPE_CAP_TILE_RASTER_ORDER:
378 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
379 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
380 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
381 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
382 case PIPE_CAP_FENCE_SIGNAL:
383 case PIPE_CAP_CONSTBUF0_FLAGS:
384 case PIPE_CAP_PACKED_UNIFORMS:
385 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
386 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
387 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
388 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
389 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
390 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
391 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
392 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
393 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
394 case PIPE_CAP_TGSI_ATOMINC_WRAP:
395 return 0;
396 case PIPE_CAP_MAX_GS_INVOCATIONS:
397 return 32;
398 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
399 return 1 << 27;
400 case PIPE_CAP_MAX_VARYINGS:
401 return 32;
402
403 case PIPE_CAP_VENDOR_ID:
404 return 0xFFFFFFFF;
405 case PIPE_CAP_DEVICE_ID:
406 return 0xFFFFFFFF;
407 case PIPE_CAP_ACCELERATED:
408 return 0;
409 case PIPE_CAP_VIDEO_MEMORY: {
410 /* XXX: Do we want to return the full amount of system memory ? */
411 uint64_t system_memory;
412
413 if (!os_get_total_physical_memory(&system_memory))
414 return 0;
415
416 return (int)(system_memory >> 20);
417 }
418 default:
419 return u_pipe_screen_get_param_defaults(screen, param);
420 }
421 }
422
423 static int
424 swr_get_shader_param(struct pipe_screen *screen,
425 enum pipe_shader_type shader,
426 enum pipe_shader_cap param)
427 {
428 if (shader == PIPE_SHADER_VERTEX ||
429 shader == PIPE_SHADER_FRAGMENT ||
430 shader == PIPE_SHADER_GEOMETRY
431 || shader == PIPE_SHADER_TESS_CTRL ||
432 shader == PIPE_SHADER_TESS_EVAL
433 )
434 return gallivm_get_shader_param(param);
435
436 // Todo: compute
437 return 0;
438 }
439
440
441 static float
442 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
443 {
444 switch (param) {
445 case PIPE_CAPF_MAX_LINE_WIDTH:
446 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
447 case PIPE_CAPF_MAX_POINT_WIDTH:
448 return 255.0; /* arbitrary */
449 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
450 return 0.0;
451 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
452 return 0.0;
453 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
454 return 16.0; /* arbitrary */
455 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
456 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
457 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
458 return 0.0f;
459 }
460 /* should only get here on unhandled cases */
461 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
462 return 0.0;
463 }
464
465 SWR_FORMAT
466 mesa_to_swr_format(enum pipe_format format)
467 {
468 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
469 /* depth / stencil */
470 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
471 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
472 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
473 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
474 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
475
476 /* alpha */
477 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
478 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
479 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
480 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
481
482 /* odd sizes, bgr */
483 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
484 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
485 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
486 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
487 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
488 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
489 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
490 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
491 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
492
493 /* rgb10a2 */
494 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
495 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
496 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
497 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
498 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
499
500 /* rgb10x2 */
501 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
502
503 /* bgr10a2 */
504 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
505 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
506 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
507 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
508 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
509
510 /* bgr10x2 */
511 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
512
513 /* r11g11b10 */
514 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
515
516 /* 32 bits per component */
517 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
518 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
519 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
520 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
521 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
522
523 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
524 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
525 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
526 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
527
528 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
529 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
530 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
531 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
532
533 {PIPE_FORMAT_R32_UINT, R32_UINT},
534 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
535 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
536 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
537
538 {PIPE_FORMAT_R32_SINT, R32_SINT},
539 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
540 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
541 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
542
543 /* 16 bits per component */
544 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
545 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
546 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
547 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
548 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
549
550 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
551 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
552 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
553 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
554
555 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
556 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
557 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
558 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
559
560 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
561 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
562 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
563 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
564
565 {PIPE_FORMAT_R16_UINT, R16_UINT},
566 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
567 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
568 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
569
570 {PIPE_FORMAT_R16_SINT, R16_SINT},
571 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
572 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
573 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
574
575 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
576 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
577 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
578 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
579 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
580
581 /* 8 bits per component */
582 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
583 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
584 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
585 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
586 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
587 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
588 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
589 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
590
591 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
592 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
593 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
594 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
595
596 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
597 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
598 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
599 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
600
601 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
602 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
603 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
604 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
605
606 {PIPE_FORMAT_R8_UINT, R8_UINT},
607 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
608 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
609 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
610
611 {PIPE_FORMAT_R8_SINT, R8_SINT},
612 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
613 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
614 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
615
616 /* These formats are valid for vertex data, but should not be used
617 * for render targets.
618 */
619
620 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
621 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
622 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
623 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
624
625 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
626 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
627 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
628 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
629
630 /* These formats have entries in SWR but don't have Load/StoreTile
631 * implementations. That means these aren't renderable, and thus having
632 * a mapping entry here is detrimental.
633 */
634 /*
635
636 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
637 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
638 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
639 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
640 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
641
642 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
643 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
644
645 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
646 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
647 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
648
649 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
650 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
651 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
652
653 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
654 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
655 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
656 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
657
658 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
659 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
660 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
661 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
662 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
663 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
664 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
665 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
666
667 {PIPE_FORMAT_I8_UINT, I8_UINT},
668 {PIPE_FORMAT_L8_UINT, L8_UINT},
669 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
670
671 {PIPE_FORMAT_I8_SINT, I8_SINT},
672 {PIPE_FORMAT_L8_SINT, L8_SINT},
673 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
674
675 */
676 };
677
678 auto it = mesa2swr.find(format);
679 if (it == mesa2swr.end())
680 return (SWR_FORMAT)-1;
681 else
682 return it->second;
683 }
684
685 static bool
686 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
687 {
688 struct sw_winsys *winsys = screen->winsys;
689 struct sw_displaytarget *dt;
690
691 const unsigned width = align(res->swr.width, res->swr.halign);
692 const unsigned height = align(res->swr.height, res->swr.valign);
693
694 UINT stride;
695 dt = winsys->displaytarget_create(winsys,
696 res->base.bind,
697 res->base.format,
698 width, height,
699 64, NULL,
700 &stride);
701
702 if (dt == NULL)
703 return false;
704
705 void *map = winsys->displaytarget_map(winsys, dt, 0);
706
707 res->display_target = dt;
708 res->swr.xpBaseAddress = (gfxptr_t)map;
709
710 /* Clear the display target surface */
711 if (map)
712 memset(map, 0, height * stride);
713
714 winsys->displaytarget_unmap(winsys, dt);
715
716 return true;
717 }
718
719 static bool
720 swr_texture_layout(struct swr_screen *screen,
721 struct swr_resource *res,
722 bool allocate)
723 {
724 struct pipe_resource *pt = &res->base;
725
726 pipe_format fmt = pt->format;
727 const struct util_format_description *desc = util_format_description(fmt);
728
729 res->has_depth = util_format_has_depth(desc);
730 res->has_stencil = util_format_has_stencil(desc);
731
732 if (res->has_stencil && !res->has_depth)
733 fmt = PIPE_FORMAT_R8_UINT;
734
735 /* We always use the SWR layout. For 2D and 3D textures this looks like:
736 *
737 * |<------- pitch ------->|
738 * +=======================+-------
739 * |Array 0 | ^
740 * | | |
741 * | Level 0 | |
742 * | | |
743 * | | qpitch
744 * +-----------+-----------+ |
745 * | | L2L2L2L2 | |
746 * | Level 1 | L3L3 | |
747 * | | L4 | v
748 * +===========+===========+-------
749 * |Array 1 |
750 * | |
751 * | Level 0 |
752 * | |
753 * | |
754 * +-----------+-----------+
755 * | | L2L2L2L2 |
756 * | Level 1 | L3L3 |
757 * | | L4 |
758 * +===========+===========+
759 *
760 * The overall width in bytes is known as the pitch, while the overall
761 * height in rows is the qpitch. Array slices are laid out logically below
762 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
763 * just invalid for the higher array numbers (since depth is also
764 * minified). 1D and 1D array surfaces are stored effectively the same way,
765 * except that pitch never plays into it. All the levels are logically
766 * adjacent to each other on the X axis. The qpitch becomes the number of
767 * elements between array slices, while the pitch is unused.
768 *
769 * Each level's sizes are subject to the valign and halign settings of the
770 * surface. For compressed formats that swr is unaware of, we will use an
771 * appropriately-sized uncompressed format, and scale the widths/heights.
772 *
773 * This surface is stored inside res->swr. For depth/stencil textures,
774 * res->secondary will have an identically-laid-out but R8_UINT-formatted
775 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
776 * texels, to simplify map/unmap logic which copies the stencil values
777 * in/out.
778 */
779
780 res->swr.width = pt->width0;
781 res->swr.height = pt->height0;
782 res->swr.type = swr_convert_target_type(pt->target);
783 res->swr.tileMode = SWR_TILE_NONE;
784 res->swr.format = mesa_to_swr_format(fmt);
785 res->swr.numSamples = std::max(1u, pt->nr_samples);
786
787 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
788 res->swr.halign = KNOB_MACROTILE_X_DIM;
789 res->swr.valign = KNOB_MACROTILE_Y_DIM;
790
791 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
792 * surface sample count. */
793 if (screen->msaa_force_enable) {
794 res->swr.numSamples = screen->msaa_max_count;
795 swr_print_info("swr_texture_layout: forcing sample count: %d\n",
796 res->swr.numSamples);
797 }
798 } else {
799 res->swr.halign = 1;
800 res->swr.valign = 1;
801 }
802
803 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
804 unsigned width = align(pt->width0, halign);
805 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
806 for (int level = 1; level <= pt->last_level; level++)
807 width += align(u_minify(pt->width0, level), halign);
808 res->swr.pitch = util_format_get_blocksize(fmt);
809 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
810 } else {
811 // The pitch is the overall width of the texture in bytes. Most of the
812 // time this is the pitch of level 0 since all the other levels fit
813 // underneath it. However in some degenerate situations, the width of
814 // level1 + level2 may be larger. In that case, we use those
815 // widths. This can happen if, e.g. halign is 32, and the width of level
816 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
817 // be 32 each, adding up to 64.
818 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
819 if (pt->last_level > 1) {
820 width = std::max<uint32_t>(
821 width,
822 align(u_minify(pt->width0, 1), halign) +
823 align(u_minify(pt->width0, 2), halign));
824 }
825 res->swr.pitch = util_format_get_stride(fmt, width);
826
827 // The qpitch is controlled by either the height of the second LOD, or
828 // the combination of all the later LODs.
829 unsigned height = align(pt->height0, valign);
830 if (pt->last_level == 1) {
831 height += align(u_minify(pt->height0, 1), valign);
832 } else if (pt->last_level > 1) {
833 unsigned level1 = align(u_minify(pt->height0, 1), valign);
834 unsigned level2 = 0;
835 for (int level = 2; level <= pt->last_level; level++) {
836 level2 += align(u_minify(pt->height0, level), valign);
837 }
838 height += std::max(level1, level2);
839 }
840 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
841 }
842
843 if (pt->target == PIPE_TEXTURE_3D)
844 res->swr.depth = pt->depth0;
845 else
846 res->swr.depth = pt->array_size;
847
848 // Fix up swr format if necessary so that LOD offset computation works
849 if (res->swr.format == (SWR_FORMAT)-1) {
850 switch (util_format_get_blocksize(fmt)) {
851 default:
852 unreachable("Unexpected format block size");
853 case 1: res->swr.format = R8_UINT; break;
854 case 2: res->swr.format = R16_UINT; break;
855 case 4: res->swr.format = R32_UINT; break;
856 case 8:
857 if (util_format_is_compressed(fmt))
858 res->swr.format = BC4_UNORM;
859 else
860 res->swr.format = R32G32_UINT;
861 break;
862 case 16:
863 if (util_format_is_compressed(fmt))
864 res->swr.format = BC5_UNORM;
865 else
866 res->swr.format = R32G32B32A32_UINT;
867 break;
868 }
869 }
870
871 for (int level = 0; level <= pt->last_level; level++) {
872 res->mip_offsets[level] =
873 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
874 }
875
876 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
877 res->swr.pitch * res->swr.numSamples;
878
879 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
880 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
881 return false;
882
883 if (allocate) {
884 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
885 if (!res->swr.xpBaseAddress)
886 return false;
887
888 if (res->has_depth && res->has_stencil) {
889 res->secondary = res->swr;
890 res->secondary.format = R8_UINT;
891 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
892
893 for (int level = 0; level <= pt->last_level; level++) {
894 res->secondary_mip_offsets[level] =
895 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
896 }
897
898 total_size = res->secondary.depth * res->secondary.qpitch *
899 res->secondary.pitch * res->secondary.numSamples;
900
901 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
902 if (!res->secondary.xpBaseAddress) {
903 AlignedFree((void *)res->swr.xpBaseAddress);
904 return false;
905 }
906 }
907 }
908
909 return true;
910 }
911
912 static bool
913 swr_can_create_resource(struct pipe_screen *screen,
914 const struct pipe_resource *templat)
915 {
916 struct swr_resource res;
917 memset(&res, 0, sizeof(res));
918 res.base = *templat;
919 return swr_texture_layout(swr_screen(screen), &res, false);
920 }
921
922 /* Helper function that conditionally creates a single-sample resolve resource
923 * and attaches it to main multisample resource. */
924 static bool
925 swr_create_resolve_resource(struct pipe_screen *_screen,
926 struct swr_resource *msaa_res)
927 {
928 struct swr_screen *screen = swr_screen(_screen);
929
930 /* If resource is multisample, create a single-sample resolve resource */
931 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
932 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
933
934 /* Create a single-sample copy of the resource. Copy the original
935 * resource parameters and set flag to prevent recursion when re-calling
936 * resource_create */
937 struct pipe_resource alt_template = msaa_res->base;
938 alt_template.nr_samples = 0;
939 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
940
941 /* Note: Display_target is a special single-sample resource, only the
942 * display_target has been created already. */
943 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
944 | PIPE_BIND_SHARED)) {
945 /* Allocate the multisample buffers. */
946 if (!swr_texture_layout(screen, msaa_res, true))
947 return false;
948
949 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
950 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
951 alt_template.bind = PIPE_BIND_RENDER_TARGET;
952 }
953
954 /* Allocate single-sample resolve surface */
955 struct pipe_resource *alt;
956 alt = _screen->resource_create(_screen, &alt_template);
957 if (!alt)
958 return false;
959
960 /* Attach it to the multisample resource */
961 msaa_res->resolve_target = alt;
962
963 /* Hang resolve surface state off the multisample surface state to so
964 * StoreTiles knows where to resolve the surface. */
965 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
966 }
967
968 return true; /* success */
969 }
970
971 static struct pipe_resource *
972 swr_resource_create(struct pipe_screen *_screen,
973 const struct pipe_resource *templat)
974 {
975 struct swr_screen *screen = swr_screen(_screen);
976 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
977 if (!res)
978 return NULL;
979
980 res->base = *templat;
981 pipe_reference_init(&res->base.reference, 1);
982 res->base.screen = &screen->base;
983
984 if (swr_resource_is_texture(&res->base)) {
985 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
986 | PIPE_BIND_SHARED)) {
987 /* displayable surface
988 * first call swr_texture_layout without allocating to finish
989 * filling out the SWR_SURFACE_STATE in res */
990 swr_texture_layout(screen, res, false);
991 if (!swr_displaytarget_layout(screen, res))
992 goto fail;
993 } else {
994 /* texture map */
995 if (!swr_texture_layout(screen, res, true))
996 goto fail;
997 }
998
999 /* If resource was multisample, create resolve resource and attach
1000 * it to multisample resource. */
1001 if (!swr_create_resolve_resource(_screen, res))
1002 goto fail;
1003
1004 } else {
1005 /* other data (vertex buffer, const buffer, etc) */
1006 assert(util_format_get_blocksize(templat->format) == 1);
1007 assert(templat->height0 == 1);
1008 assert(templat->depth0 == 1);
1009 assert(templat->last_level == 0);
1010
1011 /* Easiest to just call swr_texture_layout, as it sets up
1012 * SWR_SURFACE_STATE in res */
1013 if (!swr_texture_layout(screen, res, true))
1014 goto fail;
1015 }
1016
1017 return &res->base;
1018
1019 fail:
1020 FREE(res);
1021 return NULL;
1022 }
1023
1024 static void
1025 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
1026 {
1027 struct swr_screen *screen = swr_screen(p_screen);
1028 struct swr_resource *spr = swr_resource(pt);
1029
1030 if (spr->display_target) {
1031 /* If resource is display target, winsys manages the buffer and will
1032 * free it on displaytarget_destroy. */
1033 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1034
1035 struct sw_winsys *winsys = screen->winsys;
1036 winsys->displaytarget_destroy(winsys, spr->display_target);
1037
1038 if (spr->swr.numSamples > 1) {
1039 /* Free an attached resolve resource */
1040 struct swr_resource *alt = swr_resource(spr->resolve_target);
1041 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1042
1043 /* Free multisample buffer */
1044 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1045 }
1046 } else {
1047 /* For regular resources, defer deletion */
1048 swr_resource_unused(pt);
1049
1050 if (spr->swr.numSamples > 1) {
1051 /* Free an attached resolve resource */
1052 struct swr_resource *alt = swr_resource(spr->resolve_target);
1053 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1054 }
1055
1056 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1057 swr_fence_work_free(screen->flush_fence,
1058 (void*)(spr->secondary.xpBaseAddress), true);
1059
1060 /* If work queue grows too large, submit a fence to force queue to
1061 * drain. This is mainly to decrease the amount of memory used by the
1062 * piglit streaming-texture-leak test */
1063 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1064 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1065 }
1066
1067 FREE(spr);
1068 }
1069
1070
1071 static void
1072 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1073 struct pipe_resource *resource,
1074 unsigned level,
1075 unsigned layer,
1076 void *context_private,
1077 struct pipe_box *sub_box)
1078 {
1079 struct swr_screen *screen = swr_screen(p_screen);
1080 struct sw_winsys *winsys = screen->winsys;
1081 struct swr_resource *spr = swr_resource(resource);
1082 struct pipe_context *pipe = screen->pipe;
1083 struct swr_context *ctx = swr_context(pipe);
1084
1085 if (pipe) {
1086 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1087 swr_resource_unused(resource);
1088 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1089 }
1090
1091 /* Multisample resolved into resolve_target at flush with store_resource */
1092 if (pipe && spr->swr.numSamples > 1) {
1093 struct pipe_resource *resolve_target = spr->resolve_target;
1094
1095 /* Once resolved, copy into display target */
1096 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1097
1098 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1099 PIPE_TRANSFER_WRITE);
1100 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1101 winsys->displaytarget_unmap(winsys, spr->display_target);
1102 }
1103
1104 debug_assert(spr->display_target);
1105 if (spr->display_target)
1106 winsys->displaytarget_display(
1107 winsys, spr->display_target, context_private, sub_box);
1108 }
1109
1110
1111 void
1112 swr_destroy_screen_internal(struct swr_screen **screen)
1113 {
1114 struct pipe_screen *p_screen = &(*screen)->base;
1115
1116 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1117 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1118
1119 JitDestroyContext((*screen)->hJitMgr);
1120
1121 if ((*screen)->pLibrary)
1122 util_dl_close((*screen)->pLibrary);
1123
1124 FREE(*screen);
1125 *screen = NULL;
1126 }
1127
1128
1129 static void
1130 swr_destroy_screen(struct pipe_screen *p_screen)
1131 {
1132 struct swr_screen *screen = swr_screen(p_screen);
1133 struct sw_winsys *winsys = screen->winsys;
1134
1135 swr_print_info("SWR destroy screen!\n");
1136
1137 if (winsys->destroy)
1138 winsys->destroy(winsys);
1139
1140 swr_destroy_screen_internal(&screen);
1141 }
1142
1143
1144 static void
1145 swr_validate_env_options(struct swr_screen *screen)
1146 {
1147 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1148 * copied to scratch space on a draw. Past this, the draw will access
1149 * user-buffer directly and then block. This is faster than queuing many
1150 * large client draws. */
1151 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1152 int client_copy_limit =
1153 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1154 if (client_copy_limit > 0)
1155 screen->client_copy_limit = client_copy_limit;
1156
1157 /* XXX msaa under development, disable by default for now */
1158 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1159
1160 /* validate env override values, within range and power of 2 */
1161 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1162 if (msaa_max_count != 1) {
1163 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1164 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1165 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1166 fprintf(stderr, "must be power of 2 between 1 and %d" \
1167 " (or 1 to disable msaa)\n",
1168 SWR_MAX_NUM_MULTISAMPLES);
1169 fprintf(stderr, "(msaa disabled)\n");
1170 msaa_max_count = 1;
1171 }
1172
1173 swr_print_info("SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1174
1175 screen->msaa_max_count = msaa_max_count;
1176 }
1177
1178 screen->msaa_force_enable = debug_get_bool_option(
1179 "SWR_MSAA_FORCE_ENABLE", false);
1180 if (screen->msaa_force_enable)
1181 swr_print_info("SWR_MSAA_FORCE_ENABLE: true\n");
1182 }
1183
1184
1185 struct pipe_screen *
1186 swr_create_screen_internal(struct sw_winsys *winsys)
1187 {
1188 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1189
1190 if (!screen)
1191 return NULL;
1192
1193 if (!lp_build_init()) {
1194 FREE(screen);
1195 return NULL;
1196 }
1197
1198 screen->winsys = winsys;
1199 screen->base.get_name = swr_get_name;
1200 screen->base.get_vendor = swr_get_vendor;
1201 screen->base.is_format_supported = swr_is_format_supported;
1202 screen->base.context_create = swr_create_context;
1203 screen->base.can_create_resource = swr_can_create_resource;
1204
1205 screen->base.destroy = swr_destroy_screen;
1206 screen->base.get_param = swr_get_param;
1207 screen->base.get_shader_param = swr_get_shader_param;
1208 screen->base.get_paramf = swr_get_paramf;
1209
1210 screen->base.resource_create = swr_resource_create;
1211 screen->base.resource_destroy = swr_resource_destroy;
1212
1213 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1214
1215 // Pass in "" for architecture for run-time determination
1216 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1217
1218 swr_fence_init(&screen->base);
1219
1220 swr_validate_env_options(screen);
1221
1222 return &screen->base;
1223 }