gallium: add a pipe_context parameter to fence_finish
[mesa.git] / src / gallium / drivers / swr / swr_state.cpp
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23
24 // llvm redefines DEBUG
25 #pragma push_macro("DEBUG")
26 #undef DEBUG
27 #include "JitManager.h"
28 #pragma pop_macro("DEBUG")
29
30 #include "common/os.h"
31 #include "jit_api.h"
32 #include "state_llvm.h"
33
34 #include "gallivm/lp_bld_tgsi.h"
35 #include "util/u_format.h"
36
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_helpers.h"
40 #include "util/u_framebuffer.h"
41
42 #include "swr_state.h"
43 #include "swr_context.h"
44 #include "swr_context_llvm.h"
45 #include "swr_screen.h"
46 #include "swr_resource.h"
47 #include "swr_tex_sample.h"
48 #include "swr_scratch.h"
49 #include "swr_shader.h"
50 #include "swr_fence.h"
51
52 /* These should be pulled out into separate files as necessary
53 * Just initializing everything here to get going. */
54
55 static void *
56 swr_create_blend_state(struct pipe_context *pipe,
57 const struct pipe_blend_state *blend)
58 {
59 struct swr_blend_state *state = CALLOC_STRUCT(swr_blend_state);
60
61 memcpy(&state->pipe, blend, sizeof(*blend));
62
63 struct pipe_blend_state *pipe_blend = &state->pipe;
64
65 for (int target = 0;
66 target < std::min(SWR_NUM_RENDERTARGETS, PIPE_MAX_COLOR_BUFS);
67 target++) {
68
69 struct pipe_rt_blend_state *rt_blend = &pipe_blend->rt[target];
70 SWR_RENDER_TARGET_BLEND_STATE &blendState =
71 state->blendState.renderTarget[target];
72 RENDER_TARGET_BLEND_COMPILE_STATE &compileState =
73 state->compileState[target];
74
75 if (target != 0 && !pipe_blend->independent_blend_enable) {
76 memcpy(&compileState,
77 &state->compileState[0],
78 sizeof(RENDER_TARGET_BLEND_COMPILE_STATE));
79 continue;
80 }
81
82 compileState.blendEnable = rt_blend->blend_enable;
83 if (compileState.blendEnable) {
84 compileState.sourceAlphaBlendFactor =
85 swr_convert_blend_factor(rt_blend->alpha_src_factor);
86 compileState.destAlphaBlendFactor =
87 swr_convert_blend_factor(rt_blend->alpha_dst_factor);
88 compileState.sourceBlendFactor =
89 swr_convert_blend_factor(rt_blend->rgb_src_factor);
90 compileState.destBlendFactor =
91 swr_convert_blend_factor(rt_blend->rgb_dst_factor);
92
93 compileState.colorBlendFunc =
94 swr_convert_blend_func(rt_blend->rgb_func);
95 compileState.alphaBlendFunc =
96 swr_convert_blend_func(rt_blend->alpha_func);
97 }
98 compileState.logicOpEnable = state->pipe.logicop_enable;
99 if (compileState.logicOpEnable) {
100 compileState.logicOpFunc =
101 swr_convert_logic_op(state->pipe.logicop_func);
102 }
103
104 blendState.writeDisableRed =
105 (rt_blend->colormask & PIPE_MASK_R) ? 0 : 1;
106 blendState.writeDisableGreen =
107 (rt_blend->colormask & PIPE_MASK_G) ? 0 : 1;
108 blendState.writeDisableBlue =
109 (rt_blend->colormask & PIPE_MASK_B) ? 0 : 1;
110 blendState.writeDisableAlpha =
111 (rt_blend->colormask & PIPE_MASK_A) ? 0 : 1;
112
113 if (rt_blend->colormask == 0)
114 compileState.blendEnable = false;
115 }
116
117 return state;
118 }
119
120 static void
121 swr_bind_blend_state(struct pipe_context *pipe, void *blend)
122 {
123 struct swr_context *ctx = swr_context(pipe);
124
125 if (ctx->blend == blend)
126 return;
127
128 ctx->blend = (swr_blend_state *)blend;
129
130 ctx->dirty |= SWR_NEW_BLEND;
131 }
132
133 static void
134 swr_delete_blend_state(struct pipe_context *pipe, void *blend)
135 {
136 FREE(blend);
137 }
138
139 static void
140 swr_set_blend_color(struct pipe_context *pipe,
141 const struct pipe_blend_color *color)
142 {
143 struct swr_context *ctx = swr_context(pipe);
144
145 ctx->blend_color = *color;
146
147 ctx->dirty |= SWR_NEW_BLEND;
148 }
149
150 static void
151 swr_set_stencil_ref(struct pipe_context *pipe,
152 const struct pipe_stencil_ref *ref)
153 {
154 struct swr_context *ctx = swr_context(pipe);
155
156 ctx->stencil_ref = *ref;
157
158 ctx->dirty |= SWR_NEW_DEPTH_STENCIL_ALPHA;
159 }
160
161 static void *
162 swr_create_depth_stencil_state(
163 struct pipe_context *pipe,
164 const struct pipe_depth_stencil_alpha_state *depth_stencil)
165 {
166 struct pipe_depth_stencil_alpha_state *state;
167
168 state = (pipe_depth_stencil_alpha_state *)mem_dup(depth_stencil,
169 sizeof *depth_stencil);
170
171 return state;
172 }
173
174 static void
175 swr_bind_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)
176 {
177 struct swr_context *ctx = swr_context(pipe);
178
179 if (ctx->depth_stencil == (pipe_depth_stencil_alpha_state *)depth_stencil)
180 return;
181
182 ctx->depth_stencil = (pipe_depth_stencil_alpha_state *)depth_stencil;
183
184 ctx->dirty |= SWR_NEW_DEPTH_STENCIL_ALPHA;
185 }
186
187 static void
188 swr_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
189 {
190 FREE(depth);
191 }
192
193
194 static void *
195 swr_create_rasterizer_state(struct pipe_context *pipe,
196 const struct pipe_rasterizer_state *rast)
197 {
198 struct pipe_rasterizer_state *state;
199 state = (pipe_rasterizer_state *)mem_dup(rast, sizeof *rast);
200
201 return state;
202 }
203
204 static void
205 swr_bind_rasterizer_state(struct pipe_context *pipe, void *handle)
206 {
207 struct swr_context *ctx = swr_context(pipe);
208 const struct pipe_rasterizer_state *rasterizer =
209 (const struct pipe_rasterizer_state *)handle;
210
211 if (ctx->rasterizer == (pipe_rasterizer_state *)rasterizer)
212 return;
213
214 ctx->rasterizer = (pipe_rasterizer_state *)rasterizer;
215
216 ctx->dirty |= SWR_NEW_RASTERIZER;
217 }
218
219 static void
220 swr_delete_rasterizer_state(struct pipe_context *pipe, void *rasterizer)
221 {
222 FREE(rasterizer);
223 }
224
225
226 static void *
227 swr_create_sampler_state(struct pipe_context *pipe,
228 const struct pipe_sampler_state *sampler)
229 {
230 struct pipe_sampler_state *state =
231 (pipe_sampler_state *)mem_dup(sampler, sizeof *sampler);
232
233 return state;
234 }
235
236 static void
237 swr_bind_sampler_states(struct pipe_context *pipe,
238 unsigned shader,
239 unsigned start,
240 unsigned num,
241 void **samplers)
242 {
243 struct swr_context *ctx = swr_context(pipe);
244 unsigned i;
245
246 assert(shader < PIPE_SHADER_TYPES);
247 assert(start + num <= ARRAY_SIZE(ctx->samplers[shader]));
248
249 /* set the new samplers */
250 ctx->num_samplers[shader] = num;
251 for (i = 0; i < num; i++) {
252 ctx->samplers[shader][start + i] = (pipe_sampler_state *)samplers[i];
253 }
254
255 ctx->dirty |= SWR_NEW_SAMPLER;
256 }
257
258 static void
259 swr_delete_sampler_state(struct pipe_context *pipe, void *sampler)
260 {
261 FREE(sampler);
262 }
263
264
265 static struct pipe_sampler_view *
266 swr_create_sampler_view(struct pipe_context *pipe,
267 struct pipe_resource *texture,
268 const struct pipe_sampler_view *templ)
269 {
270 struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
271
272 if (view) {
273 *view = *templ;
274 view->reference.count = 1;
275 view->texture = NULL;
276 pipe_resource_reference(&view->texture, texture);
277 view->context = pipe;
278 }
279
280 return view;
281 }
282
283 static void
284 swr_set_sampler_views(struct pipe_context *pipe,
285 unsigned shader,
286 unsigned start,
287 unsigned num,
288 struct pipe_sampler_view **views)
289 {
290 struct swr_context *ctx = swr_context(pipe);
291 uint i;
292
293 assert(num <= PIPE_MAX_SHADER_SAMPLER_VIEWS);
294
295 assert(shader < PIPE_SHADER_TYPES);
296 assert(start + num <= ARRAY_SIZE(ctx->sampler_views[shader]));
297
298 /* set the new sampler views */
299 ctx->num_sampler_views[shader] = num;
300 for (i = 0; i < num; i++) {
301 /* Note: we're using pipe_sampler_view_release() here to work around
302 * a possible crash when the old view belongs to another context that
303 * was already destroyed.
304 */
305 pipe_sampler_view_release(pipe, &ctx->sampler_views[shader][start + i]);
306 pipe_sampler_view_reference(&ctx->sampler_views[shader][start + i],
307 views[i]);
308 }
309
310 ctx->dirty |= SWR_NEW_SAMPLER_VIEW;
311 }
312
313 static void
314 swr_sampler_view_destroy(struct pipe_context *pipe,
315 struct pipe_sampler_view *view)
316 {
317 pipe_resource_reference(&view->texture, NULL);
318 FREE(view);
319 }
320
321 static void *
322 swr_create_vs_state(struct pipe_context *pipe,
323 const struct pipe_shader_state *vs)
324 {
325 struct swr_vertex_shader *swr_vs = new swr_vertex_shader;
326 if (!swr_vs)
327 return NULL;
328
329 swr_vs->pipe.tokens = tgsi_dup_tokens(vs->tokens);
330 swr_vs->pipe.stream_output = vs->stream_output;
331
332 lp_build_tgsi_info(vs->tokens, &swr_vs->info);
333
334 swr_vs->soState = {0};
335
336 if (swr_vs->pipe.stream_output.num_outputs) {
337 pipe_stream_output_info *stream_output = &swr_vs->pipe.stream_output;
338
339 swr_vs->soState.soEnable = true;
340 // soState.rasterizerDisable set on state dirty
341 // soState.streamToRasterizer not used
342
343 for (uint32_t i = 0; i < stream_output->num_outputs; i++) {
344 swr_vs->soState.streamMasks[stream_output->output[i].stream] |=
345 1 << (stream_output->output[i].register_index - 1);
346 }
347 for (uint32_t i = 0; i < MAX_SO_STREAMS; i++) {
348 swr_vs->soState.streamNumEntries[i] =
349 _mm_popcnt_u32(swr_vs->soState.streamMasks[i]);
350 }
351 }
352
353 return swr_vs;
354 }
355
356 static void
357 swr_bind_vs_state(struct pipe_context *pipe, void *vs)
358 {
359 struct swr_context *ctx = swr_context(pipe);
360
361 if (ctx->vs == vs)
362 return;
363
364 ctx->vs = (swr_vertex_shader *)vs;
365 ctx->dirty |= SWR_NEW_VS;
366 }
367
368 static void
369 swr_delete_vs_state(struct pipe_context *pipe, void *vs)
370 {
371 struct swr_vertex_shader *swr_vs = (swr_vertex_shader *)vs;
372 FREE((void *)swr_vs->pipe.tokens);
373 delete swr_vs;
374 }
375
376 static void *
377 swr_create_fs_state(struct pipe_context *pipe,
378 const struct pipe_shader_state *fs)
379 {
380 struct swr_fragment_shader *swr_fs = new swr_fragment_shader;
381 if (!swr_fs)
382 return NULL;
383
384 swr_fs->pipe.tokens = tgsi_dup_tokens(fs->tokens);
385
386 lp_build_tgsi_info(fs->tokens, &swr_fs->info);
387
388 return swr_fs;
389 }
390
391
392 static void
393 swr_bind_fs_state(struct pipe_context *pipe, void *fs)
394 {
395 struct swr_context *ctx = swr_context(pipe);
396
397 if (ctx->fs == fs)
398 return;
399
400 ctx->fs = (swr_fragment_shader *)fs;
401 ctx->dirty |= SWR_NEW_FS;
402 }
403
404 static void
405 swr_delete_fs_state(struct pipe_context *pipe, void *fs)
406 {
407 struct swr_fragment_shader *swr_fs = (swr_fragment_shader *)fs;
408 FREE((void *)swr_fs->pipe.tokens);
409 delete swr_fs;
410 }
411
412
413 static void
414 swr_set_constant_buffer(struct pipe_context *pipe,
415 uint shader,
416 uint index,
417 const struct pipe_constant_buffer *cb)
418 {
419 struct swr_context *ctx = swr_context(pipe);
420 struct pipe_resource *constants = cb ? cb->buffer : NULL;
421
422 assert(shader < PIPE_SHADER_TYPES);
423 assert(index < ARRAY_SIZE(ctx->constants[shader]));
424
425 /* note: reference counting */
426 util_copy_constant_buffer(&ctx->constants[shader][index], cb);
427
428 if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_GEOMETRY) {
429 ctx->dirty |= SWR_NEW_VSCONSTANTS;
430 } else if (shader == PIPE_SHADER_FRAGMENT) {
431 ctx->dirty |= SWR_NEW_FSCONSTANTS;
432 }
433
434 if (cb && cb->user_buffer) {
435 pipe_resource_reference(&constants, NULL);
436 }
437 }
438
439
440 static void *
441 swr_create_vertex_elements_state(struct pipe_context *pipe,
442 unsigned num_elements,
443 const struct pipe_vertex_element *attribs)
444 {
445 struct swr_vertex_element_state *velems;
446 assert(num_elements <= PIPE_MAX_ATTRIBS);
447 velems = CALLOC_STRUCT(swr_vertex_element_state);
448 if (velems) {
449 velems->fsState.numAttribs = num_elements;
450 for (unsigned i = 0; i < num_elements; i++) {
451 // XXX: we should do this keyed on the VS usage info
452
453 const struct util_format_description *desc =
454 util_format_description(attribs[i].src_format);
455
456 velems->fsState.layout[i].AlignedByteOffset = attribs[i].src_offset;
457 velems->fsState.layout[i].Format =
458 mesa_to_swr_format(attribs[i].src_format);
459 velems->fsState.layout[i].StreamIndex =
460 attribs[i].vertex_buffer_index;
461 velems->fsState.layout[i].InstanceEnable =
462 attribs[i].instance_divisor != 0;
463 velems->fsState.layout[i].ComponentControl0 =
464 desc->channel[0].type != UTIL_FORMAT_TYPE_VOID
465 ? ComponentControl::StoreSrc
466 : ComponentControl::Store0;
467 velems->fsState.layout[i].ComponentControl1 =
468 desc->channel[1].type != UTIL_FORMAT_TYPE_VOID
469 ? ComponentControl::StoreSrc
470 : ComponentControl::Store0;
471 velems->fsState.layout[i].ComponentControl2 =
472 desc->channel[2].type != UTIL_FORMAT_TYPE_VOID
473 ? ComponentControl::StoreSrc
474 : ComponentControl::Store0;
475 velems->fsState.layout[i].ComponentControl3 =
476 desc->channel[3].type != UTIL_FORMAT_TYPE_VOID
477 ? ComponentControl::StoreSrc
478 : ComponentControl::Store1Fp;
479 velems->fsState.layout[i].ComponentPacking = ComponentEnable::XYZW;
480 velems->fsState.layout[i].InstanceDataStepRate =
481 attribs[i].instance_divisor;
482
483 /* Calculate the pitch of each stream */
484 const SWR_FORMAT_INFO &swr_desc = GetFormatInfo(
485 mesa_to_swr_format(attribs[i].src_format));
486 velems->stream_pitch[attribs[i].vertex_buffer_index] += swr_desc.Bpp;
487 }
488 }
489
490 return velems;
491 }
492
493 static void
494 swr_bind_vertex_elements_state(struct pipe_context *pipe, void *velems)
495 {
496 struct swr_context *ctx = swr_context(pipe);
497 struct swr_vertex_element_state *swr_velems =
498 (struct swr_vertex_element_state *)velems;
499
500 ctx->velems = swr_velems;
501 ctx->dirty |= SWR_NEW_VERTEX;
502 }
503
504 static void
505 swr_delete_vertex_elements_state(struct pipe_context *pipe, void *velems)
506 {
507 /* XXX Need to destroy fetch shader? */
508 FREE(velems);
509 }
510
511
512 static void
513 swr_set_vertex_buffers(struct pipe_context *pipe,
514 unsigned start_slot,
515 unsigned num_elements,
516 const struct pipe_vertex_buffer *buffers)
517 {
518 struct swr_context *ctx = swr_context(pipe);
519
520 assert(num_elements <= PIPE_MAX_ATTRIBS);
521
522 util_set_vertex_buffers_count(ctx->vertex_buffer,
523 &ctx->num_vertex_buffers,
524 buffers,
525 start_slot,
526 num_elements);
527
528 ctx->dirty |= SWR_NEW_VERTEX;
529 }
530
531
532 static void
533 swr_set_index_buffer(struct pipe_context *pipe,
534 const struct pipe_index_buffer *ib)
535 {
536 struct swr_context *ctx = swr_context(pipe);
537
538 if (ib)
539 memcpy(&ctx->index_buffer, ib, sizeof(ctx->index_buffer));
540 else
541 memset(&ctx->index_buffer, 0, sizeof(ctx->index_buffer));
542
543 ctx->dirty |= SWR_NEW_VERTEX;
544 }
545
546 static void
547 swr_set_polygon_stipple(struct pipe_context *pipe,
548 const struct pipe_poly_stipple *stipple)
549 {
550 struct swr_context *ctx = swr_context(pipe);
551
552 ctx->poly_stipple = *stipple; /* struct copy */
553 ctx->dirty |= SWR_NEW_STIPPLE;
554 }
555
556 static void
557 swr_set_clip_state(struct pipe_context *pipe,
558 const struct pipe_clip_state *clip)
559 {
560 struct swr_context *ctx = swr_context(pipe);
561
562 ctx->clip = *clip;
563 /* XXX Unimplemented, but prevents crash */
564
565 ctx->dirty |= SWR_NEW_CLIP;
566 }
567
568
569 static void
570 swr_set_scissor_states(struct pipe_context *pipe,
571 unsigned start_slot,
572 unsigned num_viewports,
573 const struct pipe_scissor_state *scissor)
574 {
575 struct swr_context *ctx = swr_context(pipe);
576
577 ctx->scissor = *scissor;
578 ctx->dirty |= SWR_NEW_SCISSOR;
579 }
580
581 static void
582 swr_set_viewport_states(struct pipe_context *pipe,
583 unsigned start_slot,
584 unsigned num_viewports,
585 const struct pipe_viewport_state *vpt)
586 {
587 struct swr_context *ctx = swr_context(pipe);
588
589 ctx->viewport = *vpt;
590 ctx->dirty |= SWR_NEW_VIEWPORT;
591 }
592
593
594 static void
595 swr_set_framebuffer_state(struct pipe_context *pipe,
596 const struct pipe_framebuffer_state *fb)
597 {
598 struct swr_context *ctx = swr_context(pipe);
599
600 boolean changed = !util_framebuffer_state_equal(&ctx->framebuffer, fb);
601
602 assert(fb->width <= KNOB_GUARDBAND_WIDTH);
603 assert(fb->height <= KNOB_GUARDBAND_HEIGHT);
604
605 if (changed) {
606 unsigned i;
607 for (i = 0; i < fb->nr_cbufs; ++i)
608 pipe_surface_reference(&ctx->framebuffer.cbufs[i], fb->cbufs[i]);
609 for (; i < ctx->framebuffer.nr_cbufs; ++i)
610 pipe_surface_reference(&ctx->framebuffer.cbufs[i], NULL);
611
612 ctx->framebuffer.nr_cbufs = fb->nr_cbufs;
613
614 ctx->framebuffer.width = fb->width;
615 ctx->framebuffer.height = fb->height;
616
617 pipe_surface_reference(&ctx->framebuffer.zsbuf, fb->zsbuf);
618
619 ctx->dirty |= SWR_NEW_FRAMEBUFFER;
620 }
621 }
622
623
624 static void
625 swr_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
626 {
627 struct swr_context *ctx = swr_context(pipe);
628
629 if (sample_mask != ctx->sample_mask) {
630 ctx->sample_mask = sample_mask;
631 ctx->dirty |= SWR_NEW_RASTERIZER;
632 }
633 }
634
635 /*
636 * Update resource in-use status
637 * All resources bound to color or depth targets marked as WRITE resources.
638 * VBO Vertex/index buffers and texture views marked as READ resources.
639 */
640 void
641 swr_update_resource_status(struct pipe_context *pipe,
642 const struct pipe_draw_info *p_draw_info)
643 {
644 struct swr_context *ctx = swr_context(pipe);
645 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
646
647 /* colorbuffer targets */
648 if (fb->nr_cbufs)
649 for (uint32_t i = 0; i < fb->nr_cbufs; ++i)
650 if (fb->cbufs[i])
651 swr_resource_write(fb->cbufs[i]->texture);
652
653 /* depth/stencil target */
654 if (fb->zsbuf)
655 swr_resource_write(fb->zsbuf->texture);
656
657 /* VBO vertex buffers */
658 for (uint32_t i = 0; i < ctx->num_vertex_buffers; i++) {
659 struct pipe_vertex_buffer *vb = &ctx->vertex_buffer[i];
660 if (!vb->user_buffer)
661 swr_resource_read(vb->buffer);
662 }
663
664 /* VBO index buffer */
665 if (p_draw_info && p_draw_info->indexed) {
666 struct pipe_index_buffer *ib = &ctx->index_buffer;
667 if (!ib->user_buffer)
668 swr_resource_read(ib->buffer);
669 }
670
671 /* texture sampler views */
672 for (uint32_t i = 0; i < PIPE_MAX_SHADER_SAMPLER_VIEWS; i++) {
673 struct pipe_sampler_view *view =
674 ctx->sampler_views[PIPE_SHADER_FRAGMENT][i];
675 if (view)
676 swr_resource_read(view->texture);
677 }
678 }
679
680 static void
681 swr_update_texture_state(struct swr_context *ctx,
682 unsigned shader_type,
683 unsigned num_sampler_views,
684 swr_jit_texture *textures)
685 {
686 for (unsigned i = 0; i < num_sampler_views; i++) {
687 struct pipe_sampler_view *view =
688 ctx->sampler_views[shader_type][i];
689
690 if (view) {
691 struct pipe_resource *res = view->texture;
692 struct swr_resource *swr_res = swr_resource(res);
693 struct swr_jit_texture *jit_tex = &textures[i];
694 memset(jit_tex, 0, sizeof(*jit_tex));
695 jit_tex->width = res->width0;
696 jit_tex->height = res->height0;
697 jit_tex->depth = res->depth0;
698 jit_tex->first_level = view->u.tex.first_level;
699 jit_tex->last_level = view->u.tex.last_level;
700 jit_tex->base_ptr = swr_res->swr.pBaseAddress;
701
702 for (unsigned level = jit_tex->first_level;
703 level <= jit_tex->last_level;
704 level++) {
705 jit_tex->row_stride[level] = swr_res->row_stride[level];
706 jit_tex->img_stride[level] = swr_res->img_stride[level];
707 jit_tex->mip_offsets[level] = swr_res->mip_offsets[level];
708 }
709 }
710 }
711 }
712
713 static void
714 swr_update_sampler_state(struct swr_context *ctx,
715 unsigned shader_type,
716 unsigned num_samplers,
717 swr_jit_sampler *samplers)
718 {
719 for (unsigned i = 0; i < num_samplers; i++) {
720 const struct pipe_sampler_state *sampler =
721 ctx->samplers[shader_type][i];
722
723 if (sampler) {
724 samplers[i].min_lod = sampler->min_lod;
725 samplers[i].max_lod = sampler->max_lod;
726 samplers[i].lod_bias = sampler->lod_bias;
727 COPY_4V(samplers[i].border_color, sampler->border_color.f);
728 }
729 }
730 }
731
732 static void
733 swr_update_constants(struct swr_context *ctx, enum pipe_shader_type shaderType)
734 {
735 swr_draw_context *pDC = &ctx->swrDC;
736
737 const float **constant;
738 uint32_t *num_constants;
739 struct swr_scratch_space *scratch;
740
741 switch (shaderType) {
742 case PIPE_SHADER_VERTEX:
743 constant = pDC->constantVS;
744 num_constants = pDC->num_constantsVS;
745 scratch = &ctx->scratch->vs_constants;
746 break;
747 case PIPE_SHADER_FRAGMENT:
748 constant = pDC->constantFS;
749 num_constants = pDC->num_constantsFS;
750 scratch = &ctx->scratch->fs_constants;
751 break;
752 default:
753 debug_printf("Unsupported shader type constants\n");
754 return;
755 }
756
757 for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
758 const pipe_constant_buffer *cb = &ctx->constants[shaderType][i];
759 num_constants[i] = cb->buffer_size;
760 if (cb->buffer) {
761 constant[i] =
762 (const float *)(swr_resource_data(cb->buffer) +
763 cb->buffer_offset);
764 } else {
765 /* Need to copy these constants to scratch space */
766 if (cb->user_buffer && cb->buffer_size) {
767 const void *ptr =
768 ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
769 uint32_t size = AlignUp(cb->buffer_size, 4);
770 ptr = swr_copy_to_scratch_space(ctx, scratch, ptr, size);
771 constant[i] = (const float *)ptr;
772 }
773 }
774 }
775 }
776
777 void
778 swr_update_derived(struct pipe_context *pipe,
779 const struct pipe_draw_info *p_draw_info)
780 {
781 struct swr_context *ctx = swr_context(pipe);
782 struct swr_screen *screen = swr_screen(ctx->pipe.screen);
783
784 /* Update screen->pipe to current pipe context. */
785 if (screen->pipe != pipe)
786 screen->pipe = pipe;
787
788 /* Any state that requires dirty flags to be re-triggered sets this mask */
789 /* For example, user_buffer vertex and index buffers. */
790 unsigned post_update_dirty_flags = 0;
791
792 /* Render Targets */
793 if (ctx->dirty & SWR_NEW_FRAMEBUFFER) {
794 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
795 SWR_SURFACE_STATE *new_attachment[SWR_NUM_ATTACHMENTS] = {0};
796 UINT i;
797
798 /* colorbuffer targets */
799 if (fb->nr_cbufs)
800 for (i = 0; i < fb->nr_cbufs; ++i)
801 if (fb->cbufs[i]) {
802 struct swr_resource *colorBuffer =
803 swr_resource(fb->cbufs[i]->texture);
804 new_attachment[SWR_ATTACHMENT_COLOR0 + i] = &colorBuffer->swr;
805 }
806
807 /* depth/stencil target */
808 if (fb->zsbuf) {
809 struct swr_resource *depthStencilBuffer =
810 swr_resource(fb->zsbuf->texture);
811 if (depthStencilBuffer->has_depth) {
812 new_attachment[SWR_ATTACHMENT_DEPTH] = &depthStencilBuffer->swr;
813
814 if (depthStencilBuffer->has_stencil)
815 new_attachment[SWR_ATTACHMENT_STENCIL] =
816 &depthStencilBuffer->secondary;
817
818 } else if (depthStencilBuffer->has_stencil)
819 new_attachment[SWR_ATTACHMENT_STENCIL] = &depthStencilBuffer->swr;
820 }
821
822 /* Make the attachment updates */
823 swr_draw_context *pDC = &ctx->swrDC;
824 SWR_SURFACE_STATE *renderTargets = pDC->renderTargets;
825 unsigned need_fence = FALSE;
826 for (i = 0; i < SWR_NUM_ATTACHMENTS; i++) {
827 void *new_base = nullptr;
828 if (new_attachment[i])
829 new_base = new_attachment[i]->pBaseAddress;
830
831 /* StoreTile for changed target */
832 if (renderTargets[i].pBaseAddress != new_base) {
833 if (renderTargets[i].pBaseAddress) {
834 /* If changing attachment to a new target, mark tiles as
835 * INVALID so they are reloaded from surface.
836 * If detaching attachment, mark tiles as RESOLVED so core
837 * won't try to load from non-existent target. */
838 enum SWR_TILE_STATE post_state = (new_attachment[i]
839 ? SWR_TILE_INVALID : SWR_TILE_RESOLVED);
840 swr_store_render_target(pipe, i, post_state);
841
842 need_fence |= TRUE;
843 }
844
845 /* Make new attachment */
846 if (new_attachment[i])
847 renderTargets[i] = *new_attachment[i];
848 else
849 if (renderTargets[i].pBaseAddress)
850 renderTargets[i] = {0};
851 }
852 }
853
854 /* This fence ensures any attachment changes are resolved before the
855 * next draw */
856 if (need_fence)
857 swr_fence_submit(ctx, screen->flush_fence);
858 }
859
860 /* Raster state */
861 if (ctx->dirty & (SWR_NEW_RASTERIZER |
862 SWR_NEW_VS | // clipping
863 SWR_NEW_FRAMEBUFFER)) {
864 pipe_rasterizer_state *rasterizer = ctx->rasterizer;
865 pipe_framebuffer_state *fb = &ctx->framebuffer;
866
867 SWR_RASTSTATE *rastState = &ctx->derived.rastState;
868 rastState->cullMode = swr_convert_cull_mode(rasterizer->cull_face);
869 rastState->frontWinding = rasterizer->front_ccw
870 ? SWR_FRONTWINDING_CCW
871 : SWR_FRONTWINDING_CW;
872 rastState->scissorEnable = rasterizer->scissor;
873 rastState->pointSize = rasterizer->point_size > 0.0f
874 ? rasterizer->point_size
875 : 1.0f;
876 rastState->lineWidth = rasterizer->line_width > 0.0f
877 ? rasterizer->line_width
878 : 1.0f;
879
880 rastState->pointParam = rasterizer->point_size_per_vertex;
881
882 rastState->pointSpriteEnable = rasterizer->sprite_coord_enable;
883 rastState->pointSpriteTopOrigin =
884 rasterizer->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT;
885
886 /* XXX TODO: Add multisample */
887 rastState->msaaRastEnable = false;
888 rastState->rastMode = SWR_MSAA_RASTMODE_OFF_PIXEL;
889 rastState->sampleCount = SWR_MULTISAMPLE_1X;
890 rastState->forcedSampleCount = false;
891
892 bool do_offset = false;
893 switch (rasterizer->fill_front) {
894 case PIPE_POLYGON_MODE_FILL:
895 do_offset = rasterizer->offset_tri;
896 break;
897 case PIPE_POLYGON_MODE_LINE:
898 do_offset = rasterizer->offset_line;
899 break;
900 case PIPE_POLYGON_MODE_POINT:
901 do_offset = rasterizer->offset_point;
902 break;
903 }
904
905 if (do_offset) {
906 rastState->depthBias = rasterizer->offset_units;
907 rastState->slopeScaledDepthBias = rasterizer->offset_scale;
908 rastState->depthBiasClamp = rasterizer->offset_clamp;
909 } else {
910 rastState->depthBias = 0;
911 rastState->slopeScaledDepthBias = 0;
912 rastState->depthBiasClamp = 0;
913 }
914 struct pipe_surface *zb = fb->zsbuf;
915 if (zb && swr_resource(zb->texture)->has_depth)
916 rastState->depthFormat = swr_resource(zb->texture)->swr.format;
917
918 rastState->depthClipEnable = rasterizer->depth_clip;
919
920 rastState->clipDistanceMask =
921 ctx->vs->info.base.num_written_clipdistance ?
922 ctx->vs->info.base.clipdist_writemask & rasterizer->clip_plane_enable :
923 rasterizer->clip_plane_enable;
924
925 rastState->cullDistanceMask =
926 ctx->vs->info.base.culldist_writemask << ctx->vs->info.base.num_written_clipdistance;
927
928 SwrSetRastState(ctx->swrContext, rastState);
929 }
930
931 /* Scissor */
932 if (ctx->dirty & SWR_NEW_SCISSOR) {
933 pipe_scissor_state *scissor = &ctx->scissor;
934 BBOX bbox(scissor->miny, scissor->maxy,
935 scissor->minx, scissor->maxx);
936 SwrSetScissorRects(ctx->swrContext, 1, &bbox);
937 }
938
939 /* Viewport */
940 if (ctx->dirty & (SWR_NEW_VIEWPORT | SWR_NEW_FRAMEBUFFER
941 | SWR_NEW_RASTERIZER)) {
942 pipe_viewport_state *state = &ctx->viewport;
943 pipe_framebuffer_state *fb = &ctx->framebuffer;
944 pipe_rasterizer_state *rasterizer = ctx->rasterizer;
945
946 SWR_VIEWPORT *vp = &ctx->derived.vp;
947 SWR_VIEWPORT_MATRIX *vpm = &ctx->derived.vpm;
948
949 vp->x = state->translate[0] - state->scale[0];
950 vp->width = state->translate[0] + state->scale[0];
951 vp->y = state->translate[1] - fabs(state->scale[1]);
952 vp->height = state->translate[1] + fabs(state->scale[1]);
953 if (rasterizer->clip_halfz == 0) {
954 vp->minZ = state->translate[2] - state->scale[2];
955 vp->maxZ = state->translate[2] + state->scale[2];
956 } else {
957 vp->minZ = state->translate[2];
958 vp->maxZ = state->translate[2] + state->scale[2];
959 }
960
961 vpm->m00 = state->scale[0];
962 vpm->m11 = state->scale[1];
963 vpm->m22 = state->scale[2];
964 vpm->m30 = state->translate[0];
965 vpm->m31 = state->translate[1];
966 vpm->m32 = state->translate[2];
967
968 /* Now that the matrix is calculated, clip the view coords to screen
969 * size. OpenGL allows for -ve x,y in the viewport. */
970 vp->x = std::max(vp->x, 0.0f);
971 vp->y = std::max(vp->y, 0.0f);
972 vp->width = std::min(vp->width, (float)fb->width);
973 vp->height = std::min(vp->height, (float)fb->height);
974
975 SwrSetViewports(ctx->swrContext, 1, vp, vpm);
976 }
977
978 /* Set vertex & index buffers */
979 /* (using draw info if called by swr_draw_vbo) */
980 if (ctx->dirty & SWR_NEW_VERTEX) {
981 uint32_t size, pitch, max_vertex, partial_inbounds;
982 const uint8_t *p_data;
983
984 /* If being called by swr_draw_vbo, copy draw details */
985 struct pipe_draw_info info = {0};
986 if (p_draw_info)
987 info = *p_draw_info;
988
989 /* vertex buffers */
990 SWR_VERTEX_BUFFER_STATE swrVertexBuffers[PIPE_MAX_ATTRIBS];
991 for (UINT i = 0; i < ctx->num_vertex_buffers; i++) {
992 struct pipe_vertex_buffer *vb = &ctx->vertex_buffer[i];
993
994 pitch = vb->stride;
995 if (!vb->user_buffer) {
996 /* VBO
997 * size is based on buffer->width0 rather than info.max_index
998 * to prevent having to validate VBO on each draw */
999 size = vb->buffer->width0;
1000 max_vertex = size / pitch;
1001 partial_inbounds = size % pitch;
1002
1003 p_data = swr_resource_data(vb->buffer) + vb->buffer_offset;
1004 } else {
1005 /* Client buffer
1006 * client memory is one-time use, re-trigger SWR_NEW_VERTEX to
1007 * revalidate on each draw */
1008 post_update_dirty_flags |= SWR_NEW_VERTEX;
1009
1010 if (pitch) {
1011 size = (info.max_index - info.min_index + 1) * pitch;
1012 } else {
1013 /* pitch = 0, means constant value
1014 * set size to 1 vertex */
1015 size = ctx->velems->stream_pitch[i];
1016 }
1017
1018 max_vertex = info.max_index + 1;
1019 partial_inbounds = 0;
1020
1021 /* Copy only needed vertices to scratch space */
1022 size = AlignUp(size, 4);
1023 const void *ptr = (const uint8_t *) vb->user_buffer
1024 + info.min_index * pitch;
1025 ptr = swr_copy_to_scratch_space(
1026 ctx, &ctx->scratch->vertex_buffer, ptr, size);
1027 p_data = (const uint8_t *)ptr - info.min_index * pitch;
1028 }
1029
1030 swrVertexBuffers[i] = {0};
1031 swrVertexBuffers[i].index = i;
1032 swrVertexBuffers[i].pitch = pitch;
1033 swrVertexBuffers[i].pData = p_data;
1034 swrVertexBuffers[i].size = size;
1035 swrVertexBuffers[i].maxVertex = max_vertex;
1036 swrVertexBuffers[i].partialInboundsSize = partial_inbounds;
1037 }
1038
1039 SwrSetVertexBuffers(
1040 ctx->swrContext, ctx->num_vertex_buffers, swrVertexBuffers);
1041
1042 /* index buffer, if required (info passed in by swr_draw_vbo) */
1043 SWR_FORMAT index_type = R32_UINT; /* Default for non-indexed draws */
1044 if (info.indexed) {
1045 struct pipe_index_buffer *ib = &ctx->index_buffer;
1046
1047 pitch = ib->index_size ? ib->index_size : sizeof(uint32_t);
1048 index_type = swr_convert_index_type(pitch);
1049
1050 if (!ib->user_buffer) {
1051 /* VBO
1052 * size is based on buffer->width0 rather than info.count
1053 * to prevent having to validate VBO on each draw */
1054 size = ib->buffer->width0;
1055 p_data = swr_resource_data(ib->buffer) + ib->offset;
1056 } else {
1057 /* Client buffer
1058 * client memory is one-time use, re-trigger SWR_NEW_VERTEX to
1059 * revalidate on each draw */
1060 post_update_dirty_flags |= SWR_NEW_VERTEX;
1061
1062 size = info.count * pitch;
1063 size = AlignUp(size, 4);
1064
1065 /* Copy indices to scratch space */
1066 const void *ptr = ib->user_buffer;
1067 ptr = swr_copy_to_scratch_space(
1068 ctx, &ctx->scratch->index_buffer, ptr, size);
1069 p_data = (const uint8_t *)ptr;
1070 }
1071
1072 SWR_INDEX_BUFFER_STATE swrIndexBuffer;
1073 swrIndexBuffer.format = swr_convert_index_type(ib->index_size);
1074 swrIndexBuffer.pIndices = p_data;
1075 swrIndexBuffer.size = size;
1076
1077 SwrSetIndexBuffer(ctx->swrContext, &swrIndexBuffer);
1078 }
1079
1080 struct swr_vertex_element_state *velems = ctx->velems;
1081 if (velems && velems->fsState.indexType != index_type) {
1082 velems->fsFunc = NULL;
1083 velems->fsState.indexType = index_type;
1084 }
1085 }
1086
1087 /* VertexShader */
1088 if (ctx->dirty & (SWR_NEW_VS |
1089 SWR_NEW_RASTERIZER | // for clip planes
1090 SWR_NEW_SAMPLER |
1091 SWR_NEW_SAMPLER_VIEW |
1092 SWR_NEW_FRAMEBUFFER)) {
1093 swr_jit_vs_key key;
1094 swr_generate_vs_key(key, ctx, ctx->vs);
1095 auto search = ctx->vs->map.find(key);
1096 PFN_VERTEX_FUNC func;
1097 if (search != ctx->vs->map.end()) {
1098 func = search->second->shader;
1099 } else {
1100 func = swr_compile_vs(ctx, key);
1101 }
1102 SwrSetVertexFunc(ctx->swrContext, func);
1103
1104 /* JIT sampler state */
1105 if (ctx->dirty & SWR_NEW_SAMPLER) {
1106 swr_update_sampler_state(ctx,
1107 PIPE_SHADER_VERTEX,
1108 key.nr_samplers,
1109 ctx->swrDC.samplersVS);
1110 }
1111
1112 /* JIT sampler view state */
1113 if (ctx->dirty & (SWR_NEW_SAMPLER_VIEW | SWR_NEW_FRAMEBUFFER)) {
1114 swr_update_texture_state(ctx,
1115 PIPE_SHADER_VERTEX,
1116 key.nr_sampler_views,
1117 ctx->swrDC.texturesVS);
1118 }
1119 }
1120
1121 /* FragmentShader */
1122 if (ctx->dirty & (SWR_NEW_FS | SWR_NEW_SAMPLER | SWR_NEW_SAMPLER_VIEW
1123 | SWR_NEW_RASTERIZER | SWR_NEW_FRAMEBUFFER)) {
1124 swr_jit_fs_key key;
1125 swr_generate_fs_key(key, ctx, ctx->fs);
1126 auto search = ctx->fs->map.find(key);
1127 PFN_PIXEL_KERNEL func;
1128 if (search != ctx->fs->map.end()) {
1129 func = search->second->shader;
1130 } else {
1131 func = swr_compile_fs(ctx, key);
1132 }
1133 SWR_PS_STATE psState = {0};
1134 psState.pfnPixelShader = func;
1135 psState.killsPixel = ctx->fs->info.base.uses_kill;
1136 psState.inputCoverage = SWR_INPUT_COVERAGE_NORMAL;
1137 psState.writesODepth = ctx->fs->info.base.writes_z;
1138 psState.usesSourceDepth = ctx->fs->info.base.reads_z;
1139 psState.shadingRate = SWR_SHADING_RATE_PIXEL; // XXX
1140 psState.numRenderTargets = ctx->framebuffer.nr_cbufs;
1141 psState.posOffset = SWR_PS_POSITION_SAMPLE_NONE; // XXX msaa
1142 uint32_t barycentricsMask = 0;
1143 #if 0
1144 // when we switch to mesa-master
1145 if (ctx->fs->info.base.uses_persp_center ||
1146 ctx->fs->info.base.uses_linear_center)
1147 barycentricsMask |= SWR_BARYCENTRIC_PER_PIXEL_MASK;
1148 if (ctx->fs->info.base.uses_persp_centroid ||
1149 ctx->fs->info.base.uses_linear_centroid)
1150 barycentricsMask |= SWR_BARYCENTRIC_CENTROID_MASK;
1151 if (ctx->fs->info.base.uses_persp_sample ||
1152 ctx->fs->info.base.uses_linear_sample)
1153 barycentricsMask |= SWR_BARYCENTRIC_PER_SAMPLE_MASK;
1154 #else
1155 for (unsigned i = 0; i < ctx->fs->info.base.num_inputs; i++) {
1156 switch (ctx->fs->info.base.input_interpolate_loc[i]) {
1157 case TGSI_INTERPOLATE_LOC_CENTER:
1158 barycentricsMask |= SWR_BARYCENTRIC_PER_PIXEL_MASK;
1159 break;
1160 case TGSI_INTERPOLATE_LOC_CENTROID:
1161 barycentricsMask |= SWR_BARYCENTRIC_CENTROID_MASK;
1162 break;
1163 case TGSI_INTERPOLATE_LOC_SAMPLE:
1164 barycentricsMask |= SWR_BARYCENTRIC_PER_SAMPLE_MASK;
1165 break;
1166 }
1167 }
1168 #endif
1169 psState.barycentricsMask = barycentricsMask;
1170 psState.usesUAV = false; // XXX
1171 psState.forceEarlyZ = false;
1172 SwrSetPixelShaderState(ctx->swrContext, &psState);
1173
1174 /* JIT sampler state */
1175 if (ctx->dirty & SWR_NEW_SAMPLER) {
1176 swr_update_sampler_state(ctx,
1177 PIPE_SHADER_FRAGMENT,
1178 key.nr_samplers,
1179 ctx->swrDC.samplersFS);
1180 }
1181
1182 /* JIT sampler view state */
1183 if (ctx->dirty & (SWR_NEW_SAMPLER_VIEW | SWR_NEW_FRAMEBUFFER)) {
1184 swr_update_texture_state(ctx,
1185 PIPE_SHADER_FRAGMENT,
1186 key.nr_sampler_views,
1187 ctx->swrDC.texturesFS);
1188 }
1189 }
1190
1191
1192 /* VertexShader Constants */
1193 if (ctx->dirty & SWR_NEW_VSCONSTANTS) {
1194 swr_update_constants(ctx, PIPE_SHADER_VERTEX);
1195 }
1196
1197 /* FragmentShader Constants */
1198 if (ctx->dirty & SWR_NEW_FSCONSTANTS) {
1199 swr_update_constants(ctx, PIPE_SHADER_FRAGMENT);
1200 }
1201
1202 /* Depth/stencil state */
1203 if (ctx->dirty & (SWR_NEW_DEPTH_STENCIL_ALPHA | SWR_NEW_FRAMEBUFFER)) {
1204 struct pipe_depth_state *depth = &(ctx->depth_stencil->depth);
1205 struct pipe_stencil_state *stencil = ctx->depth_stencil->stencil;
1206 SWR_DEPTH_STENCIL_STATE depthStencilState = {{0}};
1207
1208 /* XXX, incomplete. Need to flesh out stencil & alpha test state
1209 struct pipe_stencil_state *front_stencil =
1210 ctx->depth_stencil.stencil[0];
1211 struct pipe_stencil_state *back_stencil = ctx->depth_stencil.stencil[1];
1212 struct pipe_alpha_state alpha;
1213 */
1214 if (stencil[0].enabled) {
1215 depthStencilState.stencilWriteEnable = 1;
1216 depthStencilState.stencilTestEnable = 1;
1217 depthStencilState.stencilTestFunc =
1218 swr_convert_depth_func(stencil[0].func);
1219
1220 depthStencilState.stencilPassDepthPassOp =
1221 swr_convert_stencil_op(stencil[0].zpass_op);
1222 depthStencilState.stencilPassDepthFailOp =
1223 swr_convert_stencil_op(stencil[0].zfail_op);
1224 depthStencilState.stencilFailOp =
1225 swr_convert_stencil_op(stencil[0].fail_op);
1226 depthStencilState.stencilWriteMask = stencil[0].writemask;
1227 depthStencilState.stencilTestMask = stencil[0].valuemask;
1228 depthStencilState.stencilRefValue = ctx->stencil_ref.ref_value[0];
1229 }
1230 if (stencil[1].enabled) {
1231 depthStencilState.doubleSidedStencilTestEnable = 1;
1232
1233 depthStencilState.backfaceStencilTestFunc =
1234 swr_convert_depth_func(stencil[1].func);
1235
1236 depthStencilState.backfaceStencilPassDepthPassOp =
1237 swr_convert_stencil_op(stencil[1].zpass_op);
1238 depthStencilState.backfaceStencilPassDepthFailOp =
1239 swr_convert_stencil_op(stencil[1].zfail_op);
1240 depthStencilState.backfaceStencilFailOp =
1241 swr_convert_stencil_op(stencil[1].fail_op);
1242 depthStencilState.backfaceStencilWriteMask = stencil[1].writemask;
1243 depthStencilState.backfaceStencilTestMask = stencil[1].valuemask;
1244
1245 depthStencilState.backfaceStencilRefValue =
1246 ctx->stencil_ref.ref_value[1];
1247 }
1248
1249 depthStencilState.depthTestEnable = depth->enabled;
1250 depthStencilState.depthTestFunc = swr_convert_depth_func(depth->func);
1251 depthStencilState.depthWriteEnable = depth->writemask;
1252 SwrSetDepthStencilState(ctx->swrContext, &depthStencilState);
1253 }
1254
1255 /* Blend State */
1256 if (ctx->dirty & (SWR_NEW_BLEND |
1257 SWR_NEW_FRAMEBUFFER |
1258 SWR_NEW_DEPTH_STENCIL_ALPHA)) {
1259 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
1260
1261 SWR_BLEND_STATE blendState;
1262 memcpy(&blendState, &ctx->blend->blendState, sizeof(blendState));
1263 blendState.constantColor[0] = ctx->blend_color.color[0];
1264 blendState.constantColor[1] = ctx->blend_color.color[1];
1265 blendState.constantColor[2] = ctx->blend_color.color[2];
1266 blendState.constantColor[3] = ctx->blend_color.color[3];
1267 blendState.alphaTestReference =
1268 *((uint32_t*)&ctx->depth_stencil->alpha.ref_value);
1269
1270 // XXX MSAA
1271 blendState.sampleMask = 0;
1272 blendState.sampleCount = SWR_MULTISAMPLE_1X;
1273
1274 /* If there are no color buffers bound, disable writes on RT0
1275 * and skip loop */
1276 if (fb->nr_cbufs == 0) {
1277 blendState.renderTarget[0].writeDisableRed = 1;
1278 blendState.renderTarget[0].writeDisableGreen = 1;
1279 blendState.renderTarget[0].writeDisableBlue = 1;
1280 blendState.renderTarget[0].writeDisableAlpha = 1;
1281 SwrSetBlendFunc(ctx->swrContext, 0, NULL);
1282 }
1283 else
1284 for (int target = 0;
1285 target < std::min(SWR_NUM_RENDERTARGETS,
1286 PIPE_MAX_COLOR_BUFS);
1287 target++) {
1288 if (!fb->cbufs[target])
1289 continue;
1290
1291 struct swr_resource *colorBuffer =
1292 swr_resource(fb->cbufs[target]->texture);
1293
1294 BLEND_COMPILE_STATE compileState;
1295 memset(&compileState, 0, sizeof(compileState));
1296 compileState.format = colorBuffer->swr.format;
1297 memcpy(&compileState.blendState,
1298 &ctx->blend->compileState[target],
1299 sizeof(compileState.blendState));
1300
1301 if (compileState.blendState.blendEnable == false &&
1302 compileState.blendState.logicOpEnable == false) {
1303 SwrSetBlendFunc(ctx->swrContext, target, NULL);
1304 continue;
1305 }
1306
1307 compileState.desc.alphaTestEnable =
1308 ctx->depth_stencil->alpha.enabled;
1309 compileState.desc.independentAlphaBlendEnable =
1310 ctx->blend->pipe.independent_blend_enable;
1311 compileState.desc.alphaToCoverageEnable =
1312 ctx->blend->pipe.alpha_to_coverage;
1313 compileState.desc.sampleMaskEnable = 0; // XXX
1314 compileState.desc.numSamples = 1; // XXX
1315
1316 compileState.alphaTestFunction =
1317 swr_convert_depth_func(ctx->depth_stencil->alpha.func);
1318 compileState.alphaTestFormat = ALPHA_TEST_FLOAT32; // xxx
1319
1320 PFN_BLEND_JIT_FUNC func = NULL;
1321 auto search = ctx->blendJIT->find(compileState);
1322 if (search != ctx->blendJIT->end()) {
1323 func = search->second;
1324 } else {
1325 HANDLE hJitMgr = screen->hJitMgr;
1326 func = JitCompileBlend(hJitMgr, compileState);
1327 debug_printf("BLEND shader %p\n", func);
1328 assert(func && "Error: BlendShader = NULL");
1329
1330 ctx->blendJIT->insert(std::make_pair(compileState, func));
1331 }
1332 SwrSetBlendFunc(ctx->swrContext, target, func);
1333 }
1334
1335 SwrSetBlendState(ctx->swrContext, &blendState);
1336 }
1337
1338 if (ctx->dirty & SWR_NEW_STIPPLE) {
1339 /* XXX What to do with this one??? SWR doesn't stipple */
1340 }
1341
1342 if (ctx->dirty & (SWR_NEW_VS | SWR_NEW_SO | SWR_NEW_RASTERIZER)) {
1343 ctx->vs->soState.rasterizerDisable =
1344 ctx->rasterizer->rasterizer_discard;
1345 SwrSetSoState(ctx->swrContext, &ctx->vs->soState);
1346
1347 pipe_stream_output_info *stream_output = &ctx->vs->pipe.stream_output;
1348
1349 for (uint32_t i = 0; i < ctx->num_so_targets; i++) {
1350 SWR_STREAMOUT_BUFFER buffer = {0};
1351 if (!ctx->so_targets[i])
1352 continue;
1353 buffer.enable = true;
1354 buffer.pBuffer =
1355 (uint32_t *)swr_resource_data(ctx->so_targets[i]->buffer);
1356 buffer.bufferSize = ctx->so_targets[i]->buffer_size >> 2;
1357 buffer.pitch = stream_output->stride[i];
1358 buffer.streamOffset = ctx->so_targets[i]->buffer_offset >> 2;
1359
1360 SwrSetSoBuffers(ctx->swrContext, &buffer, i);
1361 }
1362 }
1363
1364 if (ctx->dirty & SWR_NEW_CLIP) {
1365 // shader exporting clip distances overrides all user clip planes
1366 if (ctx->rasterizer->clip_plane_enable &&
1367 !ctx->vs->info.base.num_written_clipdistance)
1368 {
1369 swr_draw_context *pDC = &ctx->swrDC;
1370 memcpy(pDC->userClipPlanes,
1371 ctx->clip.ucp,
1372 sizeof(pDC->userClipPlanes));
1373 }
1374 }
1375
1376 // set up backend state
1377 SWR_BACKEND_STATE backendState = {0};
1378 backendState.numAttributes =
1379 ctx->vs->info.base.num_outputs - 1 +
1380 (ctx->rasterizer->sprite_coord_enable ? 1 : 0);
1381 for (unsigned i = 0; i < backendState.numAttributes; i++)
1382 backendState.numComponents[i] = 4;
1383 backendState.constantInterpolationMask =
1384 ctx->rasterizer->flatshade ?
1385 ctx->fs->flatConstantMask :
1386 ctx->fs->constantMask;
1387 backendState.pointSpriteTexCoordMask = ctx->fs->pointSpriteMask;
1388
1389 SwrSetBackendState(ctx->swrContext, &backendState);
1390
1391 /* Ensure that any in-progress attachment change StoreTiles finish */
1392 if (swr_is_fence_pending(screen->flush_fence))
1393 swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
1394
1395 /* Finally, update the in-use status of all resources involved in draw */
1396 swr_update_resource_status(pipe, p_draw_info);
1397
1398 ctx->dirty = post_update_dirty_flags;
1399 }
1400
1401
1402 static struct pipe_stream_output_target *
1403 swr_create_so_target(struct pipe_context *pipe,
1404 struct pipe_resource *buffer,
1405 unsigned buffer_offset,
1406 unsigned buffer_size)
1407 {
1408 struct pipe_stream_output_target *target;
1409
1410 target = CALLOC_STRUCT(pipe_stream_output_target);
1411 if (!target)
1412 return NULL;
1413
1414 target->context = pipe;
1415 target->reference.count = 1;
1416 pipe_resource_reference(&target->buffer, buffer);
1417 target->buffer_offset = buffer_offset;
1418 target->buffer_size = buffer_size;
1419 return target;
1420 }
1421
1422 static void
1423 swr_destroy_so_target(struct pipe_context *pipe,
1424 struct pipe_stream_output_target *target)
1425 {
1426 pipe_resource_reference(&target->buffer, NULL);
1427 FREE(target);
1428 }
1429
1430 static void
1431 swr_set_so_targets(struct pipe_context *pipe,
1432 unsigned num_targets,
1433 struct pipe_stream_output_target **targets,
1434 const unsigned *offsets)
1435 {
1436 struct swr_context *swr = swr_context(pipe);
1437 uint32_t i;
1438
1439 assert(num_targets < MAX_SO_STREAMS);
1440
1441 for (i = 0; i < num_targets; i++) {
1442 pipe_so_target_reference(
1443 (struct pipe_stream_output_target **)&swr->so_targets[i],
1444 targets[i]);
1445 }
1446
1447 for (/* fall-through */; i < swr->num_so_targets; i++) {
1448 pipe_so_target_reference(
1449 (struct pipe_stream_output_target **)&swr->so_targets[i], NULL);
1450 }
1451
1452 swr->num_so_targets = num_targets;
1453
1454 swr->dirty = SWR_NEW_SO;
1455 }
1456
1457
1458 void
1459 swr_state_init(struct pipe_context *pipe)
1460 {
1461 pipe->create_blend_state = swr_create_blend_state;
1462 pipe->bind_blend_state = swr_bind_blend_state;
1463 pipe->delete_blend_state = swr_delete_blend_state;
1464
1465 pipe->create_depth_stencil_alpha_state = swr_create_depth_stencil_state;
1466 pipe->bind_depth_stencil_alpha_state = swr_bind_depth_stencil_state;
1467 pipe->delete_depth_stencil_alpha_state = swr_delete_depth_stencil_state;
1468
1469 pipe->create_rasterizer_state = swr_create_rasterizer_state;
1470 pipe->bind_rasterizer_state = swr_bind_rasterizer_state;
1471 pipe->delete_rasterizer_state = swr_delete_rasterizer_state;
1472
1473 pipe->create_sampler_state = swr_create_sampler_state;
1474 pipe->bind_sampler_states = swr_bind_sampler_states;
1475 pipe->delete_sampler_state = swr_delete_sampler_state;
1476
1477 pipe->create_sampler_view = swr_create_sampler_view;
1478 pipe->set_sampler_views = swr_set_sampler_views;
1479 pipe->sampler_view_destroy = swr_sampler_view_destroy;
1480
1481 pipe->create_vs_state = swr_create_vs_state;
1482 pipe->bind_vs_state = swr_bind_vs_state;
1483 pipe->delete_vs_state = swr_delete_vs_state;
1484
1485 pipe->create_fs_state = swr_create_fs_state;
1486 pipe->bind_fs_state = swr_bind_fs_state;
1487 pipe->delete_fs_state = swr_delete_fs_state;
1488
1489 pipe->set_constant_buffer = swr_set_constant_buffer;
1490
1491 pipe->create_vertex_elements_state = swr_create_vertex_elements_state;
1492 pipe->bind_vertex_elements_state = swr_bind_vertex_elements_state;
1493 pipe->delete_vertex_elements_state = swr_delete_vertex_elements_state;
1494
1495 pipe->set_vertex_buffers = swr_set_vertex_buffers;
1496 pipe->set_index_buffer = swr_set_index_buffer;
1497
1498 pipe->set_polygon_stipple = swr_set_polygon_stipple;
1499 pipe->set_clip_state = swr_set_clip_state;
1500 pipe->set_scissor_states = swr_set_scissor_states;
1501 pipe->set_viewport_states = swr_set_viewport_states;
1502
1503 pipe->set_framebuffer_state = swr_set_framebuffer_state;
1504
1505 pipe->set_blend_color = swr_set_blend_color;
1506 pipe->set_stencil_ref = swr_set_stencil_ref;
1507
1508 pipe->set_sample_mask = swr_set_sample_mask;
1509
1510 pipe->create_stream_output_target = swr_create_so_target;
1511 pipe->stream_output_target_destroy = swr_destroy_so_target;
1512 pipe->set_stream_output_targets = swr_set_so_targets;
1513 }