src/gallium/drivers/vc4/vc4_context.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <xf86drm.h>
  25 #include <err.h>
  26
  27 #include "pipe/p_defines.h"
  28 #include "util/ralloc.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_blitter.h"
  32 #include "indices/u_primconvert.h"
  33 #include "pipe/p_screen.h"
  34
  35 #include "vc4_screen.h"
  36 #include "vc4_context.h"
  37 #include "vc4_resource.h"
  38
  39 /**
  40  * Emits a no-op STORE_TILE_BUFFER_GENERAL.
  41  *
  42  * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
  43  * some sort before another load is triggered.
  44  */
  45 static void
  46 vc4_store_before_load(struct vc4_context *vc4, bool *coords_emitted)
  47 {
  48         if (!*coords_emitted)
  49                 return;
  50
  51         cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
  52         cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
  53         cl_u8(&vc4->rcl, (VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
  54                           VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
  55                           VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR));
  56         cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
  57
  58         *coords_emitted = false;
  59 }
  60
  61 /**
  62  * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
  63  *
  64  * The tile coordinates packet triggers a pending load if there is one, are
  65  * used for clipping during rendering, and determine where loads/stores happen
  66  * relative to their base address.
  67  */
  68 static void
  69 vc4_tile_coordinates(struct vc4_context *vc4, uint32_t x, uint32_t y,
  70                        bool *coords_emitted)
  71 {
  72         if (*coords_emitted)
  73                 return;
  74
  75         cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
  76         cl_u8(&vc4->rcl, x);
  77         cl_u8(&vc4->rcl, y);
  78
  79         *coords_emitted = true;
  80 }
  81
  82 static void
  83 vc4_setup_rcl(struct vc4_context *vc4)
  84 {
  85         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
  86         struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL;
  87         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
  88         struct vc4_resource *ztex = zsurf ? vc4_resource(zsurf->base.texture) : NULL;
  89
  90         if (!csurf)
  91                 vc4->resolve &= ~PIPE_CLEAR_COLOR0;
  92         if (!zsurf)
  93                 vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL);
  94         uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared;
  95         uint32_t width = vc4->framebuffer.width;
  96         uint32_t height = vc4->framebuffer.height;
  97         uint32_t xtiles = align(width, 64) / 64;
  98         uint32_t ytiles = align(height, 64) / 64;
  99
 100 #if 0
 101         fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n",
 102                 vc4->resolve,
 103                 vc4->cleared,
 104                 resolve_uncleared);
 105 #endif
 106
 107         cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
 108         cl_u32(&vc4->rcl, vc4->clear_color[0]);
 109         cl_u32(&vc4->rcl, vc4->clear_color[1]);
 110         cl_u32(&vc4->rcl, vc4->clear_depth);
 111         cl_u8(&vc4->rcl, vc4->clear_stencil);
 112
 113         /* The rendering mode config determines the pointer that's used for
 114          * VC4_PACKET_STORE_MS_TILE_BUFFER address computations.  The kernel
 115          * could handle a no-relocation rendering mode config and deny those
 116          * packets, but instead we just tell the kernel we're doing our color
 117          * rendering to the Z buffer, and just don't emit any of those
 118          * packets.
 119          */
 120         struct vc4_surface *render_surf = csurf ? csurf : zsurf;
 121         struct vc4_resource *render_tex = vc4_resource(render_surf->base.texture);
 122
 123         cl_start_reloc(&vc4->rcl, 1);
 124         cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
 125         cl_reloc(vc4, &vc4->rcl, render_tex->bo, render_surf->offset);
 126         cl_u16(&vc4->rcl, width);
 127         cl_u16(&vc4->rcl, height);
 128         cl_u16(&vc4->rcl, ((render_surf->tiling <<
 129                             VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
 130                            (vc4_rt_format_is_565(render_surf->base.format) ?
 131                             VC4_RENDER_CONFIG_FORMAT_BGR565 :
 132                             VC4_RENDER_CONFIG_FORMAT_RGBA8888) |
 133                            VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE));
 134
 135         /* The tile buffer normally gets cleared when the previous tile is
 136          * stored.  If the clear values changed between frames, then the tile
 137          * buffer has stale clear values in it, so we have to do a store in
 138          * None mode (no writes) so that we trigger the tile buffer clear.
 139          *
 140          * Excess clearing is only a performance cost, since per-tile contents
 141          * will be loaded/stored in the loop below.
 142          */
 143         if (vc4->cleared & (PIPE_CLEAR_COLOR0 |
 144                             PIPE_CLEAR_DEPTH |
 145                             PIPE_CLEAR_STENCIL)) {
 146                 cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
 147                 cl_u8(&vc4->rcl, 0);
 148                 cl_u8(&vc4->rcl, 0);
 149
 150                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 151                 cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
 152                 cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
 153         }
 154
 155         for (int y = 0; y < ytiles; y++) {
 156                 for (int x = 0; x < xtiles; x++) {
 157                         bool end_of_frame = (x == xtiles - 1 &&
 158                                              y == ytiles - 1);
 159                         bool coords_emitted = false;
 160
 161                         /* Note that the load doesn't actually occur until the
 162                          * tile coords packet is processed, and only one load
 163                          * may be outstanding at a time.
 164                          */
 165                         if (resolve_uncleared & PIPE_CLEAR_COLOR) {
 166                                 vc4_store_before_load(vc4, &coords_emitted);
 167
 168                                 cl_start_reloc(&vc4->rcl, 1);
 169                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 170                                 cl_u8(&vc4->rcl,
 171                                       VC4_LOADSTORE_TILE_BUFFER_COLOR |
 172                                       (csurf->tiling <<
 173                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 174                                 cl_u8(&vc4->rcl,
 175                                       vc4_rt_format_is_565(csurf->base.format) ?
 176                                       VC4_LOADSTORE_TILE_BUFFER_BGR565 :
 177                                       VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
 178                                 cl_reloc(vc4, &vc4->rcl, ctex->bo,
 179                                          csurf->offset);
 180
 181                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 182                         }
 183
 184                         if (resolve_uncleared & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 185                                 vc4_store_before_load(vc4, &coords_emitted);
 186
 187                                 cl_start_reloc(&vc4->rcl, 1);
 188                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 189                                 cl_u8(&vc4->rcl,
 190                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 191                                       (zsurf->tiling <<
 192                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 193                                 cl_u8(&vc4->rcl, 0);
 194                                 cl_reloc(vc4, &vc4->rcl, ztex->bo,
 195                                          zsurf->offset);
 196
 197                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 198                         }
 199
 200                         /* Clipping depends on tile coordinates having been
 201                          * emitted, so make sure it's happened even if
 202                          * everything was cleared to start.
 203                          */
 204                         vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 205
 206                         cl_start_reloc(&vc4->rcl, 1);
 207                         cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST);
 208                         cl_reloc(vc4, &vc4->rcl, vc4->tile_alloc,
 209                                  (y * xtiles + x) * 32);
 210
 211                         if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 212                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 213
 214                                 cl_start_reloc(&vc4->rcl, 1);
 215                                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 216                                 cl_u8(&vc4->rcl,
 217                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 218                                       (zsurf->tiling <<
 219                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 220                                 cl_u8(&vc4->rcl,
 221                                       VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR);
 222                                 cl_reloc(vc4, &vc4->rcl, ztex->bo,
 223                                          zsurf->offset |
 224                                          ((end_of_frame &&
 225                                            !(vc4->resolve & PIPE_CLEAR_COLOR0)) ?
 226                                           VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
 227
 228                                 coords_emitted = false;
 229                         }
 230
 231                         if (vc4->resolve & PIPE_CLEAR_COLOR0) {
 232                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 233                                 if (end_of_frame) {
 234                                         cl_u8(&vc4->rcl,
 235                                               VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
 236                                 } else {
 237                                         cl_u8(&vc4->rcl,
 238                                               VC4_PACKET_STORE_MS_TILE_BUFFER);
 239                                 }
 240
 241                                 coords_emitted = false;
 242                         }
 243
 244                         /* One of the bits needs to have been set that would
 245                          * have triggered an EOF.
 246                          */
 247                         assert(vc4->resolve & (PIPE_CLEAR_COLOR0 |
 248                                                PIPE_CLEAR_DEPTH |
 249                                                PIPE_CLEAR_STENCIL));
 250                         /* Any coords emitted must also have been consumed by
 251                          * a store.
 252                          */
 253                         assert(!coords_emitted);
 254                 }
 255         }
 256 }
 257
 258 void
 259 vc4_flush(struct pipe_context *pctx)
 260 {
 261         struct vc4_context *vc4 = vc4_context(pctx);
 262
 263         if (!vc4->needs_flush)
 264                 return;
 265
 266         cl_u8(&vc4->bcl, VC4_PACKET_FLUSH_ALL);
 267         cl_u8(&vc4->bcl, VC4_PACKET_NOP);
 268         cl_u8(&vc4->bcl, VC4_PACKET_HALT);
 269
 270         vc4_setup_rcl(vc4);
 271
 272         if (vc4_debug & VC4_DEBUG_CL) {
 273                 fprintf(stderr, "BCL:\n");
 274                 vc4_dump_cl(&vc4->bcl, false);
 275                 fprintf(stderr, "RCL:\n");
 276                 vc4_dump_cl(&vc4->rcl, true);
 277         }
 278
 279         struct drm_vc4_submit_cl submit;
 280         memset(&submit, 0, sizeof(submit));
 281
 282         submit.bo_handles = vc4->bo_handles.base;
 283         submit.bo_handle_count = (vc4->bo_handles.next -
 284                                   vc4->bo_handles.base) / 4;
 285         submit.bin_cl = vc4->bcl.base;
 286         submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
 287         submit.render_cl = vc4->rcl.base;
 288         submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
 289         submit.shader_rec = vc4->shader_rec.base;
 290         submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
 291         submit.shader_rec_count = vc4->shader_rec_count;
 292         submit.uniforms = vc4->uniforms.base;
 293         submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
 294
 295         if (!(vc4_debug & VC4_DEBUG_NORAST)) {
 296                 int ret;
 297
 298 #ifndef USE_VC4_SIMULATOR
 299                 ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
 300 #else
 301                 ret = vc4_simulator_flush(vc4, &submit);
 302 #endif
 303                 if (ret) {
 304                         fprintf(stderr, "VC4 submit failed\n");
 305                         abort();
 306                 }
 307         }
 308
 309         vc4_reset_cl(&vc4->bcl);
 310         vc4_reset_cl(&vc4->rcl);
 311         vc4_reset_cl(&vc4->shader_rec);
 312         vc4_reset_cl(&vc4->uniforms);
 313         vc4_reset_cl(&vc4->bo_handles);
 314         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 315         for (int i = 0; i < submit.bo_handle_count; i++)
 316                 vc4_bo_unreference(&referenced_bos[i]);
 317         vc4_reset_cl(&vc4->bo_pointers);
 318         vc4->shader_rec_count = 0;
 319
 320         vc4->needs_flush = false;
 321         vc4->draw_call_queued = false;
 322
 323         /* We have no hardware context saved between our draw calls, so we
 324          * need to flag the next draw as needing all state emitted.  Emitting
 325          * all state at the start of our draws is also what ensures that we
 326          * return to the state we need after a previous tile has finished.
 327          */
 328         vc4->dirty = ~0;
 329         vc4->resolve = 0;
 330         vc4->cleared = 0;
 331 }
 332
 333 static void
 334 vc4_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
 335                unsigned flags)
 336 {
 337         vc4_flush(pctx);
 338 }
 339
 340 /**
 341  * Flushes the current command lists if they reference the given BO.
 342  *
 343  * This helps avoid flushing the command buffers when unnecessary.
 344  */
 345 void
 346 vc4_flush_for_bo(struct pipe_context *pctx, struct vc4_bo *bo)
 347 {
 348         struct vc4_context *vc4 = vc4_context(pctx);
 349
 350         if (!vc4->needs_flush)
 351                 return;
 352
 353         /* Walk all the referenced BOs in the drawing command list to see if
 354          * they match.
 355          */
 356         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 357         for (int i = 0; i < (vc4->bo_handles.next -
 358                              vc4->bo_handles.base) / 4; i++) {
 359                 if (referenced_bos[i] == bo) {
 360                         vc4_flush(pctx);
 361                         return;
 362                 }
 363         }
 364
 365         /* Also check for the Z/color buffers, since the references to those
 366          * are only added immediately before submit.
 367          */
 368         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
 369         if (csurf) {
 370                 struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
 371                 if (ctex->bo == bo) {
 372                         vc4_flush(pctx);
 373                         return;
 374                 }
 375         }
 376
 377         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
 378         if (zsurf) {
 379                 struct vc4_resource *ztex =
 380                         vc4_resource(zsurf->base.texture);
 381                 if (ztex->bo == bo) {
 382                         vc4_flush(pctx);
 383                         return;
 384                 }
 385         }
 386 }
 387
 388 static void
 389 vc4_context_destroy(struct pipe_context *pctx)
 390 {
 391         struct vc4_context *vc4 = vc4_context(pctx);
 392
 393         if (vc4->blitter)
 394                 util_blitter_destroy(vc4->blitter);
 395
 396         if (vc4->primconvert)
 397                 util_primconvert_destroy(vc4->primconvert);
 398
 399         util_slab_destroy(&vc4->transfer_pool);
 400
 401         ralloc_free(vc4);
 402 }
 403
 404 struct pipe_context *
 405 vc4_context_create(struct pipe_screen *pscreen, void *priv)
 406 {
 407         struct vc4_screen *screen = vc4_screen(pscreen);
 408         struct vc4_context *vc4;
 409
 410         /* Prevent dumping of the shaders built during context setup. */
 411         uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
 412         vc4_debug &= ~VC4_DEBUG_SHADERDB;
 413
 414         vc4 = rzalloc(NULL, struct vc4_context);
 415         if (vc4 == NULL)
 416                 return NULL;
 417         struct pipe_context *pctx = &vc4->base;
 418
 419         vc4->screen = screen;
 420
 421         pctx->screen = pscreen;
 422         pctx->priv = priv;
 423         pctx->destroy = vc4_context_destroy;
 424         pctx->flush = vc4_pipe_flush;
 425
 426         vc4_draw_init(pctx);
 427         vc4_state_init(pctx);
 428         vc4_program_init(pctx);
 429         vc4_query_init(pctx);
 430         vc4_resource_context_init(pctx);
 431
 432         vc4_init_cl(vc4, &vc4->bcl);
 433         vc4_init_cl(vc4, &vc4->rcl);
 434         vc4_init_cl(vc4, &vc4->shader_rec);
 435         vc4_init_cl(vc4, &vc4->bo_handles);
 436
 437         vc4->dirty = ~0;
 438         vc4->fd = screen->fd;
 439
 440         util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
 441                          16, UTIL_SLAB_SINGLETHREADED);
 442         vc4->blitter = util_blitter_create(pctx);
 443         if (!vc4->blitter)
 444                 goto fail;
 445
 446         vc4->primconvert = util_primconvert_create(pctx,
 447                                                    (1 << PIPE_PRIM_QUADS) - 1);
 448         if (!vc4->primconvert)
 449                 goto fail;
 450
 451         vc4_debug |= saved_shaderdb_flag;
 452
 453         return &vc4->base;
 454
 455 fail:
 456         pctx->destroy(pctx);
 457         return NULL;
 458 }