src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifdef USE_VC4_SIMULATOR
  43 #define using_vc4_simulator true
  44 #else
  45 #define using_vc4_simulator false
  46 #endif
  47
  48 #define VC4_DIRTY_BLEND         (1 <<  0)
  49 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  50 #define VC4_DIRTY_ZSA           (1 <<  2)
  51 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  52 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  53
  54 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  55 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  56 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  57 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  58 #define VC4_DIRTY_STIPPLE       (1 << 11)
  59 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  60 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  61 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  62 #define VC4_DIRTY_VTXBUF        (1 << 15)
  63 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  64 #define VC4_DIRTY_SCISSOR       (1 << 17)
  65 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  66 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  67 #define VC4_DIRTY_CLIP          (1 << 20)
  68 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  69 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  70 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  71 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  72 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  73 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  74
  75 struct vc4_sampler_view {
  76         struct pipe_sampler_view base;
  77         uint32_t texture_p0;
  78         uint32_t texture_p1;
  79         bool force_first_level;
  80 };
  81
  82 struct vc4_sampler_state {
  83         struct pipe_sampler_state base;
  84         uint32_t texture_p1;
  85 };
  86
  87 struct vc4_texture_stateobj {
  88         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  89         unsigned num_textures;
  90         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  91         unsigned num_samplers;
  92 };
  93
  94 struct vc4_shader_uniform_info {
  95         enum quniform_contents *contents;
  96         uint32_t *data;
  97         uint32_t count;
  98         uint32_t num_texture_samples;
  99 };
 100
 101 struct vc4_uncompiled_shader {
 102         /** A name for this program, so you can track it in shader-db output. */
 103         uint32_t program_id;
 104         /** How many variants of this program were compiled, for shader-db. */
 105         uint32_t compiled_variant_count;
 106         struct pipe_shader_state base;
 107 };
 108
 109 struct vc4_ubo_range {
 110         /**
 111          * offset in bytes from the start of the ubo where this range is
 112          * uploaded.
 113          *
 114          * Only set once used is set.
 115          */
 116         uint32_t dst_offset;
 117
 118         /**
 119          * offset in bytes from the start of the gallium uniforms where the
 120          * data comes from.
 121          */
 122         uint32_t src_offset;
 123
 124         /** size in bytes of this ubo range */
 125         uint32_t size;
 126 };
 127
 128 struct vc4_fs_inputs {
 129         /**
 130          * Array of the meanings of the VPM inputs this shader needs.
 131          *
 132          * It doesn't include those that aren't part of the VPM, like
 133          * point/line coordinates.
 134          */
 135         struct vc4_varying_slot *input_slots;
 136         uint32_t num_inputs;
 137 };
 138
 139 struct vc4_compiled_shader {
 140         uint64_t program_id;
 141         struct vc4_bo *bo;
 142
 143         struct vc4_shader_uniform_info uniforms;
 144
 145         struct vc4_ubo_range *ubo_ranges;
 146         uint32_t num_ubo_ranges;
 147         uint32_t ubo_size;
 148         /**
 149          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 150          * uniforms have to be rewritten (and therefore the shader state
 151          * reemitted).
 152          */
 153         uint32_t uniform_dirty_bits;
 154
 155         /** bitmask of which inputs are color inputs, for flat shade handling. */
 156         uint32_t color_inputs;
 157
 158         bool disable_early_z;
 159
 160         /* Set if the compile failed, likely due to register allocation
 161          * failure.  In this case, we have no shader to run and should not try
 162          * to do any draws.
 163          */
 164         bool failed;
 165
 166         uint8_t num_inputs;
 167
 168         /* Byte offsets for the start of the vertex attributes 0-7, and the
 169          * total size as "attribute" 8.
 170          */
 171         uint8_t vattr_offsets[9];
 172         uint8_t vattrs_live;
 173
 174         const struct vc4_fs_inputs *fs_inputs;
 175 };
 176
 177 struct vc4_program_stateobj {
 178         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 179         struct vc4_compiled_shader *cs, *vs, *fs;
 180 };
 181
 182 struct vc4_constbuf_stateobj {
 183         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 184         uint32_t enabled_mask;
 185         uint32_t dirty_mask;
 186 };
 187
 188 struct vc4_vertexbuf_stateobj {
 189         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 190         unsigned count;
 191         uint32_t enabled_mask;
 192         uint32_t dirty_mask;
 193 };
 194
 195 struct vc4_vertex_stateobj {
 196         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 197         unsigned num_elements;
 198 };
 199
 200 /* Hash table key for vc4->jobs */
 201 struct vc4_job_key {
 202         struct pipe_surface *cbuf;
 203         struct pipe_surface *zsbuf;
 204 };
 205
 206 /**
 207  * A complete bin/render job.
 208  *
 209  * This is all of the state necessary to submit a bin/render to the kernel.
 210  * We want to be able to have multiple in progress at a time, so that we don't
 211  * need to flush an existing CL just to switch to rendering to a new render
 212  * target (which would mean reading back from the old render target when
 213  * starting to render to it again).
 214  */
 215 struct vc4_job {
 216         struct vc4_cl bcl;
 217         struct vc4_cl shader_rec;
 218         struct vc4_cl uniforms;
 219         struct vc4_cl bo_handles;
 220         struct vc4_cl bo_pointers;
 221         uint32_t shader_rec_count;
 222
 223         /** @{ Surfaces to submit rendering for. */
 224         struct pipe_surface *color_read;
 225         struct pipe_surface *color_write;
 226         struct pipe_surface *zs_read;
 227         struct pipe_surface *zs_write;
 228         struct pipe_surface *msaa_color_write;
 229         struct pipe_surface *msaa_zs_write;
 230         /** @} */
 231         /** @{
 232          * Bounding box of the scissor across all queued drawing.
 233          *
 234          * Note that the max values are exclusive.
 235          */
 236         uint32_t draw_min_x;
 237         uint32_t draw_min_y;
 238         uint32_t draw_max_x;
 239         uint32_t draw_max_y;
 240         /** @} */
 241         /** @{
 242          * Width/height of the color framebuffer being rendered to,
 243          * for VC4_TILE_RENDERING_MODE_CONFIG.
 244         */
 245         uint32_t draw_width;
 246         uint32_t draw_height;
 247         /** @} */
 248         /** @{ Tile information, depending on MSAA and float color buffer. */
 249         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 250         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 251
 252         uint32_t tile_width; /** @< Width of a tile. */
 253         uint32_t tile_height; /** @< Height of a tile. */
 254         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 255         bool msaa;
 256         /** @} */
 257
 258         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 259          * first rendering.
 260          */
 261         uint32_t cleared;
 262         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 263          * (either clears or draws).
 264          */
 265         uint32_t resolve;
 266         uint32_t clear_color[2];
 267         uint32_t clear_depth; /**< 24-bit unorm depth */
 268         uint8_t clear_stencil;
 269
 270         /**
 271          * Set if some drawing (triangles, blits, or just a glClear()) has
 272          * been done to the FBO, meaning that we need to
 273          * DRM_IOCTL_VC4_SUBMIT_CL.
 274          */
 275         bool needs_flush;
 276
 277         /**
 278          * Number of draw calls (not counting full buffer clears) queued in
 279          * the current job.
 280          */
 281         uint32_t draw_calls_queued;
 282
 283         struct vc4_job_key key;
 284 };
 285
 286 struct vc4_context {
 287         struct pipe_context base;
 288
 289         int fd;
 290         struct vc4_screen *screen;
 291
 292         /** The 3D rendering job for the currently bound FBO. */
 293         struct vc4_job *job;
 294
 295         /* Map from struct vc4_job_key to the job for that FBO.
 296          */
 297         struct hash_table *jobs;
 298
 299         /**
 300          * Map from vc4_resource to a job writing to that resource.
 301          *
 302          * Primarily for flushing jobs rendering to textures that are now
 303          * being read from.
 304          */
 305         struct hash_table *write_jobs;
 306
 307         struct slab_child_pool transfer_pool;
 308         struct blitter_context *blitter;
 309
 310         /** bitfield of VC4_DIRTY_* */
 311         uint32_t dirty;
 312
 313         struct primconvert_context *primconvert;
 314
 315         struct hash_table *fs_cache, *vs_cache;
 316         struct set *fs_inputs_set;
 317         uint32_t next_uncompiled_program_id;
 318         uint64_t next_compiled_program_id;
 319
 320         struct ra_regs *regs;
 321         unsigned int reg_class_any[2];
 322         unsigned int reg_class_a_or_b[2];
 323         unsigned int reg_class_a_or_b_or_acc[2];
 324         unsigned int reg_class_r0_r3;
 325         unsigned int reg_class_r4_or_a[2];
 326         unsigned int reg_class_a[2];
 327
 328         uint8_t prim_mode;
 329
 330         /** Maximum index buffer valid for the current shader_rec. */
 331         uint32_t max_index;
 332         /** Last index bias baked into the current shader_rec. */
 333         uint32_t last_index_bias;
 334
 335         /** Seqno of the last CL flush's job. */
 336         uint64_t last_emit_seqno;
 337
 338         struct u_upload_mgr *uploader;
 339
 340         /** @{ Current pipeline state objects */
 341         struct pipe_scissor_state scissor;
 342         struct pipe_blend_state *blend;
 343         struct vc4_rasterizer_state *rasterizer;
 344         struct vc4_depth_stencil_alpha_state *zsa;
 345
 346         struct vc4_texture_stateobj verttex, fragtex;
 347
 348         struct vc4_program_stateobj prog;
 349
 350         struct vc4_vertex_stateobj *vtx;
 351
 352         struct {
 353                 struct pipe_blend_color f;
 354                 uint8_t ub[4];
 355         } blend_color;
 356         struct pipe_stencil_ref stencil_ref;
 357         unsigned sample_mask;
 358         struct pipe_framebuffer_state framebuffer;
 359         struct pipe_poly_stipple stipple;
 360         struct pipe_clip_state clip;
 361         struct pipe_viewport_state viewport;
 362         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 363         struct vc4_vertexbuf_stateobj vertexbuf;
 364         struct pipe_index_buffer indexbuf;
 365         /** @} */
 366 };
 367
 368 struct vc4_rasterizer_state {
 369         struct pipe_rasterizer_state base;
 370
 371         /* VC4_CONFIGURATION_BITS */
 372         uint8_t config_bits[3];
 373
 374         float point_size;
 375
 376         /**
 377          * Half-float (1/8/7 bits) value of polygon offset units for
 378          * VC4_PACKET_DEPTH_OFFSET
 379          */
 380         uint16_t offset_units;
 381         /**
 382          * Half-float (1/8/7 bits) value of polygon offset scale for
 383          * VC4_PACKET_DEPTH_OFFSET
 384          */
 385         uint16_t offset_factor;
 386 };
 387
 388 struct vc4_depth_stencil_alpha_state {
 389         struct pipe_depth_stencil_alpha_state base;
 390
 391         /* VC4_CONFIGURATION_BITS */
 392         uint8_t config_bits[3];
 393
 394         /** Uniforms for stencil state.
 395          *
 396          * Index 0 is either the front config, or the front-and-back config.
 397          * Index 1 is the back config if doing separate back stencil.
 398          * Index 2 is the writemask config if it's not a common mask value.
 399          */
 400         uint32_t stencil_uniforms[3];
 401 };
 402
 403 #define perf_debug(...) do {                            \
 404         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 405                 fprintf(stderr, __VA_ARGS__);           \
 406 } while (0)
 407
 408 static inline struct vc4_context *
 409 vc4_context(struct pipe_context *pcontext)
 410 {
 411         return (struct vc4_context *)pcontext;
 412 }
 413
 414 static inline struct vc4_sampler_view *
 415 vc4_sampler_view(struct pipe_sampler_view *psview)
 416 {
 417         return (struct vc4_sampler_view *)psview;
 418 }
 419
 420 static inline struct vc4_sampler_state *
 421 vc4_sampler_state(struct pipe_sampler_state *psampler)
 422 {
 423         return (struct vc4_sampler_state *)psampler;
 424 }
 425
 426 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 427                                         void *priv, unsigned flags);
 428 void vc4_draw_init(struct pipe_context *pctx);
 429 void vc4_state_init(struct pipe_context *pctx);
 430 void vc4_program_init(struct pipe_context *pctx);
 431 void vc4_program_fini(struct pipe_context *pctx);
 432 void vc4_query_init(struct pipe_context *pctx);
 433 void vc4_simulator_init(struct vc4_screen *screen);
 434 void vc4_simulator_destroy(struct vc4_screen *screen);
 435 int vc4_simulator_flush(struct vc4_context *vc4,
 436                         struct drm_vc4_submit_cl *args,
 437                         struct vc4_job *job);
 438 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 439 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 440                                     int handle, uint32_t size);
 441
 442 static inline int
 443 vc4_ioctl(int fd, unsigned long request, void *arg)
 444 {
 445         if (using_vc4_simulator)
 446                 return vc4_simulator_ioctl(fd, request, arg);
 447         else
 448                 return drmIoctl(fd, request, arg);
 449 }
 450
 451 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 452 void vc4_write_uniforms(struct vc4_context *vc4,
 453                         struct vc4_compiled_shader *shader,
 454                         struct vc4_constbuf_stateobj *cb,
 455                         struct vc4_texture_stateobj *texstate);
 456
 457 void vc4_flush(struct pipe_context *pctx);
 458 void vc4_job_init(struct vc4_context *vc4);
 459 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 460                             struct pipe_surface *cbuf,
 461                             struct pipe_surface *zsbuf);
 462 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 463
 464 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 465 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 466                                      struct pipe_resource *prsc);
 467 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 468                                      struct pipe_resource *prsc);
 469 void vc4_emit_state(struct pipe_context *pctx);
 470 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 471 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 472 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 473
 474 bool vc4_rt_format_supported(enum pipe_format f);
 475 bool vc4_rt_format_is_565(enum pipe_format f);
 476 bool vc4_tex_format_supported(enum pipe_format f);
 477 uint8_t vc4_get_tex_format(enum pipe_format f);
 478 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 479 void vc4_init_query_functions(struct vc4_context *vc4);
 480 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 481 void vc4_blitter_save(struct vc4_context *vc4);
 482 #endif /* VC4_CONTEXT_H */