vc4: Fix leak of the compiled shader programs in the cache.
[mesa.git] / src / gallium / drivers / vc4 / vc4_context.h
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef VC4_CONTEXT_H
26 #define VC4_CONTEXT_H
27
28 #include <stdio.h>
29
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/u_slab.h"
33
34 #define __user
35 #include "vc4_drm.h"
36 #include "vc4_bufmgr.h"
37 #include "vc4_resource.h"
38 #include "vc4_cl.h"
39 #include "vc4_qir.h"
40
41 #define VC4_DIRTY_BLEND (1 << 0)
42 #define VC4_DIRTY_RASTERIZER (1 << 1)
43 #define VC4_DIRTY_ZSA (1 << 2)
44 #define VC4_DIRTY_FRAGTEX (1 << 3)
45 #define VC4_DIRTY_VERTTEX (1 << 4)
46 #define VC4_DIRTY_TEXSTATE (1 << 5)
47 #define VC4_DIRTY_PROG (1 << 6)
48 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
49 #define VC4_DIRTY_STENCIL_REF (1 << 8)
50 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
51 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
52 #define VC4_DIRTY_STIPPLE (1 << 11)
53 #define VC4_DIRTY_VIEWPORT (1 << 12)
54 #define VC4_DIRTY_CONSTBUF (1 << 13)
55 #define VC4_DIRTY_VTXSTATE (1 << 14)
56 #define VC4_DIRTY_VTXBUF (1 << 15)
57 #define VC4_DIRTY_INDEXBUF (1 << 16)
58 #define VC4_DIRTY_SCISSOR (1 << 17)
59 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
60 #define VC4_DIRTY_PRIM_MODE (1 << 19)
61 #define VC4_DIRTY_CLIP (1 << 20)
62
63 #define VC4_SHADER_DIRTY_VP (1 << 0)
64 #define VC4_SHADER_DIRTY_FP (1 << 1)
65
66 struct vc4_texture_stateobj {
67 struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
68 unsigned num_textures;
69 struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
70 unsigned num_samplers;
71 unsigned dirty_samplers;
72 };
73
74 struct vc4_shader_uniform_info {
75 enum quniform_contents *contents;
76 uint32_t *data;
77 uint32_t count;
78 uint32_t num_texture_samples;
79 };
80
81 struct vc4_uncompiled_shader {
82 /** A name for this program, so you can track it in shader-db output. */
83 uint32_t program_id;
84 /** How many variants of this program were compiled, for shader-db. */
85 uint32_t compiled_variant_count;
86 struct pipe_shader_state base;
87 const struct tgsi_token *twoside_tokens;
88 };
89
90 struct vc4_ubo_range {
91 /**
92 * offset in bytes from the start of the ubo where this range is
93 * uploaded.
94 *
95 * Only set once used is set.
96 */
97 uint32_t dst_offset;
98
99 /**
100 * offset in bytes from the start of the gallium uniforms where the
101 * data comes from.
102 */
103 uint32_t src_offset;
104
105 /** size in bytes of this ubo range */
106 uint32_t size;
107 };
108
109 struct vc4_compiled_shader {
110 uint64_t program_id;
111 struct vc4_bo *bo;
112
113 struct vc4_shader_uniform_info uniforms;
114
115 struct vc4_ubo_range *ubo_ranges;
116 uint32_t num_ubo_ranges;
117 uint32_t ubo_size;
118
119 /** bitmask of which inputs are color inputs, for flat shade handling. */
120 uint32_t color_inputs;
121
122 uint8_t num_inputs;
123
124 /**
125 * Array of the meanings of the VPM inputs this shader needs.
126 *
127 * It doesn't include those that aren't part of the VPM, like
128 * point/line coordinates.
129 */
130 struct vc4_varying_semantic *input_semantics;
131 };
132
133 struct vc4_program_stateobj {
134 struct vc4_uncompiled_shader *bind_vs, *bind_fs;
135 struct vc4_compiled_shader *cs, *vs, *fs;
136 uint32_t dirty;
137 uint8_t num_exports;
138 /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
139 * for TGSI_SEMANTIC_GENERIC. Special vs exports (position and point-
140 * size) are not included in this
141 */
142 uint8_t export_linkage[63];
143 };
144
145 struct vc4_constbuf_stateobj {
146 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
147 uint32_t enabled_mask;
148 uint32_t dirty_mask;
149 };
150
151 struct vc4_vertexbuf_stateobj {
152 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
153 unsigned count;
154 uint32_t enabled_mask;
155 uint32_t dirty_mask;
156 };
157
158 struct vc4_vertex_stateobj {
159 struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
160 unsigned num_elements;
161 };
162
163 struct vc4_context {
164 struct pipe_context base;
165
166 int fd;
167 struct vc4_screen *screen;
168
169 struct vc4_cl bcl;
170 struct vc4_cl rcl;
171 struct vc4_cl shader_rec;
172 struct vc4_cl uniforms;
173 struct vc4_cl bo_handles;
174 struct vc4_cl bo_pointers;
175 uint32_t shader_rec_count;
176
177 struct vc4_bo *tile_alloc;
178 struct vc4_bo *tile_state;
179
180 struct util_slab_mempool transfer_pool;
181 struct blitter_context *blitter;
182
183 /** bitfield of VC4_DIRTY_* */
184 uint32_t dirty;
185 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
186 * first rendering.
187 */
188 uint32_t cleared;
189 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
190 * (either clears or draws).
191 */
192 uint32_t resolve;
193 uint32_t clear_color[2];
194 uint32_t clear_depth; /**< 24-bit unorm depth */
195 uint8_t clear_stencil;
196
197 /**
198 * Set if some drawing (triangles, blits, or just a glClear()) has
199 * been done to the FBO, meaning that we need to
200 * DRM_IOCTL_VC4_SUBMIT_CL.
201 */
202 bool needs_flush;
203
204 /**
205 * Set when needs_flush, and the queued rendering is not just composed
206 * of full-buffer clears.
207 */
208 bool draw_call_queued;
209
210 struct primconvert_context *primconvert;
211
212 struct hash_table *fs_cache, *vs_cache;
213 uint32_t next_uncompiled_program_id;
214 uint64_t next_compiled_program_id;
215
216 struct ra_regs *regs;
217 unsigned int reg_class_any;
218 unsigned int reg_class_a;
219
220 uint8_t prim_mode;
221
222 /** Seqno of the last CL flush's job. */
223 uint64_t last_emit_seqno;
224
225 /** @{ Current pipeline state objects */
226 struct pipe_scissor_state scissor;
227 struct pipe_blend_state *blend;
228 struct vc4_rasterizer_state *rasterizer;
229 struct vc4_depth_stencil_alpha_state *zsa;
230
231 struct vc4_texture_stateobj verttex, fragtex;
232
233 struct vc4_program_stateobj prog;
234
235 struct vc4_vertex_stateobj *vtx;
236
237 struct pipe_blend_color blend_color;
238 struct pipe_stencil_ref stencil_ref;
239 unsigned sample_mask;
240 struct pipe_framebuffer_state framebuffer;
241 struct pipe_poly_stipple stipple;
242 struct pipe_clip_state clip;
243 struct pipe_viewport_state viewport;
244 struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
245 struct vc4_vertexbuf_stateobj vertexbuf;
246 struct pipe_index_buffer indexbuf;
247 /** @} */
248 };
249
250 struct vc4_rasterizer_state {
251 struct pipe_rasterizer_state base;
252
253 /* VC4_CONFIGURATION_BITS */
254 uint8_t config_bits[3];
255
256 float point_size;
257
258 /**
259 * Half-float (1/8/7 bits) value of polygon offset units for
260 * VC4_PACKET_DEPTH_OFFSET
261 */
262 uint16_t offset_units;
263 /**
264 * Half-float (1/8/7 bits) value of polygon offset scale for
265 * VC4_PACKET_DEPTH_OFFSET
266 */
267 uint16_t offset_factor;
268 };
269
270 struct vc4_depth_stencil_alpha_state {
271 struct pipe_depth_stencil_alpha_state base;
272
273 /* VC4_CONFIGURATION_BITS */
274 uint8_t config_bits[3];
275
276 /** Uniforms for stencil state.
277 *
278 * Index 0 is either the front config, or the front-and-back config.
279 * Index 1 is the back config if doing separate back stencil.
280 * Index 2 is the writemask config if it's not a common mask value.
281 */
282 uint32_t stencil_uniforms[3];
283 };
284
285 static inline struct vc4_context *
286 vc4_context(struct pipe_context *pcontext)
287 {
288 return (struct vc4_context *)pcontext;
289 }
290
291 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
292 void *priv);
293 void vc4_draw_init(struct pipe_context *pctx);
294 void vc4_state_init(struct pipe_context *pctx);
295 void vc4_program_init(struct pipe_context *pctx);
296 void vc4_program_fini(struct pipe_context *pctx);
297 void vc4_query_init(struct pipe_context *pctx);
298 void vc4_simulator_init(struct vc4_screen *screen);
299 int vc4_simulator_flush(struct vc4_context *vc4,
300 struct drm_vc4_submit_cl *args);
301
302 void vc4_write_uniforms(struct vc4_context *vc4,
303 struct vc4_compiled_shader *shader,
304 struct vc4_constbuf_stateobj *cb,
305 struct vc4_texture_stateobj *texstate);
306
307 void vc4_flush(struct pipe_context *pctx);
308 bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo);
309 void vc4_emit_state(struct pipe_context *pctx);
310 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
311 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
312 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
313
314 bool vc4_rt_format_supported(enum pipe_format f);
315 bool vc4_rt_format_is_565(enum pipe_format f);
316 bool vc4_tex_format_supported(enum pipe_format f);
317 uint8_t vc4_get_tex_format(enum pipe_format f);
318 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
319 void vc4_init_query_functions(struct vc4_context *vc4);
320 #endif /* VC4_CONTEXT_H */