src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_format.h"
  26 #include "util/u_pack_color.h"
  27 #include "indices/u_primconvert.h"
  28
  29 #include "vc4_context.h"
  30 #include "vc4_resource.h"
  31
  32 /**
  33  * Does the initial bining command list setup for drawing to a given FBO.
  34  */
  35 static void
  36 vc4_start_draw(struct vc4_context *vc4)
  37 {
  38         if (vc4->needs_flush)
  39                 return;
  40
  41         uint32_t width = vc4->framebuffer.width;
  42         uint32_t height = vc4->framebuffer.height;
  43         uint32_t tilew = align(width, 64) / 64;
  44         uint32_t tileh = align(height, 64) / 64;
  45
  46         /* Tile alloc memory setup: We use an initial alloc size of 32b.  The
  47          * hardware then aligns that to 256b (we use 4096, because all of our
  48          * BO allocations align to that anyway), then for some reason the
  49          * simulator wants an extra page available, even if you have overflow
  50          * memory set up.
  51          */
  52         uint32_t tile_alloc_size = 32 * tilew * tileh;
  53         tile_alloc_size = align(tile_alloc_size, 4096);
  54         tile_alloc_size += 4096;
  55         uint32_t tile_state_size = 48 * tilew * tileh;
  56         if (!vc4->tile_alloc || vc4->tile_alloc->size < tile_alloc_size) {
  57                 vc4_bo_unreference(&vc4->tile_alloc);
  58                 vc4->tile_alloc = vc4_bo_alloc(vc4->screen, tile_alloc_size,
  59                                                "tile_alloc");
  60         }
  61         if (!vc4->tile_state || vc4->tile_state->size < tile_state_size) {
  62                 vc4_bo_unreference(&vc4->tile_state);
  63                 vc4->tile_state = vc4_bo_alloc(vc4->screen, tile_state_size,
  64                                                "tile_state");
  65         }
  66
  67         //   Tile state data is 48 bytes per tile, I think it can be thrown away
  68         //   as soon as binning is finished.
  69         cl_start_reloc(&vc4->bcl, 2);
  70         cl_u8(&vc4->bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
  71         cl_reloc(vc4, &vc4->bcl, vc4->tile_alloc, 0);
  72         cl_u32(&vc4->bcl, vc4->tile_alloc->size);
  73         cl_reloc(vc4, &vc4->bcl, vc4->tile_state, 0);
  74         cl_u8(&vc4->bcl, tilew);
  75         cl_u8(&vc4->bcl, tileh);
  76         cl_u8(&vc4->bcl,
  77               VC4_BIN_CONFIG_AUTO_INIT_TSDA |
  78               VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 |
  79               VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32);
  80
  81         cl_u8(&vc4->bcl, VC4_PACKET_START_TILE_BINNING);
  82
  83         vc4->needs_flush = true;
  84         vc4->draw_call_queued = true;
  85 }
  86
  87 static void
  88 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
  89 {
  90         struct vc4_context *vc4 = vc4_context(pctx);
  91
  92         if (info->mode >= PIPE_PRIM_QUADS) {
  93                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
  94                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
  95                 util_primconvert_draw_vbo(vc4->primconvert, info);
  96                 return;
  97         }
  98
  99         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 100         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 101
 102         if (vc4->prim_mode != info->mode) {
 103                 vc4->prim_mode = info->mode;
 104                 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 105         }
 106
 107         vc4_start_draw(vc4);
 108         vc4_update_compiled_shaders(vc4, info->mode);
 109
 110         vc4_emit_state(pctx);
 111         vc4->dirty = 0;
 112
 113         vc4_write_uniforms(vc4, vc4->prog.fs,
 114                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 115                            &vc4->fragtex);
 116         vc4_write_uniforms(vc4, vc4->prog.vs,
 117                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 118                            &vc4->verttex);
 119         vc4_write_uniforms(vc4, vc4->prog.cs,
 120                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 121                            &vc4->verttex);
 122
 123         /* The simulator throws a fit if VS or CS don't read an attribute, so
 124          * we emit a dummy read.
 125          */
 126         uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
 127         /* Emit the shader record. */
 128         cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
 129         cl_u16(&vc4->shader_rec,
 130                VC4_SHADER_FLAG_ENABLE_CLIPPING |
 131                ((info->mode == PIPE_PRIM_POINTS &&
 132                  vc4->rasterizer->base.point_size_per_vertex) ?
 133                 VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
 134         cl_u8(&vc4->shader_rec, 0); /* fs num uniforms (unused) */
 135         cl_u8(&vc4->shader_rec, vc4->prog.fs->num_inputs);
 136         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.fs->bo, 0);
 137         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 138
 139         cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
 140         cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* vs attribute array bitfield */
 141         cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* vs total attribute size */
 142         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
 143         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 144
 145         cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
 146         cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* cs attribute array bitfield */
 147         cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* cs total attribute size */
 148         cl_reloc(vc4, &vc4->shader_rec, vc4->prog.cs->bo, 0);
 149         cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
 150
 151         uint32_t max_index = 0xffff;
 152         for (int i = 0; i < vtx->num_elements; i++) {
 153                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 154                 struct pipe_vertex_buffer *vb =
 155                         &vertexbuf->vb[elem->vertex_buffer_index];
 156                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 157                 uint32_t offset = vb->buffer_offset + elem->src_offset;
 158                 uint32_t vb_size = rsc->bo->size - offset;
 159                 uint32_t elem_size =
 160                         util_format_get_blocksize(elem->src_format);
 161
 162                 cl_reloc(vc4, &vc4->shader_rec, rsc->bo, offset);
 163                 cl_u8(&vc4->shader_rec, elem_size - 1);
 164                 cl_u8(&vc4->shader_rec, vb->stride);
 165                 cl_u8(&vc4->shader_rec, i * 16); /* VS VPM offset */
 166                 cl_u8(&vc4->shader_rec, i * 16); /* CS VPM offset */
 167
 168                 if (vb->stride > 0) {
 169                         max_index = MIN2(max_index,
 170                                          (vb_size - elem_size) / vb->stride);
 171                 }
 172         }
 173
 174         if (vtx->num_elements == 0) {
 175                 assert(num_elements_emit == 1);
 176                 struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
 177                 cl_reloc(vc4, &vc4->shader_rec, bo, 0);
 178                 cl_u8(&vc4->shader_rec, 16 - 1); /* element size */
 179                 cl_u8(&vc4->shader_rec, 0); /* stride */
 180                 cl_u8(&vc4->shader_rec, 0); /* VS VPM offset */
 181                 cl_u8(&vc4->shader_rec, 0); /* CS VPM offset */
 182                 vc4_bo_unreference(&bo);
 183         }
 184
 185         /* the actual draw call. */
 186         cl_u8(&vc4->bcl, VC4_PACKET_GL_SHADER_STATE);
 187         assert(vtx->num_elements <= 8);
 188         /* Note that number of attributes == 0 in the packet means 8
 189          * attributes.  This field also contains the offset into shader_rec.
 190          */
 191         cl_u32(&vc4->bcl, num_elements_emit & 0x7);
 192
 193         /* Note that the primitive type fields match with OpenGL/gallium
 194          * definitions, up to but not including QUADS.
 195          */
 196         if (info->indexed) {
 197                 struct vc4_resource *rsc = vc4_resource(vc4->indexbuf.buffer);
 198
 199                 assert(vc4->indexbuf.index_size == 1 ||
 200                        vc4->indexbuf.index_size == 2);
 201
 202                 cl_start_reloc(&vc4->bcl, 1);
 203                 cl_u8(&vc4->bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 204                 cl_u8(&vc4->bcl,
 205                       info->mode |
 206                       (vc4->indexbuf.index_size == 2 ?
 207                        VC4_INDEX_BUFFER_U16:
 208                        VC4_INDEX_BUFFER_U8));
 209                 cl_u32(&vc4->bcl, info->count);
 210                 cl_reloc(vc4, &vc4->bcl, rsc->bo, vc4->indexbuf.offset);
 211                 cl_u32(&vc4->bcl, max_index);
 212         } else {
 213                 cl_u8(&vc4->bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 214                 cl_u8(&vc4->bcl, info->mode);
 215                 cl_u32(&vc4->bcl, info->count);
 216                 cl_u32(&vc4->bcl, info->start);
 217         }
 218
 219         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 220                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 221         }
 222         if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
 223                 vc4->resolve |= PIPE_CLEAR_STENCIL;
 224         vc4->resolve |= PIPE_CLEAR_COLOR0;
 225
 226         vc4->shader_rec_count++;
 227
 228         if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
 229                 vc4_flush(pctx);
 230 }
 231
 232 static uint32_t
 233 pack_rgba(enum pipe_format format, const float *rgba)
 234 {
 235         union util_color uc;
 236         util_pack_color(rgba, format, &uc);
 237         return uc.ui[0];
 238 }
 239
 240 static void
 241 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 242           const union pipe_color_union *color, double depth, unsigned stencil)
 243 {
 244         struct vc4_context *vc4 = vc4_context(pctx);
 245
 246         /* We can't flag new buffers for clearing once we've queued draws.  We
 247          * could avoid this by using the 3d engine to clear.
 248          */
 249         if (vc4->draw_call_queued)
 250                 vc4_flush(pctx);
 251
 252         if (buffers & PIPE_CLEAR_COLOR0) {
 253                 vc4->clear_color[0] = vc4->clear_color[1] =
 254                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 255                                   color->f);
 256         }
 257
 258         if (buffers & PIPE_CLEAR_DEPTH) {
 259                 /* Though the depth buffer is stored with Z in the high 24,
 260                  * for this field we just need to store it in the low 24.
 261                  */
 262                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 263         }
 264
 265         if (buffers & PIPE_CLEAR_STENCIL)
 266                 vc4->clear_stencil = stencil;
 267
 268         vc4->cleared |= buffers;
 269         vc4->resolve |= buffers;
 270
 271         vc4_start_draw(vc4);
 272 }
 273
 274 static void
 275 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 276                         const union pipe_color_union *color,
 277                         unsigned x, unsigned y, unsigned w, unsigned h)
 278 {
 279         fprintf(stderr, "unimpl: clear RT\n");
 280 }
 281
 282 static void
 283 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 284                         unsigned buffers, double depth, unsigned stencil,
 285                         unsigned x, unsigned y, unsigned w, unsigned h)
 286 {
 287         fprintf(stderr, "unimpl: clear DS\n");
 288 }
 289
 290 void
 291 vc4_draw_init(struct pipe_context *pctx)
 292 {
 293         pctx->draw_vbo = vc4_draw_vbo;
 294         pctx->clear = vc4_clear;
 295         pctx->clear_render_target = vc4_clear_render_target;
 296         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 297 }