src/gallium/drivers/vc4/vc4_draw.c

   1 /*
   2  * Copyright (c) 2014 Scott Mansell
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_upload_mgr.h"
  29 #include "indices/u_primconvert.h"
  30
  31 #include "vc4_context.h"
  32 #include "vc4_resource.h"
  33
  34 static void
  35 vc4_get_draw_cl_space(struct vc4_context *vc4)
  36 {
  37         /* Binner gets our packet state -- vc4_emit.c contents,
  38          * and the primitive itself.
  39          */
  40         cl_ensure_space(&vc4->bcl, 256);
  41
  42         /* Nothing for rcl -- that's covered by vc4_context.c */
  43
  44         /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
  45          * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
  46          * vattr stride).
  47          */
  48         cl_ensure_space(&vc4->shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 32);
  49
  50         /* Uniforms are covered by vc4_write_uniforms(). */
  51
  52         /* There could be up to 16 textures per stage, plus misc other
  53          * pointers.
  54          */
  55         cl_ensure_space(&vc4->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
  56         cl_ensure_space(&vc4->bo_pointers,
  57                         (2 * 16 + 20) * sizeof(struct vc4_bo *));
  58 }
  59
  60 /**
  61  * Does the initial bining command list setup for drawing to a given FBO.
  62  */
  63 static void
  64 vc4_start_draw(struct vc4_context *vc4)
  65 {
  66         if (vc4->needs_flush)
  67                 return;
  68
  69         vc4_get_draw_cl_space(vc4);
  70
  71         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
  72         //   Tile state data is 48 bytes per tile, I think it can be thrown away
  73         //   as soon as binning is finished.
  74         cl_u8(&bcl, VC4_PACKET_TILE_BINNING_MODE_CONFIG);
  75         cl_u32(&bcl, 0); /* tile alloc addr, filled by kernel */
  76         cl_u32(&bcl, 0); /* tile alloc size, filled by kernel */
  77         cl_u32(&bcl, 0); /* tile state addr, filled by kernel */
  78         cl_u8(&bcl, vc4->draw_tiles_x);
  79         cl_u8(&bcl, vc4->draw_tiles_y);
  80         /* Other flags are filled by kernel. */
  81         cl_u8(&bcl, vc4->msaa ? VC4_BIN_CONFIG_MS_MODE_4X : 0);
  82
  83         /* START_TILE_BINNING resets the statechange counters in the hardware,
  84          * which are what is used when a primitive is binned to a tile to
  85          * figure out what new state packets need to be written to that tile's
  86          * command list.
  87          */
  88         cl_u8(&bcl, VC4_PACKET_START_TILE_BINNING);
  89
  90         /* Reset the current compressed primitives format.  This gets modified
  91          * by VC4_PACKET_GL_INDEXED_PRIMITIVE and
  92          * VC4_PACKET_GL_ARRAY_PRIMITIVE, so it needs to be reset at the start
  93          * of every tile.
  94          */
  95         cl_u8(&bcl, VC4_PACKET_PRIMITIVE_LIST_FORMAT);
  96         cl_u8(&bcl, (VC4_PRIMITIVE_LIST_FORMAT_16_INDEX |
  97                      VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
  98
  99         vc4->needs_flush = true;
 100         vc4->draw_calls_queued++;
 101         vc4->draw_width = vc4->framebuffer.width;
 102         vc4->draw_height = vc4->framebuffer.height;
 103
 104         cl_end(&vc4->bcl, bcl);
 105 }
 106
 107 static void
 108 vc4_update_shadow_textures(struct pipe_context *pctx,
 109                            struct vc4_texture_stateobj *stage_tex)
 110 {
 111         for (int i = 0; i < stage_tex->num_textures; i++) {
 112                 struct pipe_sampler_view *view = stage_tex->textures[i];
 113                 if (!view)
 114                         continue;
 115                 struct vc4_resource *rsc = vc4_resource(view->texture);
 116                 if (rsc->shadow_parent)
 117                         vc4_update_shadow_baselevel_texture(pctx, view);
 118         }
 119 }
 120
 121 static void
 122 vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info *info)
 123 {
 124         /* VC4_DIRTY_VTXSTATE */
 125         struct vc4_vertex_stateobj *vtx = vc4->vtx;
 126         /* VC4_DIRTY_VTXBUF */
 127         struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
 128
 129         /* The simulator throws a fit if VS or CS don't read an attribute, so
 130          * we emit a dummy read.
 131          */
 132         uint32_t num_elements_emit = MAX2(vtx->num_elements, 1);
 133         /* Emit the shader record. */
 134         struct vc4_cl_out *shader_rec =
 135                 cl_start_shader_reloc(&vc4->shader_rec, 3 + num_elements_emit);
 136         /* VC4_DIRTY_PRIM_MODE | VC4_DIRTY_RASTERIZER */
 137         cl_u16(&shader_rec,
 138                VC4_SHADER_FLAG_ENABLE_CLIPPING |
 139                VC4_SHADER_FLAG_FS_SINGLE_THREAD |
 140                ((info->mode == PIPE_PRIM_POINTS &&
 141                  vc4->rasterizer->base.point_size_per_vertex) ?
 142                 VC4_SHADER_FLAG_VS_POINT_SIZE : 0));
 143
 144         /* VC4_DIRTY_COMPILED_FS */
 145         cl_u8(&shader_rec, 0); /* fs num uniforms (unused) */
 146         cl_u8(&shader_rec, vc4->prog.fs->num_inputs);
 147         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.fs->bo, 0);
 148         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 149
 150         /* VC4_DIRTY_COMPILED_VS */
 151         cl_u16(&shader_rec, 0); /* vs num uniforms */
 152         cl_u8(&shader_rec, vc4->prog.vs->vattrs_live);
 153         cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[8]);
 154         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.vs->bo, 0);
 155         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 156
 157         /* VC4_DIRTY_COMPILED_CS */
 158         cl_u16(&shader_rec, 0); /* cs num uniforms */
 159         cl_u8(&shader_rec, vc4->prog.cs->vattrs_live);
 160         cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[8]);
 161         cl_reloc(vc4, &vc4->shader_rec, &shader_rec, vc4->prog.cs->bo, 0);
 162         cl_u32(&shader_rec, 0); /* UBO offset written by kernel */
 163
 164         uint32_t max_index = 0xffff;
 165         for (int i = 0; i < vtx->num_elements; i++) {
 166                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 167                 struct pipe_vertex_buffer *vb =
 168                         &vertexbuf->vb[elem->vertex_buffer_index];
 169                 struct vc4_resource *rsc = vc4_resource(vb->buffer);
 170                 /* not vc4->dirty tracked: vc4->last_index_bias */
 171                 uint32_t offset = (vb->buffer_offset +
 172                                    elem->src_offset +
 173                                    vb->stride * info->index_bias);
 174                 uint32_t vb_size = rsc->bo->size - offset;
 175                 uint32_t elem_size =
 176                         util_format_get_blocksize(elem->src_format);
 177
 178                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, rsc->bo, offset);
 179                 cl_u8(&shader_rec, elem_size - 1);
 180                 cl_u8(&shader_rec, vb->stride);
 181                 cl_u8(&shader_rec, vc4->prog.vs->vattr_offsets[i]);
 182                 cl_u8(&shader_rec, vc4->prog.cs->vattr_offsets[i]);
 183
 184                 if (vb->stride > 0) {
 185                         max_index = MIN2(max_index,
 186                                          (vb_size - elem_size) / vb->stride);
 187                 }
 188         }
 189
 190         if (vtx->num_elements == 0) {
 191                 assert(num_elements_emit == 1);
 192                 struct vc4_bo *bo = vc4_bo_alloc(vc4->screen, 4096, "scratch VBO");
 193                 cl_reloc(vc4, &vc4->shader_rec, &shader_rec, bo, 0);
 194                 cl_u8(&shader_rec, 16 - 1); /* element size */
 195                 cl_u8(&shader_rec, 0); /* stride */
 196                 cl_u8(&shader_rec, 0); /* VS VPM offset */
 197                 cl_u8(&shader_rec, 0); /* CS VPM offset */
 198                 vc4_bo_unreference(&bo);
 199         }
 200         cl_end(&vc4->shader_rec, shader_rec);
 201
 202         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
 203         /* the actual draw call. */
 204         cl_u8(&bcl, VC4_PACKET_GL_SHADER_STATE);
 205         assert(vtx->num_elements <= 8);
 206         /* Note that number of attributes == 0 in the packet means 8
 207          * attributes.  This field also contains the offset into shader_rec.
 208          */
 209         cl_u32(&bcl, num_elements_emit & 0x7);
 210         cl_end(&vc4->bcl, bcl);
 211
 212         vc4_write_uniforms(vc4, vc4->prog.fs,
 213                            &vc4->constbuf[PIPE_SHADER_FRAGMENT],
 214                            &vc4->fragtex);
 215         vc4_write_uniforms(vc4, vc4->prog.vs,
 216                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 217                            &vc4->verttex);
 218         vc4_write_uniforms(vc4, vc4->prog.cs,
 219                            &vc4->constbuf[PIPE_SHADER_VERTEX],
 220                            &vc4->verttex);
 221
 222         vc4->last_index_bias = info->index_bias;
 223         vc4->max_index = max_index;
 224 }
 225
 226 /**
 227  * HW-2116 workaround: Flush the batch before triggering the hardware state
 228  * counter wraparound behavior.
 229  *
 230  * State updates are tracked by a global counter which increments at the first
 231  * state update after a draw or a START_BINNING.  Tiles can then have their
 232  * state updated at draw time with a set of cheap checks for whether the
 233  * state's copy of the global counter matches the global counter the last time
 234  * that state was written to the tile.
 235  *
 236  * The state counters are relatively small and wrap around quickly, so you
 237  * could get false negatives for needing to update a particular state in the
 238  * tile.  To avoid this, the hardware attempts to write all of the state in
 239  * the tile at wraparound time.  This apparently is broken, so we just flush
 240  * everything before that behavior is triggered.  A batch flush is sufficient
 241  * to get our current contents drawn and reset the counters to 0.
 242  *
 243  * Note that we can't just use VC4_PACKET_FLUSH_ALL, because that caps the
 244  * tiles with VC4_PACKET_RETURN_FROM_LIST.
 245  */
 246 static void
 247 vc4_hw_2116_workaround(struct pipe_context *pctx)
 248 {
 249         struct vc4_context *vc4 = vc4_context(pctx);
 250
 251         if (vc4->draw_calls_queued == 0x1ef0) {
 252                 perf_debug("Flushing batch due to HW-2116 workaround "
 253                            "(too many draw calls per scene\n");
 254                 vc4_flush(pctx);
 255         }
 256 }
 257
 258 static void
 259 vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 260 {
 261         struct vc4_context *vc4 = vc4_context(pctx);
 262
 263         if (info->mode >= PIPE_PRIM_QUADS) {
 264                 util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
 265                 util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
 266                 util_primconvert_draw_vbo(vc4->primconvert, info);
 267                 perf_debug("Fallback conversion for %d %s vertices\n",
 268                            info->count, u_prim_name(info->mode));
 269                 return;
 270         }
 271
 272         /* Before setting up the draw, do any fixup blits necessary. */
 273         vc4_update_shadow_textures(pctx, &vc4->verttex);
 274         vc4_update_shadow_textures(pctx, &vc4->fragtex);
 275
 276         vc4_hw_2116_workaround(pctx);
 277
 278         vc4_get_draw_cl_space(vc4);
 279
 280         if (vc4->prim_mode != info->mode) {
 281                 vc4->prim_mode = info->mode;
 282                 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 283         }
 284
 285         vc4_start_draw(vc4);
 286         vc4_update_compiled_shaders(vc4, info->mode);
 287
 288         vc4_emit_state(pctx);
 289
 290         if ((vc4->dirty & (VC4_DIRTY_VTXBUF |
 291                            VC4_DIRTY_VTXSTATE |
 292                            VC4_DIRTY_PRIM_MODE |
 293                            VC4_DIRTY_RASTERIZER |
 294                            VC4_DIRTY_COMPILED_CS |
 295                            VC4_DIRTY_COMPILED_VS |
 296                            VC4_DIRTY_COMPILED_FS |
 297                            vc4->prog.cs->uniform_dirty_bits |
 298                            vc4->prog.vs->uniform_dirty_bits |
 299                            vc4->prog.fs->uniform_dirty_bits)) ||
 300             vc4->last_index_bias != info->index_bias) {
 301                 vc4_emit_gl_shader_state(vc4, info);
 302         }
 303
 304         vc4->dirty = 0;
 305
 306         /* Note that the primitive type fields match with OpenGL/gallium
 307          * definitions, up to but not including QUADS.
 308          */
 309         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
 310         if (info->indexed) {
 311                 uint32_t offset = vc4->indexbuf.offset;
 312                 uint32_t index_size = vc4->indexbuf.index_size;
 313                 struct pipe_resource *prsc;
 314                 if (vc4->indexbuf.index_size == 4) {
 315                         prsc = vc4_get_shadow_index_buffer(pctx, &vc4->indexbuf,
 316                                                            info->count, &offset);
 317                         index_size = 2;
 318                 } else {
 319                         if (vc4->indexbuf.user_buffer) {
 320                                 prsc = NULL;
 321                                 u_upload_data(vc4->uploader, 0,
 322                                               info->count * index_size, 4,
 323                                               vc4->indexbuf.user_buffer,
 324                                               &offset, &prsc);
 325                         } else {
 326                                 prsc = vc4->indexbuf.buffer;
 327                         }
 328                 }
 329                 struct vc4_resource *rsc = vc4_resource(prsc);
 330
 331                 cl_start_reloc(&vc4->bcl, &bcl, 1);
 332                 cl_u8(&bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
 333                 cl_u8(&bcl,
 334                       info->mode |
 335                       (index_size == 2 ?
 336                        VC4_INDEX_BUFFER_U16:
 337                        VC4_INDEX_BUFFER_U8));
 338                 cl_u32(&bcl, info->count);
 339                 cl_reloc(vc4, &vc4->bcl, &bcl, rsc->bo, offset);
 340                 cl_u32(&bcl, vc4->max_index);
 341
 342                 if (vc4->indexbuf.index_size == 4 || vc4->indexbuf.user_buffer)
 343                         pipe_resource_reference(&prsc, NULL);
 344         } else {
 345                 cl_u8(&bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
 346                 cl_u8(&bcl, info->mode);
 347                 cl_u32(&bcl, info->count);
 348                 cl_u32(&bcl, info->start);
 349         }
 350         cl_end(&vc4->bcl, bcl);
 351
 352         if (vc4->zsa && vc4->zsa->base.depth.enabled) {
 353                 vc4->resolve |= PIPE_CLEAR_DEPTH;
 354         }
 355         if (vc4->zsa && vc4->zsa->base.stencil[0].enabled)
 356                 vc4->resolve |= PIPE_CLEAR_STENCIL;
 357         vc4->resolve |= PIPE_CLEAR_COLOR0;
 358
 359         vc4->shader_rec_count++;
 360
 361         if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
 362                 vc4_flush(pctx);
 363 }
 364
 365 static uint32_t
 366 pack_rgba(enum pipe_format format, const float *rgba)
 367 {
 368         union util_color uc;
 369         util_pack_color(rgba, format, &uc);
 370         if (util_format_get_blocksize(format) == 2)
 371                 return uc.us;
 372         else
 373                 return uc.ui[0];
 374 }
 375
 376 static void
 377 vc4_clear(struct pipe_context *pctx, unsigned buffers,
 378           const union pipe_color_union *color, double depth, unsigned stencil)
 379 {
 380         struct vc4_context *vc4 = vc4_context(pctx);
 381
 382         /* We can't flag new buffers for clearing once we've queued draws.  We
 383          * could avoid this by using the 3d engine to clear.
 384          */
 385         if (vc4->draw_calls_queued) {
 386                 perf_debug("Flushing rendering to process new clear.\n");
 387                 vc4_flush(pctx);
 388         }
 389
 390         if (buffers & PIPE_CLEAR_COLOR0) {
 391                 vc4->clear_color[0] = vc4->clear_color[1] =
 392                         pack_rgba(vc4->framebuffer.cbufs[0]->format,
 393                                   color->f);
 394         }
 395
 396         if (buffers & PIPE_CLEAR_DEPTH) {
 397                 /* Though the depth buffer is stored with Z in the high 24,
 398                  * for this field we just need to store it in the low 24.
 399                  */
 400                 vc4->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
 401         }
 402
 403         if (buffers & PIPE_CLEAR_STENCIL)
 404                 vc4->clear_stencil = stencil;
 405
 406         vc4->draw_min_x = 0;
 407         vc4->draw_min_y = 0;
 408         vc4->draw_max_x = vc4->framebuffer.width;
 409         vc4->draw_max_y = vc4->framebuffer.height;
 410         vc4->cleared |= buffers;
 411         vc4->resolve |= buffers;
 412
 413         vc4_start_draw(vc4);
 414 }
 415
 416 static void
 417 vc4_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 418                         const union pipe_color_union *color,
 419                         unsigned x, unsigned y, unsigned w, unsigned h)
 420 {
 421         fprintf(stderr, "unimpl: clear RT\n");
 422 }
 423
 424 static void
 425 vc4_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 426                         unsigned buffers, double depth, unsigned stencil,
 427                         unsigned x, unsigned y, unsigned w, unsigned h)
 428 {
 429         fprintf(stderr, "unimpl: clear DS\n");
 430 }
 431
 432 void
 433 vc4_draw_init(struct pipe_context *pctx)
 434 {
 435         pctx->draw_vbo = vc4_draw_vbo;
 436         pctx->clear = vc4_clear;
 437         pctx->clear_render_target = vc4_clear_render_target;
 438         pctx->clear_depth_stencil = vc4_clear_depth_stencil;
 439 }