src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c

   1 /*
   2  * Copyright © 2015 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "vc4_qir.h"
  25 #include "kernel/vc4_packet.h"
  26 #include "tgsi/tgsi_info.h"
  27 #include "compiler/nir/nir_builder.h"
  28
  29 /** @file vc4_nir_lower_txf_ms.c
  30  * Walks the NIR generated by TGSI-to-NIR to lower its nir_texop_txf_ms
  31  * coordinates to do the math necessary and use a plain nir_texop_txf instead.
  32  *
  33  * MSAA textures are laid out as 32x32-aligned blocks of RGBA8888 or Z24S8.
  34  * We can't load them through the normal sampler path because of the lack of
  35  * linear support in the hardware.  So, we treat MSAA textures as a giant UBO
  36  * and do the math in the shader.
  37  */
  38
  39 static void
  40 vc4_nir_lower_txf_ms_instr(struct vc4_compile *c, nir_builder *b,
  41                            nir_tex_instr *txf_ms)
  42 {
  43         if (txf_ms->op != nir_texop_txf_ms)
  44                 return;
  45
  46         b->cursor = nir_before_instr(&txf_ms->instr);
  47
  48         nir_tex_instr *txf = nir_tex_instr_create(c->s, 1);
  49         txf->op = nir_texop_txf;
  50         txf->texture = txf_ms->texture;
  51         txf->texture_index = txf_ms->texture_index;
  52         txf->coord_components = txf_ms->coord_components;
  53         txf->is_shadow = txf_ms->is_shadow;
  54         txf->is_new_style_shadow = txf_ms->is_new_style_shadow;
  55
  56         nir_ssa_def *coord = NULL, *sample_index = NULL;
  57         for (int i = 0; i < txf_ms->num_srcs; i++) {
  58                 assert(txf_ms->src[i].src.is_ssa);
  59
  60                 switch (txf_ms->src[i].src_type) {
  61                 case nir_tex_src_coord:
  62                         coord = txf_ms->src[i].src.ssa;
  63                         break;
  64                 case nir_tex_src_ms_index:
  65                         sample_index = txf_ms->src[i].src.ssa;
  66                         break;
  67                 default:
  68                         unreachable("Unknown txf_ms src\n");
  69                 }
  70         }
  71         assert(coord);
  72         assert(sample_index);
  73
  74         nir_ssa_def *x = nir_channel(b, coord, 0);
  75         nir_ssa_def *y = nir_channel(b, coord, 1);
  76
  77         uint32_t tile_w = 32;
  78         uint32_t tile_h = 32;
  79         uint32_t tile_w_shift = 5;
  80         uint32_t tile_h_shift = 5;
  81         uint32_t tile_size = (tile_h * tile_w *
  82                               VC4_MAX_SAMPLES * sizeof(uint32_t));
  83         unsigned unit = txf_ms->texture_index;
  84         uint32_t w = align(c->key->tex[unit].msaa_width, tile_w);
  85         uint32_t w_tiles = w / tile_w;
  86
  87         nir_ssa_def *x_tile = nir_ushr(b, x, nir_imm_int(b, tile_w_shift));
  88         nir_ssa_def *y_tile = nir_ushr(b, y, nir_imm_int(b, tile_h_shift));
  89         nir_ssa_def *tile_addr = nir_iadd(b,
  90                                           nir_imul(b, x_tile,
  91                                                    nir_imm_int(b, tile_size)),
  92                                           nir_imul(b, y_tile,
  93                                                    nir_imm_int(b, (w_tiles *
  94                                                                    tile_size))));
  95         nir_ssa_def *x_subspan = nir_iand(b, x,
  96                                           nir_imm_int(b, (tile_w - 1) & ~1));
  97         nir_ssa_def *y_subspan = nir_iand(b, y,
  98                                           nir_imm_int(b, (tile_h - 1) & ~1));
  99         nir_ssa_def *subspan_addr = nir_iadd(b,
 100                                              nir_imul(b, x_subspan,
 101                                                       nir_imm_int(b, 2 * VC4_MAX_SAMPLES * sizeof(uint32_t))),
 102                                              nir_imul(b, y_subspan,
 103                                                       nir_imm_int(b,
 104                                                                   tile_w *
 105                                                                   VC4_MAX_SAMPLES *
 106                                                                   sizeof(uint32_t))));
 107
 108         nir_ssa_def *pixel_addr = nir_ior(b,
 109                                           nir_iand(b,
 110                                                    nir_ishl(b, x,
 111                                                             nir_imm_int(b, 2)),
 112                                                    nir_imm_int(b, (1 << 2))),
 113                                           nir_iand(b,
 114                                                    nir_ishl(b, y,
 115                                                             nir_imm_int(b, 3)),
 116                                                    nir_imm_int(b, (1 << 3))));
 117
 118         nir_ssa_def *sample_addr = nir_ishl(b, sample_index, nir_imm_int(b, 4));
 119
 120         nir_ssa_def *addr = nir_iadd(b,
 121                                      nir_ior(b, sample_addr, pixel_addr),
 122                                      nir_iadd(b, subspan_addr, tile_addr));
 123
 124         txf->src[0].src_type = nir_tex_src_coord;
 125         txf->src[0].src = nir_src_for_ssa(nir_vec2(b, addr, nir_imm_int(b, 0)));
 126         nir_ssa_dest_init(&txf->instr, &txf->dest, 4, 32, NULL);
 127         nir_builder_instr_insert(b, &txf->instr);
 128         nir_ssa_def_rewrite_uses(&txf_ms->dest.ssa,
 129                                  nir_src_for_ssa(&txf->dest.ssa));
 130         nir_instr_remove(&txf_ms->instr);
 131 }
 132
 133 static bool
 134 vc4_nir_lower_txf_ms_block(nir_block *block, void *arg)
 135 {
 136         struct vc4_compile *c = arg;
 137         nir_function_impl *impl =
 138                 nir_cf_node_get_function(&block->cf_node);
 139
 140         nir_builder b;
 141         nir_builder_init(&b, impl);
 142
 143         nir_foreach_instr_safe(block, instr) {
 144                 if (instr->type == nir_instr_type_tex) {
 145                         vc4_nir_lower_txf_ms_instr(c, &b,
 146                                                    nir_instr_as_tex(instr));
 147                 }
 148         }
 149
 150         return true;
 151 }
 152
 153 static bool
 154 vc4_nir_lower_txf_ms_impl(struct vc4_compile *c, nir_function_impl *impl)
 155 {
 156         nir_foreach_block(impl, vc4_nir_lower_txf_ms_block, c);
 157
 158         nir_metadata_preserve(impl,
 159                               nir_metadata_block_index |
 160                               nir_metadata_dominance);
 161
 162         return true;
 163 }
 164
 165 void
 166 vc4_nir_lower_txf_ms(struct vc4_compile *c)
 167 {
 168         nir_foreach_function(c->s, function) {
 169                 if (function->impl)
 170                         vc4_nir_lower_txf_ms_impl(c, function->impl);
 171         }
 172 }