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[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash_table.h"
29 #include "util/u_hash.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/format_srgb.h"
33 #include "util/ralloc.h"
34 #include "util/hash_table.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "tgsi/tgsi_info.h"
37 #include "tgsi/tgsi_lowering.h"
38
39 #include "vc4_context.h"
40 #include "vc4_qpu.h"
41 #include "vc4_qir.h"
42 #ifdef USE_VC4_SIMULATOR
43 #include "simpenrose/simpenrose.h"
44 #endif
45
46 struct vc4_key {
47 struct vc4_uncompiled_shader *shader_state;
48 struct {
49 enum pipe_format format;
50 unsigned compare_mode:1;
51 unsigned compare_func:3;
52 unsigned wrap_s:3;
53 unsigned wrap_t:3;
54 uint8_t swizzle[4];
55 } tex[VC4_MAX_TEXTURE_SAMPLERS];
56 uint8_t ucp_enables;
57 };
58
59 struct vc4_fs_key {
60 struct vc4_key base;
61 enum pipe_format color_format;
62 bool depth_enabled;
63 bool stencil_enabled;
64 bool stencil_twoside;
65 bool stencil_full_writemasks;
66 bool is_points;
67 bool is_lines;
68 bool alpha_test;
69 bool point_coord_upper_left;
70 bool light_twoside;
71 uint8_t alpha_test_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 add_uniform(struct vc4_compile *c,
114 enum quniform_contents contents,
115 uint32_t data)
116 {
117 uint32_t uniform = c->num_uniforms++;
118 struct qreg u = { QFILE_UNIF, uniform };
119
120 if (uniform >= c->uniform_array_size) {
121 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),
122 c->uniform_array_size * 2);
123
124 c->uniform_data = reralloc(c, c->uniform_data,
125 uint32_t,
126 c->uniform_array_size);
127 c->uniform_contents = reralloc(c, c->uniform_contents,
128 enum quniform_contents,
129 c->uniform_array_size);
130 }
131
132 c->uniform_contents[uniform] = contents;
133 c->uniform_data[uniform] = data;
134
135 return u;
136 }
137
138 static struct qreg
139 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,
140 uint32_t data)
141 {
142 struct qreg u = add_uniform(c, contents, data);
143 struct qreg t = qir_MOV(c, u);
144 return t;
145 }
146
147 static struct qreg
148 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
149 {
150 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);
151 }
152
153 static struct qreg
154 qir_uniform_f(struct vc4_compile *c, float f)
155 {
156 return qir_uniform_ui(c, fui(f));
157 }
158
159 static struct qreg
160 get_src(struct vc4_compile *c, unsigned tgsi_op,
161 struct tgsi_src_register *src, int i)
162 {
163 struct qreg r = c->undef;
164
165 uint32_t s = i;
166 switch (i) {
167 case TGSI_SWIZZLE_X:
168 s = src->SwizzleX;
169 break;
170 case TGSI_SWIZZLE_Y:
171 s = src->SwizzleY;
172 break;
173 case TGSI_SWIZZLE_Z:
174 s = src->SwizzleZ;
175 break;
176 case TGSI_SWIZZLE_W:
177 s = src->SwizzleW;
178 break;
179 default:
180 abort();
181 }
182
183 assert(!src->Indirect);
184
185 switch (src->File) {
186 case TGSI_FILE_NULL:
187 return r;
188 case TGSI_FILE_TEMPORARY:
189 r = c->temps[src->Index * 4 + s];
190 break;
191 case TGSI_FILE_IMMEDIATE:
192 r = c->consts[src->Index * 4 + s];
193 break;
194 case TGSI_FILE_CONSTANT:
195 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,
196 src->Index * 4 + s);
197 break;
198 case TGSI_FILE_INPUT:
199 r = c->inputs[src->Index * 4 + s];
200 break;
201 case TGSI_FILE_SAMPLER:
202 case TGSI_FILE_SAMPLER_VIEW:
203 r = c->undef;
204 break;
205 default:
206 fprintf(stderr, "unknown src file %d\n", src->File);
207 abort();
208 }
209
210 if (src->Absolute)
211 r = qir_FMAXABS(c, r, r);
212
213 if (src->Negate) {
214 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
215 case TGSI_TYPE_SIGNED:
216 case TGSI_TYPE_UNSIGNED:
217 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
218 break;
219 default:
220 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
221 break;
222 }
223 }
224
225 return r;
226 };
227
228
229 static void
230 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
231 int i, struct qreg val)
232 {
233 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
234
235 assert(!tgsi_dst->Indirect);
236
237 switch (tgsi_dst->File) {
238 case TGSI_FILE_TEMPORARY:
239 c->temps[tgsi_dst->Index * 4 + i] = val;
240 break;
241 case TGSI_FILE_OUTPUT:
242 c->outputs[tgsi_dst->Index * 4 + i] = val;
243 c->num_outputs = MAX2(c->num_outputs,
244 tgsi_dst->Index * 4 + i + 1);
245 break;
246 default:
247 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
248 abort();
249 }
250 };
251
252 static struct qreg
253 get_swizzled_channel(struct vc4_compile *c,
254 struct qreg *srcs, int swiz)
255 {
256 switch (swiz) {
257 default:
258 case UTIL_FORMAT_SWIZZLE_NONE:
259 fprintf(stderr, "warning: unknown swizzle\n");
260 /* FALLTHROUGH */
261 case UTIL_FORMAT_SWIZZLE_0:
262 return qir_uniform_f(c, 0.0);
263 case UTIL_FORMAT_SWIZZLE_1:
264 return qir_uniform_f(c, 1.0);
265 case UTIL_FORMAT_SWIZZLE_X:
266 case UTIL_FORMAT_SWIZZLE_Y:
267 case UTIL_FORMAT_SWIZZLE_Z:
268 case UTIL_FORMAT_SWIZZLE_W:
269 return srcs[swiz];
270 }
271 }
272
273 static struct qreg
274 tgsi_to_qir_alu(struct vc4_compile *c,
275 struct tgsi_full_instruction *tgsi_inst,
276 enum qop op, struct qreg *src, int i)
277 {
278 struct qreg dst = qir_get_temp(c);
279 qir_emit(c, qir_inst4(op, dst,
280 src[0 * 4 + i],
281 src[1 * 4 + i],
282 src[2 * 4 + i],
283 c->undef));
284 return dst;
285 }
286
287 static struct qreg
288 tgsi_to_qir_scalar(struct vc4_compile *c,
289 struct tgsi_full_instruction *tgsi_inst,
290 enum qop op, struct qreg *src, int i)
291 {
292 struct qreg dst = qir_get_temp(c);
293 qir_emit(c, qir_inst(op, dst,
294 src[0 * 4 + 0],
295 c->undef));
296 return dst;
297 }
298
299 static struct qreg
300 tgsi_to_qir_rcp(struct vc4_compile *c,
301 struct tgsi_full_instruction *tgsi_inst,
302 enum qop op, struct qreg *src, int i)
303 {
304 struct qreg x = src[0 * 4 + 0];
305 struct qreg r = qir_RCP(c, x);
306
307 /* Apply a Newton-Raphson step to improve the accuracy. */
308 r = qir_FMUL(c, r, qir_FSUB(c,
309 qir_uniform_f(c, 2.0),
310 qir_FMUL(c, x, r)));
311
312 return r;
313 }
314
315 static struct qreg
316 tgsi_to_qir_rsq(struct vc4_compile *c,
317 struct tgsi_full_instruction *tgsi_inst,
318 enum qop op, struct qreg *src, int i)
319 {
320 struct qreg x = src[0 * 4 + 0];
321 struct qreg r = qir_RSQ(c, x);
322
323 /* Apply a Newton-Raphson step to improve the accuracy. */
324 r = qir_FMUL(c, r, qir_FSUB(c,
325 qir_uniform_f(c, 1.5),
326 qir_FMUL(c,
327 qir_uniform_f(c, 0.5),
328 qir_FMUL(c, x,
329 qir_FMUL(c, r, r)))));
330
331 return r;
332 }
333
334 static struct qreg
335 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
336 {
337 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
338 struct qreg high = qir_POW(c,
339 qir_FMUL(c,
340 qir_FADD(c,
341 srgb,
342 qir_uniform_f(c, 0.055)),
343 qir_uniform_f(c, 1.0 / 1.055)),
344 qir_uniform_f(c, 2.4));
345
346 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
347 return qir_SEL_X_Y_NS(c, low, high);
348 }
349
350 static struct qreg
351 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
352 {
353 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
354 struct qreg high = qir_FSUB(c,
355 qir_FMUL(c,
356 qir_uniform_f(c, 1.055),
357 qir_POW(c,
358 linear,
359 qir_uniform_f(c, 0.41666))),
360 qir_uniform_f(c, 0.055));
361
362 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
363 return qir_SEL_X_Y_NS(c, low, high);
364 }
365
366 static struct qreg
367 tgsi_to_qir_umul(struct vc4_compile *c,
368 struct tgsi_full_instruction *tgsi_inst,
369 enum qop op, struct qreg *src, int i)
370 {
371 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],
372 qir_uniform_ui(c, 16));
373 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],
374 qir_uniform_ui(c, 0xffff));
375 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],
376 qir_uniform_ui(c, 16));
377 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],
378 qir_uniform_ui(c, 0xffff));
379
380 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);
381 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);
382 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);
383
384 return qir_ADD(c, lolo, qir_SHL(c,
385 qir_ADD(c, hilo, lohi),
386 qir_uniform_ui(c, 16)));
387 }
388
389 static struct qreg
390 tgsi_to_qir_idiv(struct vc4_compile *c,
391 struct tgsi_full_instruction *tgsi_inst,
392 enum qop op, struct qreg *src, int i)
393 {
394 return qir_FTOI(c, qir_FMUL(c,
395 qir_ITOF(c, src[0 * 4 + i]),
396 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
397 }
398
399 static struct qreg
400 tgsi_to_qir_ineg(struct vc4_compile *c,
401 struct tgsi_full_instruction *tgsi_inst,
402 enum qop op, struct qreg *src, int i)
403 {
404 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
405 }
406
407 static struct qreg
408 tgsi_to_qir_seq(struct vc4_compile *c,
409 struct tgsi_full_instruction *tgsi_inst,
410 enum qop op, struct qreg *src, int i)
411 {
412 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
413 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
414 }
415
416 static struct qreg
417 tgsi_to_qir_sne(struct vc4_compile *c,
418 struct tgsi_full_instruction *tgsi_inst,
419 enum qop op, struct qreg *src, int i)
420 {
421 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
422 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
423 }
424
425 static struct qreg
426 tgsi_to_qir_slt(struct vc4_compile *c,
427 struct tgsi_full_instruction *tgsi_inst,
428 enum qop op, struct qreg *src, int i)
429 {
430 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
431 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
432 }
433
434 static struct qreg
435 tgsi_to_qir_sge(struct vc4_compile *c,
436 struct tgsi_full_instruction *tgsi_inst,
437 enum qop op, struct qreg *src, int i)
438 {
439 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
440 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
441 }
442
443 static struct qreg
444 tgsi_to_qir_fseq(struct vc4_compile *c,
445 struct tgsi_full_instruction *tgsi_inst,
446 enum qop op, struct qreg *src, int i)
447 {
448 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
449 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
450 }
451
452 static struct qreg
453 tgsi_to_qir_fsne(struct vc4_compile *c,
454 struct tgsi_full_instruction *tgsi_inst,
455 enum qop op, struct qreg *src, int i)
456 {
457 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
458 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
459 }
460
461 static struct qreg
462 tgsi_to_qir_fslt(struct vc4_compile *c,
463 struct tgsi_full_instruction *tgsi_inst,
464 enum qop op, struct qreg *src, int i)
465 {
466 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
467 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
468 }
469
470 static struct qreg
471 tgsi_to_qir_fsge(struct vc4_compile *c,
472 struct tgsi_full_instruction *tgsi_inst,
473 enum qop op, struct qreg *src, int i)
474 {
475 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
476 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
477 }
478
479 static struct qreg
480 tgsi_to_qir_useq(struct vc4_compile *c,
481 struct tgsi_full_instruction *tgsi_inst,
482 enum qop op, struct qreg *src, int i)
483 {
484 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
485 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
486 }
487
488 static struct qreg
489 tgsi_to_qir_usne(struct vc4_compile *c,
490 struct tgsi_full_instruction *tgsi_inst,
491 enum qop op, struct qreg *src, int i)
492 {
493 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
494 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
495 }
496
497 static struct qreg
498 tgsi_to_qir_islt(struct vc4_compile *c,
499 struct tgsi_full_instruction *tgsi_inst,
500 enum qop op, struct qreg *src, int i)
501 {
502 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
503 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
504 }
505
506 static struct qreg
507 tgsi_to_qir_isge(struct vc4_compile *c,
508 struct tgsi_full_instruction *tgsi_inst,
509 enum qop op, struct qreg *src, int i)
510 {
511 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
512 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
513 }
514
515 static struct qreg
516 tgsi_to_qir_cmp(struct vc4_compile *c,
517 struct tgsi_full_instruction *tgsi_inst,
518 enum qop op, struct qreg *src, int i)
519 {
520 qir_SF(c, src[0 * 4 + i]);
521 return qir_SEL_X_Y_NS(c,
522 src[1 * 4 + i],
523 src[2 * 4 + i]);
524 }
525
526 static struct qreg
527 tgsi_to_qir_mad(struct vc4_compile *c,
528 struct tgsi_full_instruction *tgsi_inst,
529 enum qop op, struct qreg *src, int i)
530 {
531 return qir_FADD(c,
532 qir_FMUL(c,
533 src[0 * 4 + i],
534 src[1 * 4 + i]),
535 src[2 * 4 + i]);
536 }
537
538 static struct qreg
539 tgsi_to_qir_lrp(struct vc4_compile *c,
540 struct tgsi_full_instruction *tgsi_inst,
541 enum qop op, struct qreg *src, int i)
542 {
543 struct qreg src0 = src[0 * 4 + i];
544 struct qreg src1 = src[1 * 4 + i];
545 struct qreg src2 = src[2 * 4 + i];
546
547 /* LRP is:
548 * src0 * src1 + (1 - src0) * src2.
549 * -> src0 * src1 + src2 - src0 * src2
550 * -> src2 + src0 * (src1 - src2)
551 */
552 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
553
554 }
555
556 static void
557 tgsi_to_qir_tex(struct vc4_compile *c,
558 struct tgsi_full_instruction *tgsi_inst,
559 enum qop op, struct qreg *src)
560 {
561 assert(!tgsi_inst->Instruction.Saturate);
562
563 struct qreg s = src[0 * 4 + 0];
564 struct qreg t = src[0 * 4 + 1];
565 struct qreg r = src[0 * 4 + 2];
566 uint32_t unit = tgsi_inst->Src[1].Register.Index;
567 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
568
569 struct qreg proj = c->undef;
570 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
571 proj = qir_RCP(c, src[0 * 4 + 3]);
572 s = qir_FMUL(c, s, proj);
573 t = qir_FMUL(c, t, proj);
574 }
575
576 struct qreg texture_u[] = {
577 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
578 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
579 add_uniform(c, QUNIFORM_CONSTANT, 0),
580 add_uniform(c, QUNIFORM_CONSTANT, 0),
581 };
582 uint32_t next_texture_u = 0;
583
584 /* There is no native support for GL texture rectangle coordinates, so
585 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
586 * 1]).
587 */
588 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
589 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
590 s = qir_FMUL(c, s,
591 get_temp_for_uniform(c,
592 QUNIFORM_TEXRECT_SCALE_X,
593 unit));
594 t = qir_FMUL(c, t,
595 get_temp_for_uniform(c,
596 QUNIFORM_TEXRECT_SCALE_Y,
597 unit));
598 }
599
600 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
601 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
602 is_txl) {
603 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
604 unit | (is_txl << 16));
605 }
606
607 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
608 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
609 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
610 struct qreg rcp_ma = qir_RCP(c, ma);
611 s = qir_FMUL(c, s, rcp_ma);
612 t = qir_FMUL(c, t, rcp_ma);
613 r = qir_FMUL(c, r, rcp_ma);
614
615 qir_TEX_R(c, r, texture_u[next_texture_u++]);
616 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
617 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
618 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
619 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
620 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
621 texture_u[next_texture_u++]);
622 }
623
624 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
625 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),
626 qir_uniform_f(c, 1.0));
627 }
628
629 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
630 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),
631 qir_uniform_f(c, 1.0));
632 }
633
634 qir_TEX_T(c, t, texture_u[next_texture_u++]);
635
636 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
637 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
638 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
639
640 qir_TEX_S(c, s, texture_u[next_texture_u++]);
641
642 c->num_texture_samples++;
643 struct qreg r4 = qir_TEX_RESULT(c);
644
645 enum pipe_format format = c->key->tex[unit].format;
646
647 struct qreg unpacked[4];
648 if (util_format_is_depth_or_stencil(format)) {
649 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
650 qir_uniform_ui(c, 8)));
651 struct qreg normalized = qir_FMUL(c, depthf,
652 qir_uniform_f(c, 1.0f/0xffffff));
653
654 struct qreg depth_output;
655
656 struct qreg one = qir_uniform_f(c, 1.0f);
657 if (c->key->tex[unit].compare_mode) {
658 struct qreg compare = src[0 * 4 + 2];
659
660 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
661 compare = qir_FMUL(c, compare, proj);
662
663 switch (c->key->tex[unit].compare_func) {
664 case PIPE_FUNC_NEVER:
665 depth_output = qir_uniform_f(c, 0.0f);
666 break;
667 case PIPE_FUNC_ALWAYS:
668 depth_output = one;
669 break;
670 case PIPE_FUNC_EQUAL:
671 qir_SF(c, qir_FSUB(c, compare, normalized));
672 depth_output = qir_SEL_X_0_ZS(c, one);
673 break;
674 case PIPE_FUNC_NOTEQUAL:
675 qir_SF(c, qir_FSUB(c, compare, normalized));
676 depth_output = qir_SEL_X_0_ZC(c, one);
677 break;
678 case PIPE_FUNC_GREATER:
679 qir_SF(c, qir_FSUB(c, compare, normalized));
680 depth_output = qir_SEL_X_0_NC(c, one);
681 break;
682 case PIPE_FUNC_GEQUAL:
683 qir_SF(c, qir_FSUB(c, normalized, compare));
684 depth_output = qir_SEL_X_0_NS(c, one);
685 break;
686 case PIPE_FUNC_LESS:
687 qir_SF(c, qir_FSUB(c, compare, normalized));
688 depth_output = qir_SEL_X_0_NS(c, one);
689 break;
690 case PIPE_FUNC_LEQUAL:
691 qir_SF(c, qir_FSUB(c, normalized, compare));
692 depth_output = qir_SEL_X_0_NC(c, one);
693 break;
694 }
695 } else {
696 depth_output = normalized;
697 }
698
699 for (int i = 0; i < 4; i++)
700 unpacked[i] = depth_output;
701 } else {
702 for (int i = 0; i < 4; i++)
703 unpacked[i] = qir_R4_UNPACK(c, r4, i);
704 }
705
706 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
707 struct qreg texture_output[4];
708 for (int i = 0; i < 4; i++) {
709 texture_output[i] = get_swizzled_channel(c, unpacked,
710 format_swiz[i]);
711 }
712
713 if (util_format_is_srgb(format)) {
714 for (int i = 0; i < 3; i++)
715 texture_output[i] = qir_srgb_decode(c,
716 texture_output[i]);
717 }
718
719 for (int i = 0; i < 4; i++) {
720 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
721 continue;
722
723 update_dst(c, tgsi_inst, i,
724 get_swizzled_channel(c, texture_output,
725 c->key->tex[unit].swizzle[i]));
726 }
727 }
728
729 static struct qreg
730 tgsi_to_qir_trunc(struct vc4_compile *c,
731 struct tgsi_full_instruction *tgsi_inst,
732 enum qop op, struct qreg *src, int i)
733 {
734 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
735 }
736
737 /**
738 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
739 * to zero).
740 */
741 static struct qreg
742 tgsi_to_qir_frc(struct vc4_compile *c,
743 struct tgsi_full_instruction *tgsi_inst,
744 enum qop op, struct qreg *src, int i)
745 {
746 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
747 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
748 qir_SF(c, diff);
749 return qir_SEL_X_Y_NS(c,
750 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
751 diff);
752 }
753
754 /**
755 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
756 * zero).
757 */
758 static struct qreg
759 tgsi_to_qir_flr(struct vc4_compile *c,
760 struct tgsi_full_instruction *tgsi_inst,
761 enum qop op, struct qreg *src, int i)
762 {
763 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
764
765 /* This will be < 0 if we truncated and the truncation was of a value
766 * that was < 0 in the first place.
767 */
768 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
769
770 return qir_SEL_X_Y_NS(c,
771 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
772 trunc);
773 }
774
775 /**
776 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
777 * zero).
778 */
779 static struct qreg
780 tgsi_to_qir_ceil(struct vc4_compile *c,
781 struct tgsi_full_instruction *tgsi_inst,
782 enum qop op, struct qreg *src, int i)
783 {
784 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
785
786 /* This will be < 0 if we truncated and the truncation was of a value
787 * that was > 0 in the first place.
788 */
789 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
790
791 return qir_SEL_X_Y_NS(c,
792 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
793 trunc);
794 }
795
796 static struct qreg
797 tgsi_to_qir_abs(struct vc4_compile *c,
798 struct tgsi_full_instruction *tgsi_inst,
799 enum qop op, struct qreg *src, int i)
800 {
801 struct qreg arg = src[0 * 4 + i];
802 return qir_FMAXABS(c, arg, arg);
803 }
804
805 /* Note that this instruction replicates its result from the x channel */
806 static struct qreg
807 tgsi_to_qir_sin(struct vc4_compile *c,
808 struct tgsi_full_instruction *tgsi_inst,
809 enum qop op, struct qreg *src, int i)
810 {
811 float coeff[] = {
812 -2.0 * M_PI,
813 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
814 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
815 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
816 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
817 };
818
819 struct qreg scaled_x =
820 qir_FMUL(c,
821 src[0 * 4 + 0],
822 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
823
824 struct qreg x = qir_FADD(c,
825 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
826 qir_uniform_f(c, -0.5));
827 struct qreg x2 = qir_FMUL(c, x, x);
828 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
829 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
830 x = qir_FMUL(c, x, x2);
831 sum = qir_FADD(c,
832 sum,
833 qir_FMUL(c,
834 x,
835 qir_uniform_f(c, coeff[i])));
836 }
837 return sum;
838 }
839
840 /* Note that this instruction replicates its result from the x channel */
841 static struct qreg
842 tgsi_to_qir_cos(struct vc4_compile *c,
843 struct tgsi_full_instruction *tgsi_inst,
844 enum qop op, struct qreg *src, int i)
845 {
846 float coeff[] = {
847 -1.0f,
848 pow(2.0 * M_PI, 2) / (2 * 1),
849 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
850 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
851 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
852 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
853 };
854
855 struct qreg scaled_x =
856 qir_FMUL(c, src[0 * 4 + 0],
857 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
858 struct qreg x_frac = qir_FADD(c,
859 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
860 qir_uniform_f(c, -0.5));
861
862 struct qreg sum = qir_uniform_f(c, coeff[0]);
863 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
864 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
865 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
866 if (i != 1)
867 x = qir_FMUL(c, x, x2);
868
869 struct qreg mul = qir_FMUL(c,
870 x,
871 qir_uniform_f(c, coeff[i]));
872 if (i == 0)
873 sum = mul;
874 else
875 sum = qir_FADD(c, sum, mul);
876 }
877 return sum;
878 }
879
880 static struct qreg
881 tgsi_to_qir_clamp(struct vc4_compile *c,
882 struct tgsi_full_instruction *tgsi_inst,
883 enum qop op, struct qreg *src, int i)
884 {
885 return qir_FMAX(c, qir_FMIN(c,
886 src[0 * 4 + i],
887 src[2 * 4 + i]),
888 src[1 * 4 + i]);
889 }
890
891 static struct qreg
892 tgsi_to_qir_ssg(struct vc4_compile *c,
893 struct tgsi_full_instruction *tgsi_inst,
894 enum qop op, struct qreg *src, int i)
895 {
896 qir_SF(c, src[0 * 4 + i]);
897 return qir_SEL_X_Y_NC(c,
898 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
899 qir_uniform_f(c, -1.0));
900 }
901
902 static void
903 emit_vertex_input(struct vc4_compile *c, int attr)
904 {
905 enum pipe_format format = c->vs_key->attr_formats[attr];
906 struct qreg vpm_reads[4];
907
908 /* Right now, we're setting the VPM offsets to be 16 bytes wide every
909 * time, so we always read 4 32-bit VPM entries.
910 */
911 for (int i = 0; i < 4; i++) {
912 vpm_reads[i] = qir_get_temp(c);
913 qir_emit(c, qir_inst(QOP_VPM_READ,
914 vpm_reads[i],
915 c->undef,
916 c->undef));
917 c->num_inputs++;
918 }
919
920 bool format_warned = false;
921 const struct util_format_description *desc =
922 util_format_description(format);
923
924 for (int i = 0; i < 4; i++) {
925 uint8_t swiz = desc->swizzle[i];
926 struct qreg result;
927
928 if (swiz > UTIL_FORMAT_SWIZZLE_W)
929 result = get_swizzled_channel(c, vpm_reads, swiz);
930 else if (desc->channel[swiz].size == 32 &&
931 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {
932 result = get_swizzled_channel(c, vpm_reads, swiz);
933 } else if (desc->channel[swiz].size == 8 &&
934 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||
935 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&
936 desc->channel[swiz].normalized) {
937 struct qreg vpm = vpm_reads[0];
938 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)
939 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
940 result = qir_UNPACK_8(c, vpm, swiz);
941 } else {
942 if (!format_warned) {
943 fprintf(stderr,
944 "vtx element %d unsupported type: %s\n",
945 attr, util_format_name(format));
946 format_warned = true;
947 }
948 result = qir_uniform_f(c, 0.0);
949 }
950
951 if (desc->channel[swiz].normalized &&
952 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {
953 result = qir_FSUB(c,
954 qir_FMUL(c,
955 result,
956 qir_uniform_f(c, 2.0)),
957 qir_uniform_f(c, 1.0));
958 }
959
960 c->inputs[attr * 4 + i] = result;
961 }
962 }
963
964 static void
965 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
966 {
967 if (c->discard.file == QFILE_NULL)
968 c->discard = qir_uniform_f(c, 0.0);
969 qir_SF(c, src[0 * 4 + i]);
970 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
971 c->discard);
972 }
973
974 static void
975 emit_fragcoord_input(struct vc4_compile *c, int attr)
976 {
977 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
978 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
979 c->inputs[attr * 4 + 2] =
980 qir_FMUL(c,
981 qir_ITOF(c, qir_FRAG_Z(c)),
982 qir_uniform_f(c, 1.0 / 0xffffff));
983 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
984 }
985
986 static void
987 emit_point_coord_input(struct vc4_compile *c, int attr)
988 {
989 if (c->point_x.file == QFILE_NULL) {
990 c->point_x = qir_uniform_f(c, 0.0);
991 c->point_y = qir_uniform_f(c, 0.0);
992 }
993
994 c->inputs[attr * 4 + 0] = c->point_x;
995 if (c->fs_key->point_coord_upper_left) {
996 c->inputs[attr * 4 + 1] = qir_FSUB(c,
997 qir_uniform_f(c, 1.0),
998 c->point_y);
999 } else {
1000 c->inputs[attr * 4 + 1] = c->point_y;
1001 }
1002 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1003 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1004 }
1005
1006 static struct qreg
1007 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1008 uint8_t index, uint8_t swizzle)
1009 {
1010 uint32_t i = c->num_input_semantics++;
1011 struct qreg vary = {
1012 QFILE_VARY,
1013 i
1014 };
1015
1016 if (c->num_input_semantics >= c->input_semantics_array_size) {
1017 c->input_semantics_array_size =
1018 MAX2(4, c->input_semantics_array_size * 2);
1019
1020 c->input_semantics = reralloc(c, c->input_semantics,
1021 struct vc4_varying_semantic,
1022 c->input_semantics_array_size);
1023 }
1024
1025 c->input_semantics[i].semantic = semantic;
1026 c->input_semantics[i].index = index;
1027 c->input_semantics[i].swizzle = swizzle;
1028
1029 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1030 }
1031
1032 static void
1033 emit_fragment_input(struct vc4_compile *c, int attr,
1034 struct tgsi_full_declaration *decl)
1035 {
1036 for (int i = 0; i < 4; i++) {
1037 c->inputs[attr * 4 + i] =
1038 emit_fragment_varying(c,
1039 decl->Semantic.Name,
1040 decl->Semantic.Index,
1041 i);
1042 c->num_inputs++;
1043 }
1044 }
1045
1046 static void
1047 emit_face_input(struct vc4_compile *c, int attr)
1048 {
1049 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1050 qir_uniform_f(c, 1.0),
1051 qir_FMUL(c,
1052 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1053 qir_uniform_f(c, 2.0)));
1054 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1055 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1056 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1057 }
1058
1059 static void
1060 add_output(struct vc4_compile *c,
1061 uint32_t decl_offset,
1062 uint8_t semantic_name,
1063 uint8_t semantic_index,
1064 uint8_t semantic_swizzle)
1065 {
1066 uint32_t old_array_size = c->outputs_array_size;
1067 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1068 decl_offset + 1);
1069
1070 if (old_array_size != c->outputs_array_size) {
1071 c->output_semantics = reralloc(c,
1072 c->output_semantics,
1073 struct vc4_varying_semantic,
1074 c->outputs_array_size);
1075 }
1076
1077 c->output_semantics[decl_offset].semantic = semantic_name;
1078 c->output_semantics[decl_offset].index = semantic_index;
1079 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1080 }
1081
1082 static void
1083 emit_tgsi_declaration(struct vc4_compile *c,
1084 struct tgsi_full_declaration *decl)
1085 {
1086 switch (decl->Declaration.File) {
1087 case TGSI_FILE_TEMPORARY: {
1088 uint32_t old_size = c->temps_array_size;
1089 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1090 (decl->Range.Last + 1) * 4);
1091
1092 for (int i = old_size; i < c->temps_array_size; i++)
1093 c->temps[i] = qir_uniform_ui(c, 0);
1094 break;
1095 }
1096
1097 case TGSI_FILE_INPUT:
1098 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1099 (decl->Range.Last + 1) * 4);
1100
1101 for (int i = decl->Range.First;
1102 i <= decl->Range.Last;
1103 i++) {
1104 if (c->stage == QSTAGE_FRAG) {
1105 if (decl->Semantic.Name ==
1106 TGSI_SEMANTIC_POSITION) {
1107 emit_fragcoord_input(c, i);
1108 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1109 emit_face_input(c, i);
1110 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1111 (c->fs_key->point_sprite_mask &
1112 (1 << decl->Semantic.Index))) {
1113 emit_point_coord_input(c, i);
1114 } else {
1115 emit_fragment_input(c, i, decl);
1116 }
1117 } else {
1118 emit_vertex_input(c, i);
1119 }
1120 }
1121 break;
1122
1123 case TGSI_FILE_OUTPUT: {
1124 for (int i = 0; i < 4; i++) {
1125 add_output(c,
1126 decl->Range.First * 4 + i,
1127 decl->Semantic.Name,
1128 decl->Semantic.Index,
1129 i);
1130 }
1131
1132 switch (decl->Semantic.Name) {
1133 case TGSI_SEMANTIC_POSITION:
1134 c->output_position_index = decl->Range.First * 4;
1135 break;
1136 case TGSI_SEMANTIC_CLIPVERTEX:
1137 c->output_clipvertex_index = decl->Range.First * 4;
1138 break;
1139 case TGSI_SEMANTIC_COLOR:
1140 c->output_color_index = decl->Range.First * 4;
1141 break;
1142 case TGSI_SEMANTIC_PSIZE:
1143 c->output_point_size_index = decl->Range.First * 4;
1144 break;
1145 }
1146
1147 break;
1148 }
1149 }
1150 }
1151
1152 static void
1153 emit_tgsi_instruction(struct vc4_compile *c,
1154 struct tgsi_full_instruction *tgsi_inst)
1155 {
1156 struct {
1157 enum qop op;
1158 struct qreg (*func)(struct vc4_compile *c,
1159 struct tgsi_full_instruction *tgsi_inst,
1160 enum qop op,
1161 struct qreg *src, int i);
1162 } op_trans[] = {
1163 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1164 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1165 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1166 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1167 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1168 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1169 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1170 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1171 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1172 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1173 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1174 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1175 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1176 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1177 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1178 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1179 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1180 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1181 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1182
1183 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1184 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1185 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1186
1187 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1188 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1189 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1190 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1191 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1192 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1193 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1194 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1195 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1196 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1197 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1198 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1199
1200 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1201 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1202 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1203 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1204 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1205 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1206 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1207 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1208 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1209 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1210 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1211 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1212 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1213 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1214 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1215 };
1216 static int asdf = 0;
1217 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1218
1219 if (tgsi_op == TGSI_OPCODE_END)
1220 return;
1221
1222 struct qreg src_regs[12];
1223 for (int s = 0; s < 3; s++) {
1224 for (int i = 0; i < 4; i++) {
1225 src_regs[4 * s + i] =
1226 get_src(c, tgsi_inst->Instruction.Opcode,
1227 &tgsi_inst->Src[s].Register, i);
1228 }
1229 }
1230
1231 switch (tgsi_op) {
1232 case TGSI_OPCODE_TEX:
1233 case TGSI_OPCODE_TXP:
1234 case TGSI_OPCODE_TXB:
1235 case TGSI_OPCODE_TXL:
1236 tgsi_to_qir_tex(c, tgsi_inst,
1237 op_trans[tgsi_op].op, src_regs);
1238 return;
1239 case TGSI_OPCODE_KILL:
1240 c->discard = qir_uniform_f(c, 1.0);
1241 return;
1242 case TGSI_OPCODE_KILL_IF:
1243 for (int i = 0; i < 4; i++)
1244 tgsi_to_qir_kill_if(c, src_regs, i);
1245 return;
1246 default:
1247 break;
1248 }
1249
1250 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1251 fprintf(stderr, "unknown tgsi inst: ");
1252 tgsi_dump_instruction(tgsi_inst, asdf++);
1253 fprintf(stderr, "\n");
1254 abort();
1255 }
1256
1257 for (int i = 0; i < 4; i++) {
1258 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1259 continue;
1260
1261 struct qreg result;
1262
1263 result = op_trans[tgsi_op].func(c, tgsi_inst,
1264 op_trans[tgsi_op].op,
1265 src_regs, i);
1266
1267 if (tgsi_inst->Instruction.Saturate) {
1268 float low = (tgsi_inst->Instruction.Saturate ==
1269 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1270 result = qir_FMAX(c,
1271 qir_FMIN(c,
1272 result,
1273 qir_uniform_f(c, 1.0)),
1274 qir_uniform_f(c, low));
1275 }
1276
1277 update_dst(c, tgsi_inst, i, result);
1278 }
1279 }
1280
1281 static void
1282 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1283 {
1284 for (int i = 0; i < 4; i++) {
1285 unsigned n = c->num_consts++;
1286 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1287 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1288 }
1289 }
1290
1291 static struct qreg
1292 vc4_blend_channel(struct vc4_compile *c,
1293 struct qreg *dst,
1294 struct qreg *src,
1295 struct qreg val,
1296 unsigned factor,
1297 int channel)
1298 {
1299 switch(factor) {
1300 case PIPE_BLENDFACTOR_ONE:
1301 return val;
1302 case PIPE_BLENDFACTOR_SRC_COLOR:
1303 return qir_FMUL(c, val, src[channel]);
1304 case PIPE_BLENDFACTOR_SRC_ALPHA:
1305 return qir_FMUL(c, val, src[3]);
1306 case PIPE_BLENDFACTOR_DST_ALPHA:
1307 return qir_FMUL(c, val, dst[3]);
1308 case PIPE_BLENDFACTOR_DST_COLOR:
1309 return qir_FMUL(c, val, dst[channel]);
1310 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1311 return qir_FMIN(c, src[3], qir_FSUB(c,
1312 qir_uniform_f(c, 1.0),
1313 dst[3]));
1314 case PIPE_BLENDFACTOR_CONST_COLOR:
1315 return qir_FMUL(c, val,
1316 get_temp_for_uniform(c,
1317 QUNIFORM_BLEND_CONST_COLOR,
1318 channel));
1319 case PIPE_BLENDFACTOR_CONST_ALPHA:
1320 return qir_FMUL(c, val,
1321 get_temp_for_uniform(c,
1322 QUNIFORM_BLEND_CONST_COLOR,
1323 3));
1324 case PIPE_BLENDFACTOR_ZERO:
1325 return qir_uniform_f(c, 0.0);
1326 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1327 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1328 src[channel]));
1329 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1330 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1331 src[3]));
1332 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1333 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1334 dst[3]));
1335 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1336 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1337 dst[channel]));
1338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1339 return qir_FMUL(c, val,
1340 qir_FSUB(c, qir_uniform_f(c, 1.0),
1341 get_temp_for_uniform(c,
1342 QUNIFORM_BLEND_CONST_COLOR,
1343 channel)));
1344 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1345 return qir_FMUL(c, val,
1346 qir_FSUB(c, qir_uniform_f(c, 1.0),
1347 get_temp_for_uniform(c,
1348 QUNIFORM_BLEND_CONST_COLOR,
1349 3)));
1350
1351 default:
1352 case PIPE_BLENDFACTOR_SRC1_COLOR:
1353 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1354 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1355 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1356 /* Unsupported. */
1357 fprintf(stderr, "Unknown blend factor %d\n", factor);
1358 return val;
1359 }
1360 }
1361
1362 static struct qreg
1363 vc4_blend_func(struct vc4_compile *c,
1364 struct qreg src, struct qreg dst,
1365 unsigned func)
1366 {
1367 switch (func) {
1368 case PIPE_BLEND_ADD:
1369 return qir_FADD(c, src, dst);
1370 case PIPE_BLEND_SUBTRACT:
1371 return qir_FSUB(c, src, dst);
1372 case PIPE_BLEND_REVERSE_SUBTRACT:
1373 return qir_FSUB(c, dst, src);
1374 case PIPE_BLEND_MIN:
1375 return qir_FMIN(c, src, dst);
1376 case PIPE_BLEND_MAX:
1377 return qir_FMAX(c, src, dst);
1378
1379 default:
1380 /* Unsupported. */
1381 fprintf(stderr, "Unknown blend func %d\n", func);
1382 return src;
1383
1384 }
1385 }
1386
1387 /**
1388 * Implements fixed function blending in shader code.
1389 *
1390 * VC4 doesn't have any hardware support for blending. Instead, you read the
1391 * current contents of the destination from the tile buffer after having
1392 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1393 * math using your output color and that destination value, and update the
1394 * output color appropriately.
1395 */
1396 static void
1397 vc4_blend(struct vc4_compile *c, struct qreg *result,
1398 struct qreg *dst_color, struct qreg *src_color)
1399 {
1400 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1401
1402 if (!blend->blend_enable) {
1403 for (int i = 0; i < 4; i++)
1404 result[i] = src_color[i];
1405 return;
1406 }
1407
1408 struct qreg src_blend[4], dst_blend[4];
1409 for (int i = 0; i < 3; i++) {
1410 src_blend[i] = vc4_blend_channel(c,
1411 dst_color, src_color,
1412 src_color[i],
1413 blend->rgb_src_factor, i);
1414 dst_blend[i] = vc4_blend_channel(c,
1415 dst_color, src_color,
1416 dst_color[i],
1417 blend->rgb_dst_factor, i);
1418 }
1419 src_blend[3] = vc4_blend_channel(c,
1420 dst_color, src_color,
1421 src_color[3],
1422 blend->alpha_src_factor, 3);
1423 dst_blend[3] = vc4_blend_channel(c,
1424 dst_color, src_color,
1425 dst_color[3],
1426 blend->alpha_dst_factor, 3);
1427
1428 for (int i = 0; i < 3; i++) {
1429 result[i] = vc4_blend_func(c,
1430 src_blend[i], dst_blend[i],
1431 blend->rgb_func);
1432 }
1433 result[3] = vc4_blend_func(c,
1434 src_blend[3], dst_blend[3],
1435 blend->alpha_func);
1436 }
1437
1438 static void
1439 clip_distance_discard(struct vc4_compile *c)
1440 {
1441 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1442 if (!(c->key->ucp_enables & (1 << i)))
1443 continue;
1444
1445 struct qreg dist = emit_fragment_varying(c,
1446 TGSI_SEMANTIC_CLIPDIST,
1447 i,
1448 TGSI_SWIZZLE_X);
1449
1450 qir_SF(c, dist);
1451
1452 if (c->discard.file == QFILE_NULL)
1453 c->discard = qir_uniform_f(c, 0.0);
1454
1455 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1456 c->discard);
1457 }
1458 }
1459
1460 static void
1461 alpha_test_discard(struct vc4_compile *c)
1462 {
1463 struct qreg src_alpha;
1464 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);
1465
1466 if (!c->fs_key->alpha_test)
1467 return;
1468
1469 if (c->output_color_index != -1)
1470 src_alpha = c->outputs[c->output_color_index + 3];
1471 else
1472 src_alpha = qir_uniform_f(c, 1.0);
1473
1474 if (c->discard.file == QFILE_NULL)
1475 c->discard = qir_uniform_f(c, 0.0);
1476
1477 switch (c->fs_key->alpha_test_func) {
1478 case PIPE_FUNC_NEVER:
1479 c->discard = qir_uniform_f(c, 1.0);
1480 break;
1481 case PIPE_FUNC_ALWAYS:
1482 break;
1483 case PIPE_FUNC_EQUAL:
1484 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1485 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1486 qir_uniform_f(c, 1.0));
1487 break;
1488 case PIPE_FUNC_NOTEQUAL:
1489 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1490 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1491 qir_uniform_f(c, 1.0));
1492 break;
1493 case PIPE_FUNC_GREATER:
1494 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1495 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1496 qir_uniform_f(c, 1.0));
1497 break;
1498 case PIPE_FUNC_GEQUAL:
1499 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1500 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1501 qir_uniform_f(c, 1.0));
1502 break;
1503 case PIPE_FUNC_LESS:
1504 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1505 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1506 qir_uniform_f(c, 1.0));
1507 break;
1508 case PIPE_FUNC_LEQUAL:
1509 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1510 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1511 qir_uniform_f(c, 1.0));
1512 break;
1513 }
1514 }
1515
1516 static void
1517 emit_frag_end(struct vc4_compile *c)
1518 {
1519 clip_distance_discard(c);
1520 alpha_test_discard(c);
1521
1522 enum pipe_format color_format = c->fs_key->color_format;
1523 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1524 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1525 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1526 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1527 if (c->fs_key->blend.blend_enable ||
1528 c->fs_key->blend.colormask != 0xf) {
1529 struct qreg r4 = qir_TLB_COLOR_READ(c);
1530 for (int i = 0; i < 4; i++)
1531 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1532 for (int i = 0; i < 4; i++) {
1533 dst_color[i] = get_swizzled_channel(c,
1534 tlb_read_color,
1535 format_swiz[i]);
1536 if (util_format_is_srgb(color_format) && i != 3) {
1537 linear_dst_color[i] =
1538 qir_srgb_decode(c, dst_color[i]);
1539 } else {
1540 linear_dst_color[i] = dst_color[i];
1541 }
1542 }
1543 }
1544
1545 struct qreg blend_color[4];
1546 struct qreg undef_array[4] = {
1547 c->undef, c->undef, c->undef, c->undef
1548 };
1549 vc4_blend(c, blend_color, linear_dst_color,
1550 (c->output_color_index != -1 ?
1551 c->outputs + c->output_color_index :
1552 undef_array));
1553
1554 if (util_format_is_srgb(color_format)) {
1555 for (int i = 0; i < 3; i++)
1556 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1557 }
1558
1559 /* If the bit isn't set in the color mask, then just return the
1560 * original dst color, instead.
1561 */
1562 for (int i = 0; i < 4; i++) {
1563 if (!(c->fs_key->blend.colormask & (1 << i))) {
1564 blend_color[i] = dst_color[i];
1565 }
1566 }
1567
1568 /* Debug: Sometimes you're getting a black output and just want to see
1569 * if the FS is getting executed at all. Spam magenta into the color
1570 * output.
1571 */
1572 if (0) {
1573 blend_color[0] = qir_uniform_f(c, 1.0);
1574 blend_color[1] = qir_uniform_f(c, 0.0);
1575 blend_color[2] = qir_uniform_f(c, 1.0);
1576 blend_color[3] = qir_uniform_f(c, 0.5);
1577 }
1578
1579 struct qreg swizzled_outputs[4];
1580 for (int i = 0; i < 4; i++) {
1581 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1582 format_swiz[i]);
1583 }
1584
1585 if (c->discard.file != QFILE_NULL)
1586 qir_TLB_DISCARD_SETUP(c, c->discard);
1587
1588 if (c->fs_key->stencil_enabled) {
1589 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));
1590 if (c->fs_key->stencil_twoside) {
1591 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));
1592 }
1593 if (c->fs_key->stencil_full_writemasks) {
1594 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));
1595 }
1596 }
1597
1598 if (c->fs_key->depth_enabled) {
1599 struct qreg z;
1600 if (c->output_position_index != -1) {
1601 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1602 qir_uniform_f(c, 0xffffff)));
1603 } else {
1604 z = qir_FRAG_Z(c);
1605 }
1606 qir_TLB_Z_WRITE(c, z);
1607 }
1608
1609 bool color_written = false;
1610 for (int i = 0; i < 4; i++) {
1611 if (swizzled_outputs[i].file != QFILE_NULL)
1612 color_written = true;
1613 }
1614
1615 struct qreg packed_color;
1616 if (color_written) {
1617 /* Fill in any undefined colors. The simulator will assertion
1618 * fail if we read something that wasn't written, and I don't
1619 * know what hardware does.
1620 */
1621 for (int i = 0; i < 4; i++) {
1622 if (swizzled_outputs[i].file == QFILE_NULL)
1623 swizzled_outputs[i] = qir_uniform_f(c, 0.0);
1624 }
1625 packed_color = qir_get_temp(c);
1626 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,
1627 swizzled_outputs[0],
1628 swizzled_outputs[1],
1629 swizzled_outputs[2],
1630 swizzled_outputs[3]));
1631 } else {
1632 packed_color = qir_uniform_ui(c, 0);
1633 }
1634
1635 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1636 packed_color, c->undef));
1637 }
1638
1639 static void
1640 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1641 {
1642 struct qreg xyi[2];
1643
1644 for (int i = 0; i < 2; i++) {
1645 struct qreg scale =
1646 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1647
1648 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1649 qir_FMUL(c,
1650 c->outputs[i],
1651 scale),
1652 rcp_w));
1653 }
1654
1655 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1656 }
1657
1658 static void
1659 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1660 {
1661 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1662 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1663
1664 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,
1665 c->outputs[2],
1666 zscale),
1667 zoffset),
1668 rcp_w));
1669 }
1670
1671 static void
1672 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1673 {
1674 qir_VPM_WRITE(c, rcp_w);
1675 }
1676
1677 static void
1678 emit_point_size_write(struct vc4_compile *c)
1679 {
1680 struct qreg point_size;
1681
1682 if (c->output_point_size_index)
1683 point_size = c->outputs[c->output_point_size_index + 3];
1684 else
1685 point_size = qir_uniform_f(c, 1.0);
1686
1687 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1688 * BCM21553).
1689 */
1690 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1691
1692 qir_VPM_WRITE(c, point_size);
1693 }
1694
1695 /**
1696 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1697 *
1698 * The simulator insists that there be at least one vertex attribute, so
1699 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1700 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1701 * to consume it here.
1702 */
1703 static void
1704 emit_stub_vpm_read(struct vc4_compile *c)
1705 {
1706 if (c->num_inputs)
1707 return;
1708
1709 for (int i = 0; i < 4; i++) {
1710 qir_emit(c, qir_inst(QOP_VPM_READ,
1711 qir_get_temp(c),
1712 c->undef,
1713 c->undef));
1714 c->num_inputs++;
1715 }
1716 }
1717
1718 static void
1719 emit_ucp_clipdistance(struct vc4_compile *c)
1720 {
1721 struct qreg *clipvertex;
1722
1723 if (c->output_clipvertex_index != -1)
1724 clipvertex = &c->outputs[c->output_clipvertex_index];
1725 else if (c->output_position_index != -1)
1726 clipvertex = &c->outputs[c->output_position_index];
1727 else
1728 return;
1729
1730 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1731 if (!(c->key->ucp_enables & (1 << plane)))
1732 continue;
1733
1734 /* Pick the next outputs[] that hasn't been written to, since
1735 * there are no other program writes left to be processed at
1736 * this point. If something had been declared but not written
1737 * (like a w component), we'll just smash over the top of it.
1738 */
1739 uint32_t output_index = c->num_outputs++;
1740 add_output(c, output_index,
1741 TGSI_SEMANTIC_CLIPDIST,
1742 plane,
1743 TGSI_SWIZZLE_X);
1744
1745 struct qreg dist = qir_uniform_f(c, 0.0);
1746 for (int i = 0; i < 4; i++) {
1747 struct qreg ucp =
1748 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1749 plane * 4 + i);
1750 dist = qir_FADD(c, dist, qir_FMUL(c, clipvertex[i], ucp));
1751 }
1752
1753 c->outputs[output_index] = dist;
1754 }
1755 }
1756
1757 static void
1758 emit_vert_end(struct vc4_compile *c,
1759 struct vc4_varying_semantic *fs_inputs,
1760 uint32_t num_fs_inputs)
1761 {
1762 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1763
1764 emit_stub_vpm_read(c);
1765 emit_ucp_clipdistance(c);
1766
1767 emit_scaled_viewport_write(c, rcp_w);
1768 emit_zs_write(c, rcp_w);
1769 emit_rcp_wc_write(c, rcp_w);
1770 if (c->vs_key->per_vertex_point_size)
1771 emit_point_size_write(c);
1772
1773 for (int i = 0; i < num_fs_inputs; i++) {
1774 struct vc4_varying_semantic *input = &fs_inputs[i];
1775 int j;
1776
1777 for (j = 0; j < c->num_outputs; j++) {
1778 struct vc4_varying_semantic *output =
1779 &c->output_semantics[j];
1780
1781 if (input->semantic == output->semantic &&
1782 input->index == output->index &&
1783 input->swizzle == output->swizzle) {
1784 qir_VPM_WRITE(c, c->outputs[j]);
1785 break;
1786 }
1787 }
1788 /* Emit padding if we didn't find a declared VS output for
1789 * this FS input.
1790 */
1791 if (j == c->num_outputs)
1792 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1793 }
1794 }
1795
1796 static void
1797 emit_coord_end(struct vc4_compile *c)
1798 {
1799 struct qreg rcp_w = qir_RCP(c, c->outputs[3]);
1800
1801 emit_stub_vpm_read(c);
1802
1803 for (int i = 0; i < 4; i++)
1804 qir_VPM_WRITE(c, c->outputs[i]);
1805
1806 emit_scaled_viewport_write(c, rcp_w);
1807 emit_zs_write(c, rcp_w);
1808 emit_rcp_wc_write(c, rcp_w);
1809 if (c->vs_key->per_vertex_point_size)
1810 emit_point_size_write(c);
1811 }
1812
1813 static struct vc4_compile *
1814 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1815 struct vc4_key *key)
1816 {
1817 struct vc4_compile *c = qir_compile_init();
1818 int ret;
1819
1820 c->stage = stage;
1821 c->shader_state = &key->shader_state->base;
1822
1823 c->key = key;
1824 switch (stage) {
1825 case QSTAGE_FRAG:
1826 c->fs_key = (struct vc4_fs_key *)key;
1827 if (c->fs_key->is_points) {
1828 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
1829 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
1830 } else if (c->fs_key->is_lines) {
1831 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
1832 }
1833 break;
1834 case QSTAGE_VERT:
1835 c->vs_key = (struct vc4_vs_key *)key;
1836 break;
1837 case QSTAGE_COORD:
1838 c->vs_key = (struct vc4_vs_key *)key;
1839 break;
1840 }
1841
1842 const struct tgsi_token *tokens = key->shader_state->base.tokens;
1843 if (c->fs_key && c->fs_key->light_twoside) {
1844 if (!key->shader_state->twoside_tokens) {
1845 const struct tgsi_lowering_config lowering_config = {
1846 .color_two_side = true,
1847 };
1848 struct tgsi_shader_info info;
1849 key->shader_state->twoside_tokens =
1850 tgsi_transform_lowering(&lowering_config,
1851 key->shader_state->base.tokens,
1852 &info);
1853
1854 /* If no transformation occurred, then NULL is
1855 * returned and we just use our original tokens.
1856 */
1857 if (!key->shader_state->twoside_tokens) {
1858 key->shader_state->twoside_tokens =
1859 key->shader_state->base.tokens;
1860 }
1861 }
1862 tokens = key->shader_state->twoside_tokens;
1863 }
1864
1865 ret = tgsi_parse_init(&c->parser, tokens);
1866 assert(ret == TGSI_PARSE_OK);
1867
1868 if (vc4_debug & VC4_DEBUG_TGSI) {
1869 fprintf(stderr, "TGSI:\n");
1870 tgsi_dump(tokens, 0);
1871 }
1872
1873 while (!tgsi_parse_end_of_tokens(&c->parser)) {
1874 tgsi_parse_token(&c->parser);
1875
1876 switch (c->parser.FullToken.Token.Type) {
1877 case TGSI_TOKEN_TYPE_DECLARATION:
1878 emit_tgsi_declaration(c,
1879 &c->parser.FullToken.FullDeclaration);
1880 break;
1881
1882 case TGSI_TOKEN_TYPE_INSTRUCTION:
1883 emit_tgsi_instruction(c,
1884 &c->parser.FullToken.FullInstruction);
1885 break;
1886
1887 case TGSI_TOKEN_TYPE_IMMEDIATE:
1888 parse_tgsi_immediate(c,
1889 &c->parser.FullToken.FullImmediate);
1890 break;
1891 }
1892 }
1893
1894 switch (stage) {
1895 case QSTAGE_FRAG:
1896 emit_frag_end(c);
1897 break;
1898 case QSTAGE_VERT:
1899 emit_vert_end(c,
1900 vc4->prog.fs->input_semantics,
1901 vc4->prog.fs->num_inputs);
1902 break;
1903 case QSTAGE_COORD:
1904 emit_coord_end(c);
1905 break;
1906 }
1907
1908 tgsi_parse_free(&c->parser);
1909
1910 qir_optimize(c);
1911
1912 if (vc4_debug & VC4_DEBUG_QIR) {
1913 fprintf(stderr, "QIR:\n");
1914 qir_dump(c);
1915 }
1916 qir_reorder_uniforms(c);
1917 vc4_generate_code(vc4, c);
1918
1919 if (vc4_debug & VC4_DEBUG_SHADERDB) {
1920 fprintf(stderr, "SHADER-DB: %s: %d instructions\n",
1921 qir_get_stage_name(c->stage), c->qpu_inst_count);
1922 fprintf(stderr, "SHADER-DB: %s: %d uniforms\n",
1923 qir_get_stage_name(c->stage), c->num_uniforms);
1924 }
1925
1926 return c;
1927 }
1928
1929 static void *
1930 vc4_shader_state_create(struct pipe_context *pctx,
1931 const struct pipe_shader_state *cso)
1932 {
1933 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
1934 if (!so)
1935 return NULL;
1936
1937 const struct tgsi_lowering_config lowering_config = {
1938 .lower_DST = true,
1939 .lower_XPD = true,
1940 .lower_SCS = true,
1941 .lower_POW = true,
1942 .lower_LIT = true,
1943 .lower_EXP = true,
1944 .lower_LOG = true,
1945 .lower_DP4 = true,
1946 .lower_DP3 = true,
1947 .lower_DPH = true,
1948 .lower_DP2 = true,
1949 .lower_DP2A = true,
1950 };
1951
1952 struct tgsi_shader_info info;
1953 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
1954 if (!so->base.tokens)
1955 so->base.tokens = tgsi_dup_tokens(cso->tokens);
1956
1957 return so;
1958 }
1959
1960 static void
1961 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
1962 struct vc4_compile *c)
1963 {
1964 int count = c->num_uniforms;
1965 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
1966
1967 uinfo->count = count;
1968 uinfo->data = ralloc_array(shader, uint32_t, count);
1969 memcpy(uinfo->data, c->uniform_data,
1970 count * sizeof(*uinfo->data));
1971 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
1972 memcpy(uinfo->contents, c->uniform_contents,
1973 count * sizeof(*uinfo->contents));
1974 uinfo->num_texture_samples = c->num_texture_samples;
1975 }
1976
1977 static struct vc4_compiled_shader *
1978 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
1979 struct vc4_key *key)
1980 {
1981 struct util_hash_table *ht;
1982 uint32_t key_size;
1983 if (stage == QSTAGE_FRAG) {
1984 ht = vc4->fs_cache;
1985 key_size = sizeof(struct vc4_fs_key);
1986 } else {
1987 ht = vc4->vs_cache;
1988 key_size = sizeof(struct vc4_vs_key);
1989 }
1990
1991 struct vc4_compiled_shader *shader;
1992 shader = util_hash_table_get(ht, key);
1993 if (shader)
1994 return shader;
1995
1996 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
1997 shader = rzalloc(NULL, struct vc4_compiled_shader);
1998
1999 shader->program_id = vc4->next_compiled_program_id++;
2000 if (stage == QSTAGE_FRAG) {
2001 shader->input_semantics = ralloc_array(shader,
2002 struct vc4_varying_semantic,
2003 c->num_input_semantics);
2004
2005 for (int i = 0; i < c->num_input_semantics; i++) {
2006 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2007
2008 /* Skip non-VS-output inputs. */
2009 if (sem->semantic == (uint8_t)~0)
2010 continue;
2011
2012 if (sem->semantic == TGSI_SEMANTIC_COLOR)
2013 shader->color_inputs |= (1 << shader->num_inputs);
2014 shader->input_semantics[shader->num_inputs] = *sem;
2015 shader->num_inputs++;
2016 }
2017 } else {
2018 shader->num_inputs = c->num_inputs;
2019 }
2020
2021 copy_uniform_state_to_shader(shader, c);
2022 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2023 c->qpu_inst_count * sizeof(uint64_t),
2024 "code");
2025
2026 qir_compile_destroy(c);
2027
2028 struct vc4_key *dup_key;
2029 dup_key = malloc(key_size);
2030 memcpy(dup_key, key, key_size);
2031 util_hash_table_set(ht, dup_key, shader);
2032
2033 return shader;
2034 }
2035
2036 static void
2037 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2038 struct vc4_texture_stateobj *texstate)
2039 {
2040 for (int i = 0; i < texstate->num_textures; i++) {
2041 struct pipe_sampler_view *sampler = texstate->textures[i];
2042 struct pipe_sampler_state *sampler_state =
2043 texstate->samplers[i];
2044
2045 if (sampler) {
2046 key->tex[i].format = sampler->format;
2047 key->tex[i].swizzle[0] = sampler->swizzle_r;
2048 key->tex[i].swizzle[1] = sampler->swizzle_g;
2049 key->tex[i].swizzle[2] = sampler->swizzle_b;
2050 key->tex[i].swizzle[3] = sampler->swizzle_a;
2051 key->tex[i].compare_mode = sampler_state->compare_mode;
2052 key->tex[i].compare_func = sampler_state->compare_func;
2053 key->tex[i].wrap_s = sampler_state->wrap_s;
2054 key->tex[i].wrap_t = sampler_state->wrap_t;
2055 }
2056 }
2057
2058 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2059 }
2060
2061 static void
2062 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2063 {
2064 struct vc4_fs_key local_key;
2065 struct vc4_fs_key *key = &local_key;
2066
2067 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2068 VC4_DIRTY_BLEND |
2069 VC4_DIRTY_FRAMEBUFFER |
2070 VC4_DIRTY_ZSA |
2071 VC4_DIRTY_RASTERIZER |
2072 VC4_DIRTY_FRAGTEX |
2073 VC4_DIRTY_TEXSTATE |
2074 VC4_DIRTY_PROG))) {
2075 return;
2076 }
2077
2078 memset(key, 0, sizeof(*key));
2079 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2080 key->base.shader_state = vc4->prog.bind_fs;
2081 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2082 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2083 prim_mode <= PIPE_PRIM_LINE_STRIP);
2084 key->blend = vc4->blend->rt[0];
2085
2086 if (vc4->framebuffer.cbufs[0])
2087 key->color_format = vc4->framebuffer.cbufs[0]->format;
2088
2089 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2090 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2091 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2092 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2093 key->stencil_enabled);
2094 if (vc4->zsa->base.alpha.enabled) {
2095 key->alpha_test = true;
2096 key->alpha_test_func = vc4->zsa->base.alpha.func;
2097 }
2098
2099 if (key->is_points) {
2100 key->point_sprite_mask =
2101 vc4->rasterizer->base.sprite_coord_enable;
2102 key->point_coord_upper_left =
2103 (vc4->rasterizer->base.sprite_coord_mode ==
2104 PIPE_SPRITE_COORD_UPPER_LEFT);
2105 }
2106
2107 key->light_twoside = vc4->rasterizer->base.light_twoside;
2108
2109 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2110 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2111 if (vc4->prog.fs == old_fs)
2112 return;
2113
2114 if (vc4->rasterizer->base.flatshade &&
2115 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2116 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2117 }
2118 }
2119
2120 static void
2121 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2122 {
2123 struct vc4_vs_key local_key;
2124 struct vc4_vs_key *key = &local_key;
2125
2126 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2127 VC4_DIRTY_RASTERIZER |
2128 VC4_DIRTY_VERTTEX |
2129 VC4_DIRTY_TEXSTATE |
2130 VC4_DIRTY_VTXSTATE |
2131 VC4_DIRTY_PROG))) {
2132 return;
2133 }
2134
2135 memset(key, 0, sizeof(*key));
2136 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2137 key->base.shader_state = vc4->prog.bind_vs;
2138 key->compiled_fs_id = vc4->prog.fs->program_id;
2139
2140 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2141 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2142
2143 key->per_vertex_point_size =
2144 (prim_mode == PIPE_PRIM_POINTS &&
2145 vc4->rasterizer->base.point_size_per_vertex);
2146
2147 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2148 key->is_coord = true;
2149 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2150 }
2151
2152 void
2153 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2154 {
2155 vc4_update_compiled_fs(vc4, prim_mode);
2156 vc4_update_compiled_vs(vc4, prim_mode);
2157 }
2158
2159 static unsigned
2160 fs_cache_hash(void *key)
2161 {
2162 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2163 }
2164
2165 static unsigned
2166 vs_cache_hash(void *key)
2167 {
2168 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2169 }
2170
2171 static int
2172 fs_cache_compare(void *key1, void *key2)
2173 {
2174 return memcmp(key1, key2, sizeof(struct vc4_fs_key));
2175 }
2176
2177 static int
2178 vs_cache_compare(void *key1, void *key2)
2179 {
2180 return memcmp(key1, key2, sizeof(struct vc4_vs_key));
2181 }
2182
2183 struct delete_state {
2184 struct vc4_context *vc4;
2185 struct vc4_uncompiled_shader *shader_state;
2186 };
2187
2188 static enum pipe_error
2189 fs_delete_from_cache(void *in_key, void *in_value, void *data)
2190 {
2191 struct delete_state *del = data;
2192 struct vc4_fs_key *key = in_key;
2193 struct vc4_compiled_shader *shader = in_value;
2194
2195 if (key->base.shader_state == data) {
2196 util_hash_table_remove(del->vc4->fs_cache, key);
2197 vc4_bo_unreference(&shader->bo);
2198 ralloc_free(shader);
2199 }
2200
2201 return 0;
2202 }
2203
2204 static enum pipe_error
2205 vs_delete_from_cache(void *in_key, void *in_value, void *data)
2206 {
2207 struct delete_state *del = data;
2208 struct vc4_vs_key *key = in_key;
2209 struct vc4_compiled_shader *shader = in_value;
2210
2211 if (key->base.shader_state == data) {
2212 util_hash_table_remove(del->vc4->vs_cache, key);
2213 vc4_bo_unreference(&shader->bo);
2214 ralloc_free(shader);
2215 }
2216
2217 return 0;
2218 }
2219
2220 static void
2221 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2222 {
2223 struct vc4_context *vc4 = vc4_context(pctx);
2224 struct vc4_uncompiled_shader *so = hwcso;
2225 struct delete_state del;
2226
2227 del.vc4 = vc4;
2228 del.shader_state = so;
2229 util_hash_table_foreach(vc4->fs_cache, fs_delete_from_cache, &del);
2230 util_hash_table_foreach(vc4->vs_cache, vs_delete_from_cache, &del);
2231
2232 if (so->twoside_tokens != so->base.tokens)
2233 free((void *)so->twoside_tokens);
2234 free((void *)so->base.tokens);
2235 free(so);
2236 }
2237
2238 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2239 {
2240 switch (p_wrap) {
2241 case PIPE_TEX_WRAP_REPEAT:
2242 return 0;
2243 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2244 return 1;
2245 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2246 return 2;
2247 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2248 return 3;
2249 case PIPE_TEX_WRAP_CLAMP:
2250 return (using_nearest ? 1 : 3);
2251 default:
2252 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2253 assert(!"not reached");
2254 return 0;
2255 }
2256 }
2257
2258 static void
2259 write_texture_p0(struct vc4_context *vc4,
2260 struct vc4_texture_stateobj *texstate,
2261 uint32_t unit)
2262 {
2263 struct pipe_sampler_view *texture = texstate->textures[unit];
2264 struct vc4_resource *rsc = vc4_resource(texture->texture);
2265
2266 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2267 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2268 VC4_SET_FIELD(texture->u.tex.last_level, VC4_TEX_P0_MIPLVLS) |
2269 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2270 VC4_TEX_P0_CMMODE) |
2271 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));
2272 }
2273
2274 static void
2275 write_texture_p1(struct vc4_context *vc4,
2276 struct vc4_texture_stateobj *texstate,
2277 uint32_t unit)
2278 {
2279 struct pipe_sampler_view *texture = texstate->textures[unit];
2280 struct vc4_resource *rsc = vc4_resource(texture->texture);
2281 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2282 static const uint8_t minfilter_map[6] = {
2283 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2284 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2285 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2286 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2287 VC4_TEX_P1_MINFILT_NEAREST,
2288 VC4_TEX_P1_MINFILT_LINEAR,
2289 };
2290 static const uint32_t magfilter_map[] = {
2291 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2292 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2293 };
2294
2295 bool either_nearest =
2296 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2297 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2298
2299 cl_u32(&vc4->uniforms,
2300 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2301 VC4_SET_FIELD(texture->texture->height0 & 2047,
2302 VC4_TEX_P1_HEIGHT) |
2303 VC4_SET_FIELD(texture->texture->width0 & 2047,
2304 VC4_TEX_P1_WIDTH) |
2305 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2306 VC4_TEX_P1_MAGFILT) |
2307 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2308 sampler->min_img_filter],
2309 VC4_TEX_P1_MINFILT) |
2310 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2311 VC4_TEX_P1_WRAP_S) |
2312 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2313 VC4_TEX_P1_WRAP_T));
2314 }
2315
2316 static void
2317 write_texture_p2(struct vc4_context *vc4,
2318 struct vc4_texture_stateobj *texstate,
2319 uint32_t data)
2320 {
2321 uint32_t unit = data & 0xffff;
2322 struct pipe_sampler_view *texture = texstate->textures[unit];
2323 struct vc4_resource *rsc = vc4_resource(texture->texture);
2324
2325 cl_u32(&vc4->uniforms,
2326 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2327 VC4_TEX_P2_PTYPE) |
2328 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2329 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2330 }
2331
2332
2333 #define SWIZ(x,y,z,w) { \
2334 UTIL_FORMAT_SWIZZLE_##x, \
2335 UTIL_FORMAT_SWIZZLE_##y, \
2336 UTIL_FORMAT_SWIZZLE_##z, \
2337 UTIL_FORMAT_SWIZZLE_##w \
2338 }
2339
2340 static void
2341 write_texture_border_color(struct vc4_context *vc4,
2342 struct vc4_texture_stateobj *texstate,
2343 uint32_t unit)
2344 {
2345 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2346 struct pipe_sampler_view *texture = texstate->textures[unit];
2347 struct vc4_resource *rsc = vc4_resource(texture->texture);
2348 union util_color uc;
2349
2350 const struct util_format_description *tex_format_desc =
2351 util_format_description(texture->format);
2352
2353 float border_color[4];
2354 for (int i = 0; i < 4; i++)
2355 border_color[i] = sampler->border_color.f[i];
2356 if (util_format_is_srgb(texture->format)) {
2357 for (int i = 0; i < 3; i++)
2358 border_color[i] =
2359 util_format_linear_to_srgb_float(border_color[i]);
2360 }
2361
2362 /* Turn the border color into the layout of channels that it would
2363 * have when stored as texture contents.
2364 */
2365 float storage_color[4];
2366 util_format_unswizzle_4f(storage_color,
2367 border_color,
2368 tex_format_desc->swizzle);
2369
2370 /* Now, pack so that when the vc4_format-sampled texture contents are
2371 * replaced with our border color, the vc4_get_format_swizzle()
2372 * swizzling will get the right channels.
2373 */
2374 if (util_format_is_depth_or_stencil(texture->format)) {
2375 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2376 sampler->border_color.f[0]) << 8;
2377 } else {
2378 switch (rsc->vc4_format) {
2379 default:
2380 case VC4_TEXTURE_TYPE_RGBA8888:
2381 util_pack_color(storage_color,
2382 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2383 break;
2384 case VC4_TEXTURE_TYPE_RGBA4444:
2385 util_pack_color(storage_color,
2386 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2387 break;
2388 case VC4_TEXTURE_TYPE_RGB565:
2389 util_pack_color(storage_color,
2390 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2391 break;
2392 case VC4_TEXTURE_TYPE_ALPHA:
2393 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2394 break;
2395 case VC4_TEXTURE_TYPE_LUMALPHA:
2396 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2397 (float_to_ubyte(storage_color[0]) << 0));
2398 break;
2399 }
2400 }
2401
2402 cl_u32(&vc4->uniforms, uc.ui[0]);
2403 }
2404
2405 static uint32_t
2406 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2407 enum quniform_contents contents,
2408 uint32_t data)
2409 {
2410 struct pipe_sampler_view *texture = texstate->textures[data];
2411 uint32_t dim;
2412
2413 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2414 dim = texture->texture->width0;
2415 else
2416 dim = texture->texture->height0;
2417
2418 return fui(1.0f / dim);
2419 }
2420
2421 void
2422 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2423 struct vc4_constbuf_stateobj *cb,
2424 struct vc4_texture_stateobj *texstate)
2425 {
2426 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2427 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2428
2429 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2430
2431 for (int i = 0; i < uinfo->count; i++) {
2432
2433 switch (uinfo->contents[i]) {
2434 case QUNIFORM_CONSTANT:
2435 cl_u32(&vc4->uniforms, uinfo->data[i]);
2436 break;
2437 case QUNIFORM_UNIFORM:
2438 cl_u32(&vc4->uniforms,
2439 gallium_uniforms[uinfo->data[i]]);
2440 break;
2441 case QUNIFORM_VIEWPORT_X_SCALE:
2442 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2443 break;
2444 case QUNIFORM_VIEWPORT_Y_SCALE:
2445 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2446 break;
2447
2448 case QUNIFORM_VIEWPORT_Z_OFFSET:
2449 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);
2450 break;
2451 case QUNIFORM_VIEWPORT_Z_SCALE:
2452 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);
2453 break;
2454
2455 case QUNIFORM_USER_CLIP_PLANE:
2456 cl_f(&vc4->uniforms,
2457 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2458 break;
2459
2460 case QUNIFORM_TEXTURE_CONFIG_P0:
2461 write_texture_p0(vc4, texstate, uinfo->data[i]);
2462 break;
2463
2464 case QUNIFORM_TEXTURE_CONFIG_P1:
2465 write_texture_p1(vc4, texstate, uinfo->data[i]);
2466 break;
2467
2468 case QUNIFORM_TEXTURE_CONFIG_P2:
2469 write_texture_p2(vc4, texstate, uinfo->data[i]);
2470 break;
2471
2472 case QUNIFORM_TEXTURE_BORDER_COLOR:
2473 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2474 break;
2475
2476 case QUNIFORM_TEXRECT_SCALE_X:
2477 case QUNIFORM_TEXRECT_SCALE_Y:
2478 cl_u32(&vc4->uniforms,
2479 get_texrect_scale(texstate,
2480 uinfo->contents[i],
2481 uinfo->data[i]));
2482 break;
2483
2484 case QUNIFORM_BLEND_CONST_COLOR:
2485 cl_f(&vc4->uniforms,
2486 vc4->blend_color.color[uinfo->data[i]]);
2487 break;
2488
2489 case QUNIFORM_STENCIL:
2490 cl_u32(&vc4->uniforms,
2491 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2492 (uinfo->data[i] <= 1 ?
2493 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2494 0));
2495 break;
2496
2497 case QUNIFORM_ALPHA_REF:
2498 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);
2499 break;
2500 }
2501 #if 0
2502 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2503 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2504 shader, i, written_val, uif(written_val));
2505 #endif
2506 }
2507 }
2508
2509 static void
2510 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2511 {
2512 struct vc4_context *vc4 = vc4_context(pctx);
2513 vc4->prog.bind_fs = hwcso;
2514 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;
2515 vc4->dirty |= VC4_DIRTY_PROG;
2516 }
2517
2518 static void
2519 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2520 {
2521 struct vc4_context *vc4 = vc4_context(pctx);
2522 vc4->prog.bind_vs = hwcso;
2523 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;
2524 vc4->dirty |= VC4_DIRTY_PROG;
2525 }
2526
2527 void
2528 vc4_program_init(struct pipe_context *pctx)
2529 {
2530 struct vc4_context *vc4 = vc4_context(pctx);
2531
2532 pctx->create_vs_state = vc4_shader_state_create;
2533 pctx->delete_vs_state = vc4_shader_state_delete;
2534
2535 pctx->create_fs_state = vc4_shader_state_create;
2536 pctx->delete_fs_state = vc4_shader_state_delete;
2537
2538 pctx->bind_fs_state = vc4_fp_state_bind;
2539 pctx->bind_vs_state = vc4_vp_state_bind;
2540
2541 vc4->fs_cache = util_hash_table_create(fs_cache_hash, fs_cache_compare);
2542 vc4->vs_cache = util_hash_table_create(vs_cache_hash, vs_cache_compare);
2543 }