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[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "vc4_qpu.h"
42 #include "kernel/vc4_packet.h"
43 #include "pipe/p_state.h"
44
45 struct nir_builder;
46
47 enum qfile {
48 QFILE_NULL,
49 QFILE_TEMP,
50 QFILE_VARY,
51 QFILE_UNIF,
52 QFILE_VPM,
53 QFILE_TLB_COLOR_WRITE,
54 QFILE_TLB_COLOR_WRITE_MS,
55 QFILE_TLB_Z_WRITE,
56 QFILE_TLB_STENCIL_SETUP,
57
58 /* Payload registers that aren't in the physical register file, so we
59 * can just use the corresponding qpu_reg at qpu_emit time.
60 */
61 QFILE_FRAG_X,
62 QFILE_FRAG_Y,
63 QFILE_FRAG_REV_FLAG,
64
65 /**
66 * Stores an immediate value in the index field that will be used
67 * directly by qpu_load_imm().
68 */
69 QFILE_LOAD_IMM,
70
71 /**
72 * Stores an immediate value in the index field that can be turned
73 * into a small immediate field by qpu_encode_small_immediate().
74 */
75 QFILE_SMALL_IMM,
76 };
77
78 struct qreg {
79 enum qfile file;
80 uint32_t index;
81 int pack;
82 };
83
84 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
85 {
86 return (struct qreg){file, index};
87 }
88
89 enum qop {
90 QOP_UNDEF,
91 QOP_MOV,
92 QOP_FMOV,
93 QOP_MMOV,
94 QOP_FADD,
95 QOP_FSUB,
96 QOP_FMUL,
97 QOP_V8MULD,
98 QOP_V8MIN,
99 QOP_V8MAX,
100 QOP_V8ADDS,
101 QOP_V8SUBS,
102 QOP_MUL24,
103 QOP_FMIN,
104 QOP_FMAX,
105 QOP_FMINABS,
106 QOP_FMAXABS,
107 QOP_ADD,
108 QOP_SUB,
109 QOP_SHL,
110 QOP_SHR,
111 QOP_ASR,
112 QOP_MIN,
113 QOP_MAX,
114 QOP_AND,
115 QOP_OR,
116 QOP_XOR,
117 QOP_NOT,
118
119 QOP_FTOI,
120 QOP_ITOF,
121 QOP_RCP,
122 QOP_RSQ,
123 QOP_EXP2,
124 QOP_LOG2,
125 QOP_VW_SETUP,
126 QOP_VR_SETUP,
127 QOP_TLB_COLOR_READ,
128 QOP_MS_MASK,
129 QOP_VARY_ADD_C,
130
131 QOP_FRAG_Z,
132 QOP_FRAG_W,
133
134 /** Texture x coordinate parameter write */
135 QOP_TEX_S,
136 /** Texture y coordinate parameter write */
137 QOP_TEX_T,
138 /** Texture border color parameter or cube map z coordinate write */
139 QOP_TEX_R,
140 /** Texture LOD bias parameter write */
141 QOP_TEX_B,
142
143 /**
144 * Texture-unit 4-byte read with address provided direct in S
145 * cooordinate.
146 *
147 * The first operand is the offset from the start of the UBO, and the
148 * second is the uniform that has the UBO's base pointer.
149 */
150 QOP_TEX_DIRECT,
151
152 /**
153 * Signal of texture read being necessary and then reading r4 into
154 * the destination
155 */
156 QOP_TEX_RESULT,
157
158 QOP_LOAD_IMM,
159
160 /* Jumps to block->successor[0] if the qinst->cond (as a
161 * QPU_COND_BRANCH_*) passes, or block->successor[1] if not. Note
162 * that block->successor[1] may be unset if the condition is ALWAYS.
163 */
164 QOP_BRANCH,
165 };
166
167 struct queued_qpu_inst {
168 struct list_head link;
169 uint64_t inst;
170 };
171
172 struct qinst {
173 struct list_head link;
174
175 enum qop op;
176 struct qreg dst;
177 struct qreg *src;
178 bool sf;
179 uint8_t cond;
180 };
181
182 enum qstage {
183 /**
184 * Coordinate shader, runs during binning, before the VS, and just
185 * outputs position.
186 */
187 QSTAGE_COORD,
188 QSTAGE_VERT,
189 QSTAGE_FRAG,
190 };
191
192 enum quniform_contents {
193 /**
194 * Indicates that a constant 32-bit value is copied from the program's
195 * uniform contents.
196 */
197 QUNIFORM_CONSTANT,
198 /**
199 * Indicates that the program's uniform contents are used as an index
200 * into the GL uniform storage.
201 */
202 QUNIFORM_UNIFORM,
203
204 /** @{
205 * Scaling factors from clip coordinates to relative to the viewport
206 * center.
207 *
208 * This is used by the coordinate and vertex shaders to produce the
209 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
210 * point offsets from the viewport ccenter.
211 */
212 QUNIFORM_VIEWPORT_X_SCALE,
213 QUNIFORM_VIEWPORT_Y_SCALE,
214 /** @} */
215
216 QUNIFORM_VIEWPORT_Z_OFFSET,
217 QUNIFORM_VIEWPORT_Z_SCALE,
218
219 QUNIFORM_USER_CLIP_PLANE,
220
221 /**
222 * A reference to a texture config parameter 0 uniform.
223 *
224 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
225 * defines texture type, miplevels, and such. It will be found as a
226 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
227 */
228 QUNIFORM_TEXTURE_CONFIG_P0,
229
230 /**
231 * A reference to a texture config parameter 1 uniform.
232 *
233 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
234 * defines texture width, height, filters, and wrap modes. It will be
235 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
236 * sequence.
237 */
238 QUNIFORM_TEXTURE_CONFIG_P1,
239
240 /** A reference to a texture config parameter 2 cubemap stride uniform */
241 QUNIFORM_TEXTURE_CONFIG_P2,
242
243 QUNIFORM_TEXTURE_MSAA_ADDR,
244
245 QUNIFORM_UBO_ADDR,
246
247 QUNIFORM_TEXRECT_SCALE_X,
248 QUNIFORM_TEXRECT_SCALE_Y,
249
250 QUNIFORM_TEXTURE_BORDER_COLOR,
251
252 QUNIFORM_BLEND_CONST_COLOR_X,
253 QUNIFORM_BLEND_CONST_COLOR_Y,
254 QUNIFORM_BLEND_CONST_COLOR_Z,
255 QUNIFORM_BLEND_CONST_COLOR_W,
256 QUNIFORM_BLEND_CONST_COLOR_RGBA,
257 QUNIFORM_BLEND_CONST_COLOR_AAAA,
258
259 QUNIFORM_STENCIL,
260
261 QUNIFORM_ALPHA_REF,
262 QUNIFORM_SAMPLE_MASK,
263 };
264
265 struct vc4_varying_slot {
266 uint8_t slot;
267 uint8_t swizzle;
268 };
269
270 struct vc4_compiler_ubo_range {
271 /**
272 * offset in bytes from the start of the ubo where this range is
273 * uploaded.
274 *
275 * Only set once used is set.
276 */
277 uint32_t dst_offset;
278
279 /**
280 * offset in bytes from the start of the gallium uniforms where the
281 * data comes from.
282 */
283 uint32_t src_offset;
284
285 /** size in bytes of this ubo range */
286 uint32_t size;
287
288 /**
289 * Set if this range is used by the shader for indirect uniforms
290 * access.
291 */
292 bool used;
293 };
294
295 struct vc4_key {
296 struct vc4_uncompiled_shader *shader_state;
297 struct {
298 enum pipe_format format;
299 uint8_t swizzle[4];
300 union {
301 struct {
302 unsigned compare_mode:1;
303 unsigned compare_func:3;
304 unsigned wrap_s:3;
305 unsigned wrap_t:3;
306 };
307 struct {
308 uint16_t msaa_width, msaa_height;
309 };
310 };
311 } tex[VC4_MAX_TEXTURE_SAMPLERS];
312 uint8_t ucp_enables;
313 };
314
315 struct vc4_fs_key {
316 struct vc4_key base;
317 enum pipe_format color_format;
318 bool depth_enabled;
319 bool stencil_enabled;
320 bool stencil_twoside;
321 bool stencil_full_writemasks;
322 bool is_points;
323 bool is_lines;
324 bool alpha_test;
325 bool point_coord_upper_left;
326 bool light_twoside;
327 bool msaa;
328 bool sample_coverage;
329 bool sample_alpha_to_coverage;
330 bool sample_alpha_to_one;
331 uint8_t alpha_test_func;
332 uint8_t logicop_func;
333 uint32_t point_sprite_mask;
334
335 struct pipe_rt_blend_state blend;
336 };
337
338 struct vc4_vs_key {
339 struct vc4_key base;
340
341 /**
342 * This is a proxy for the array of FS input semantics, which is
343 * larger than we would want to put in the key.
344 */
345 uint64_t compiled_fs_id;
346
347 enum pipe_format attr_formats[8];
348 bool is_coord;
349 bool per_vertex_point_size;
350 bool clamp_color;
351 };
352
353 /** A basic block of QIR intructions. */
354 struct qblock {
355 struct list_head link;
356
357 struct list_head instructions;
358
359 struct set *predecessors;
360 struct qblock *successors[2];
361
362 int index;
363
364 /** @{ used by vc4_qir_live_variables.c */
365 BITSET_WORD *def;
366 BITSET_WORD *use;
367 BITSET_WORD *live_in;
368 BITSET_WORD *live_out;
369 int start_ip, end_ip;
370 /** @} */
371 };
372
373 struct vc4_compile {
374 struct vc4_context *vc4;
375 nir_shader *s;
376 nir_function_impl *impl;
377 struct exec_list *cf_node_list;
378
379 /**
380 * Mapping from nir_register * or nir_ssa_def * to array of struct
381 * qreg for the values.
382 */
383 struct hash_table *def_ht;
384
385 /* For each temp, the instruction generating its value. */
386 struct qinst **defs;
387 uint32_t defs_array_size;
388
389 /**
390 * Inputs to the shader, arranged by TGSI declaration order.
391 *
392 * Not all fragment shader QFILE_VARY reads are present in this array.
393 */
394 struct qreg *inputs;
395 struct qreg *outputs;
396 bool msaa_per_sample_output;
397 struct qreg color_reads[VC4_MAX_SAMPLES];
398 struct qreg sample_colors[VC4_MAX_SAMPLES];
399 uint32_t inputs_array_size;
400 uint32_t outputs_array_size;
401 uint32_t uniforms_array_size;
402
403 struct vc4_compiler_ubo_range *ubo_ranges;
404 uint32_t ubo_ranges_array_size;
405 /** Number of uniform areas declared in ubo_ranges. */
406 uint32_t num_uniform_ranges;
407 /** Number of uniform areas used for indirect addressed loads. */
408 uint32_t num_ubo_ranges;
409 uint32_t next_ubo_dst_offset;
410
411 /* State for whether we're executing on each channel currently. 0 if
412 * yes, otherwise a block number + 1 that the channel jumped to.
413 */
414 struct qreg execute;
415
416 struct qreg line_x, point_x, point_y;
417 struct qreg discard;
418 struct qreg payload_FRAG_Z;
419 struct qreg payload_FRAG_W;
420
421 uint8_t vattr_sizes[8];
422
423 /**
424 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
425 *
426 * This includes those that aren't part of the VPM varyings, like
427 * point/line coordinates.
428 */
429 struct vc4_varying_slot *input_slots;
430 uint32_t num_input_slots;
431 uint32_t input_slots_array_size;
432
433 /**
434 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
435 * of the output is. Used to emit from the VS in the order that the
436 * FS needs.
437 */
438 struct vc4_varying_slot *output_slots;
439
440 struct pipe_shader_state *shader_state;
441 struct vc4_key *key;
442 struct vc4_fs_key *fs_key;
443 struct vc4_vs_key *vs_key;
444
445 /* Live ranges of temps. */
446 int *temp_start, *temp_end;
447
448 uint32_t *uniform_data;
449 enum quniform_contents *uniform_contents;
450 uint32_t uniform_array_size;
451 uint32_t num_uniforms;
452 uint32_t num_outputs;
453 uint32_t num_texture_samples;
454 uint32_t output_position_index;
455 uint32_t output_color_index;
456 uint32_t output_point_size_index;
457 uint32_t output_sample_mask_index;
458
459 struct qreg undef;
460 enum qstage stage;
461 uint32_t num_temps;
462
463 struct list_head blocks;
464 int next_block_index;
465 struct qblock *cur_block;
466 struct qblock *loop_cont_block;
467 struct qblock *loop_break_block;
468
469 struct list_head qpu_inst_list;
470 uint64_t *qpu_insts;
471 uint32_t qpu_inst_count;
472 uint32_t qpu_inst_size;
473 uint32_t num_inputs;
474
475 uint32_t program_id;
476 uint32_t variant_id;
477 };
478
479 /* Special nir_load_input intrinsic index for loading the current TLB
480 * destination color.
481 */
482 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
483
484 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
485
486 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
487 * state-dependent value.
488 */
489 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
490
491 struct vc4_compile *qir_compile_init(void);
492 void qir_compile_destroy(struct vc4_compile *c);
493 struct qblock *qir_new_block(struct vc4_compile *c);
494 void qir_set_emit_block(struct vc4_compile *c, struct qblock *block);
495 void qir_link_blocks(struct qblock *predecessor, struct qblock *successor);
496 struct qblock *qir_entry_block(struct vc4_compile *c);
497 struct qblock *qir_exit_block(struct vc4_compile *c);
498 struct qinst *qir_inst(enum qop op, struct qreg dst,
499 struct qreg src0, struct qreg src1);
500 struct qinst *qir_inst4(enum qop op, struct qreg dst,
501 struct qreg a,
502 struct qreg b,
503 struct qreg c,
504 struct qreg d);
505 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
506 struct qreg qir_uniform(struct vc4_compile *c,
507 enum quniform_contents contents,
508 uint32_t data);
509 void qir_schedule_instructions(struct vc4_compile *c);
510 void qir_reorder_uniforms(struct vc4_compile *c);
511
512 struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
513 struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
514
515 struct qreg qir_get_temp(struct vc4_compile *c);
516 void qir_calculate_live_intervals(struct vc4_compile *c);
517 int qir_get_op_nsrc(enum qop qop);
518 bool qir_reg_equals(struct qreg a, struct qreg b);
519 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
520 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
521 bool qir_is_mul(struct qinst *inst);
522 bool qir_is_raw_mov(struct qinst *inst);
523 bool qir_is_tex(struct qinst *inst);
524 bool qir_is_float_input(struct qinst *inst);
525 bool qir_depends_on_flags(struct qinst *inst);
526 bool qir_writes_r4(struct qinst *inst);
527 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
528 uint8_t qir_channels_written(struct qinst *inst);
529
530 void qir_dump(struct vc4_compile *c);
531 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
532 const char *qir_get_stage_name(enum qstage stage);
533
534 void qir_validate(struct vc4_compile *c);
535
536 void qir_optimize(struct vc4_compile *c);
537 bool qir_opt_algebraic(struct vc4_compile *c);
538 bool qir_opt_constant_folding(struct vc4_compile *c);
539 bool qir_opt_copy_propagation(struct vc4_compile *c);
540 bool qir_opt_dead_code(struct vc4_compile *c);
541 bool qir_opt_peephole_sf(struct vc4_compile *c);
542 bool qir_opt_small_immediates(struct vc4_compile *c);
543 bool qir_opt_vpm(struct vc4_compile *c);
544 void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
545 void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
546 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
547 enum quniform_contents contents);
548 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
549 nir_ssa_def **srcs, int swiz);
550 void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
551 void qir_lower_uniforms(struct vc4_compile *c);
552
553 uint32_t qpu_schedule_instructions(struct vc4_compile *c);
554
555 void qir_SF(struct vc4_compile *c, struct qreg src);
556
557 static inline struct qreg
558 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
559 {
560 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
561 }
562
563 static inline struct qreg
564 qir_uniform_f(struct vc4_compile *c, float f)
565 {
566 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
567 }
568
569 #define QIR_ALU0(name) \
570 static inline struct qreg \
571 qir_##name(struct vc4_compile *c) \
572 { \
573 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
574 c->undef, c->undef)); \
575 } \
576 static inline struct qinst * \
577 qir_##name##_dest(struct vc4_compile *c, struct qreg dest) \
578 { \
579 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, \
580 c->undef, c->undef)); \
581 }
582
583 #define QIR_ALU1(name) \
584 static inline struct qreg \
585 qir_##name(struct vc4_compile *c, struct qreg a) \
586 { \
587 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, \
588 a, c->undef)); \
589 } \
590 static inline struct qinst * \
591 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
592 struct qreg a) \
593 { \
594 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, \
595 c->undef)); \
596 }
597
598 #define QIR_ALU2(name) \
599 static inline struct qreg \
600 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
601 { \
602 return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b)); \
603 } \
604 static inline struct qinst * \
605 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
606 struct qreg a, struct qreg b) \
607 { \
608 return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b)); \
609 }
610
611 #define QIR_NODST_1(name) \
612 static inline struct qinst * \
613 qir_##name(struct vc4_compile *c, struct qreg a) \
614 { \
615 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
616 a, c->undef)); \
617 }
618
619 #define QIR_NODST_2(name) \
620 static inline struct qinst * \
621 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
622 { \
623 return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef, \
624 a, b)); \
625 }
626
627 #define QIR_PAYLOAD(name) \
628 static inline struct qreg \
629 qir_##name(struct vc4_compile *c) \
630 { \
631 struct qreg *payload = &c->payload_##name; \
632 if (payload->file != QFILE_NULL) \
633 return *payload; \
634 *payload = qir_get_temp(c); \
635 struct qinst *inst = qir_inst(QOP_##name, *payload, \
636 c->undef, c->undef); \
637 struct qblock *entry = qir_entry_block(c); \
638 list_add(&inst->link, &entry->instructions); \
639 c->defs[payload->index] = inst; \
640 return *payload; \
641 }
642
643 QIR_ALU1(MOV)
644 QIR_ALU1(FMOV)
645 QIR_ALU1(MMOV)
646 QIR_ALU2(FADD)
647 QIR_ALU2(FSUB)
648 QIR_ALU2(FMUL)
649 QIR_ALU2(V8MULD)
650 QIR_ALU2(V8MIN)
651 QIR_ALU2(V8MAX)
652 QIR_ALU2(V8ADDS)
653 QIR_ALU2(V8SUBS)
654 QIR_ALU2(MUL24)
655 QIR_ALU2(FMIN)
656 QIR_ALU2(FMAX)
657 QIR_ALU2(FMINABS)
658 QIR_ALU2(FMAXABS)
659 QIR_ALU1(FTOI)
660 QIR_ALU1(ITOF)
661
662 QIR_ALU2(ADD)
663 QIR_ALU2(SUB)
664 QIR_ALU2(SHL)
665 QIR_ALU2(SHR)
666 QIR_ALU2(ASR)
667 QIR_ALU2(MIN)
668 QIR_ALU2(MAX)
669 QIR_ALU2(AND)
670 QIR_ALU2(OR)
671 QIR_ALU2(XOR)
672 QIR_ALU1(NOT)
673
674 QIR_ALU1(RCP)
675 QIR_ALU1(RSQ)
676 QIR_ALU1(EXP2)
677 QIR_ALU1(LOG2)
678 QIR_ALU1(VARY_ADD_C)
679 QIR_NODST_2(TEX_S)
680 QIR_NODST_2(TEX_T)
681 QIR_NODST_2(TEX_R)
682 QIR_NODST_2(TEX_B)
683 QIR_NODST_2(TEX_DIRECT)
684 QIR_PAYLOAD(FRAG_Z)
685 QIR_PAYLOAD(FRAG_W)
686 QIR_ALU0(TEX_RESULT)
687 QIR_ALU0(TLB_COLOR_READ)
688 QIR_NODST_1(MS_MASK)
689
690 static inline struct qreg
691 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
692 {
693 struct qreg t = qir_get_temp(c);
694 struct qinst *a = qir_MOV_dest(c, t, src0);
695 struct qinst *b = qir_MOV_dest(c, t, src1);
696 a->cond = cond;
697 b->cond = qpu_cond_complement(cond);
698 return t;
699 }
700
701 static inline struct qreg
702 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
703 {
704 struct qreg t = qir_FMOV(c, src);
705 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
706 return t;
707 }
708
709 static inline struct qreg
710 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
711 {
712 struct qreg t = qir_MOV(c, src);
713 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
714 return t;
715 }
716
717 static inline struct qreg
718 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
719 {
720 struct qreg t = qir_FMOV(c, src);
721 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
722 return t;
723 }
724
725 static inline struct qreg
726 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
727 {
728 struct qreg t = qir_MOV(c, src);
729 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
730 return t;
731 }
732
733 static inline void
734 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
735 {
736 assert(!dest.pack);
737 dest.pack = QPU_PACK_MUL_8A + chan;
738 qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef));
739 }
740
741 static inline struct qreg
742 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
743 {
744 struct qreg dest = qir_MMOV(c, val);
745 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
746 return dest;
747 }
748
749 static inline struct qreg
750 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
751 {
752 return qir_EXP2(c, qir_FMUL(c,
753 y,
754 qir_LOG2(c, x)));
755 }
756
757 static inline void
758 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
759 {
760 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
761 }
762
763 static inline struct qreg
764 qir_LOAD_IMM(struct vc4_compile *c, uint32_t val)
765 {
766 return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef,
767 qir_reg(QFILE_LOAD_IMM, val), c->undef));
768 }
769
770 static inline void
771 qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
772 struct qreg dest, struct qreg src)
773 {
774 qir_MOV_dest(c, dest, src)->cond = cond;
775 }
776
777 static inline struct qinst *
778 qir_BRANCH(struct vc4_compile *c, uint8_t cond)
779 {
780 struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef);
781 inst->cond = cond;
782 qir_emit_nondef(c, inst);
783 return inst;
784 }
785
786 #define qir_for_each_block(block, c) \
787 list_for_each_entry(struct qblock, block, &c->blocks, link)
788
789 #define qir_for_each_block_rev(block, c) \
790 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
791
792 /* Loop over the non-NULL members of the successors array. */
793 #define qir_for_each_successor(succ, block) \
794 for (struct qblock *succ = block->successors[0]; \
795 succ != NULL; \
796 succ = (succ == block->successors[1] ? NULL : \
797 block->successors[1]))
798
799 #define qir_for_each_inst(inst, block) \
800 list_for_each_entry(struct qinst, inst, &block->instructions, link)
801
802 #define qir_for_each_inst_rev(inst, block) \
803 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
804
805 #define qir_for_each_inst_safe(inst, block) \
806 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
807
808 #define qir_for_each_inst_inorder(inst, c) \
809 qir_for_each_block(_block, c) \
810 qir_for_each_inst(inst, _block)
811
812 #endif /* VC4_QIR_H */