src/gallium/drivers/vc4/vc4_qir.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef VC4_QIR_H
  25 #define VC4_QIR_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "compiler/nir/nir.h"
  36 #include "util/list.h"
  37 #include "util/u_math.h"
  38
  39 #include "vc4_screen.h"
  40 #include "vc4_qpu_defines.h"
  41 #include "vc4_qpu.h"
  42 #include "kernel/vc4_packet.h"
  43 #include "pipe/p_state.h"
  44
  45 struct nir_builder;
  46
  47 enum qfile {
  48         QFILE_NULL,
  49         QFILE_TEMP,
  50         QFILE_VARY,
  51         QFILE_UNIF,
  52         QFILE_VPM,
  53         QFILE_TLB_COLOR_WRITE,
  54         QFILE_TLB_COLOR_WRITE_MS,
  55         QFILE_TLB_Z_WRITE,
  56         QFILE_TLB_STENCIL_SETUP,
  57
  58         /* If tex_s is written on its own without preceding t/r/b setup, it's
  59          * a direct memory access using the input value, without the sideband
  60          * uniform load.  We represent these in QIR as a separate write
  61          * destination so we can tell if the sideband uniform is present.
  62          */
  63         QFILE_TEX_S_DIRECT,
  64
  65         QFILE_TEX_S,
  66         QFILE_TEX_T,
  67         QFILE_TEX_R,
  68         QFILE_TEX_B,
  69
  70         /* Payload registers that aren't in the physical register file, so we
  71          * can just use the corresponding qpu_reg at qpu_emit time.
  72          */
  73         QFILE_FRAG_X,
  74         QFILE_FRAG_Y,
  75         QFILE_FRAG_REV_FLAG,
  76         QFILE_QPU_ELEMENT,
  77
  78         /**
  79          * Stores an immediate value in the index field that will be used
  80          * directly by qpu_load_imm().
  81          */
  82         QFILE_LOAD_IMM,
  83
  84         /**
  85          * Stores an immediate value in the index field that can be turned
  86          * into a small immediate field by qpu_encode_small_immediate().
  87          */
  88         QFILE_SMALL_IMM,
  89 };
  90
  91 struct qreg {
  92         enum qfile file;
  93         uint32_t index;
  94         int pack;
  95 };
  96
  97 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
  98 {
  99         return (struct qreg){file, index};
 100 }
 101
 102 enum qop {
 103         QOP_UNDEF,
 104         QOP_MOV,
 105         QOP_FMOV,
 106         QOP_MMOV,
 107         QOP_FADD,
 108         QOP_FSUB,
 109         QOP_FMUL,
 110         QOP_V8MULD,
 111         QOP_V8MIN,
 112         QOP_V8MAX,
 113         QOP_V8ADDS,
 114         QOP_V8SUBS,
 115         QOP_MUL24,
 116         QOP_FMIN,
 117         QOP_FMAX,
 118         QOP_FMINABS,
 119         QOP_FMAXABS,
 120         QOP_ADD,
 121         QOP_SUB,
 122         QOP_SHL,
 123         QOP_SHR,
 124         QOP_ASR,
 125         QOP_MIN,
 126         QOP_MIN_NOIMM,
 127         QOP_MAX,
 128         QOP_AND,
 129         QOP_OR,
 130         QOP_XOR,
 131         QOP_NOT,
 132
 133         QOP_FTOI,
 134         QOP_ITOF,
 135         QOP_RCP,
 136         QOP_RSQ,
 137         QOP_EXP2,
 138         QOP_LOG2,
 139         QOP_VW_SETUP,
 140         QOP_VR_SETUP,
 141         QOP_TLB_COLOR_READ,
 142         QOP_MS_MASK,
 143         QOP_VARY_ADD_C,
 144
 145         QOP_FRAG_Z,
 146         QOP_FRAG_W,
 147
 148         /**
 149          * Signal of texture read being necessary and then reading r4 into
 150          * the destination
 151          */
 152         QOP_TEX_RESULT,
 153
 154         /**
 155          * Insert the signal for switching threads in a threaded fragment
 156          * shader.  No value can be live in an accumulator across a thrsw.
 157          *
 158          * At the QPU level, this will have several delay slots before the
 159          * switch happens.  Those slots are the responsibility of the
 160          * scheduler.
 161          */
 162         QOP_THRSW,
 163
 164         /* 32-bit immediate loaded to each SIMD channel */
 165         QOP_LOAD_IMM,
 166
 167         /* 32-bit immediate divided into 16 2-bit unsigned int values and
 168          * loaded to each corresponding SIMD channel.
 169          */
 170         QOP_LOAD_IMM_U2,
 171         /* 32-bit immediate divided into 16 2-bit signed int values and
 172          * loaded to each corresponding SIMD channel.
 173          */
 174         QOP_LOAD_IMM_I2,
 175
 176         QOP_ROT_MUL,
 177
 178         /* Jumps to block->successor[0] if the qinst->cond (as a
 179          * QPU_COND_BRANCH_*) passes, or block->successor[1] if not.  Note
 180          * that block->successor[1] may be unset if the condition is ALWAYS.
 181          */
 182         QOP_BRANCH,
 183
 184         /* Emits an ADD from src[0] to src[1], where src[0] must be a
 185          * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
 186          * required by the kernel as part of its branch validation.
 187          */
 188         QOP_UNIFORMS_RESET,
 189 };
 190
 191 struct queued_qpu_inst {
 192         struct list_head link;
 193         uint64_t inst;
 194 };
 195
 196 struct qinst {
 197         struct list_head link;
 198
 199         enum qop op;
 200         struct qreg dst;
 201         struct qreg src[3];
 202         bool sf;
 203         bool cond_is_exec_mask;
 204         uint8_t cond;
 205 };
 206
 207 enum qstage {
 208         /**
 209          * Coordinate shader, runs during binning, before the VS, and just
 210          * outputs position.
 211          */
 212         QSTAGE_COORD,
 213         QSTAGE_VERT,
 214         QSTAGE_FRAG,
 215 };
 216
 217 enum quniform_contents {
 218         /**
 219          * Indicates that a constant 32-bit value is copied from the program's
 220          * uniform contents.
 221          */
 222         QUNIFORM_CONSTANT,
 223         /**
 224          * Indicates that the program's uniform contents are used as an index
 225          * into the GL uniform storage.
 226          */
 227         QUNIFORM_UNIFORM,
 228
 229         /** @{
 230          * Scaling factors from clip coordinates to relative to the viewport
 231          * center.
 232          *
 233          * This is used by the coordinate and vertex shaders to produce the
 234          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 235          * point offsets from the viewport ccenter.
 236          */
 237         QUNIFORM_VIEWPORT_X_SCALE,
 238         QUNIFORM_VIEWPORT_Y_SCALE,
 239         /** @} */
 240
 241         QUNIFORM_VIEWPORT_Z_OFFSET,
 242         QUNIFORM_VIEWPORT_Z_SCALE,
 243
 244         QUNIFORM_USER_CLIP_PLANE,
 245
 246         /**
 247          * A reference to a texture config parameter 0 uniform.
 248          *
 249          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 250          * defines texture type, miplevels, and such.  It will be found as a
 251          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 252          */
 253         QUNIFORM_TEXTURE_CONFIG_P0,
 254
 255         /**
 256          * A reference to a texture config parameter 1 uniform.
 257          *
 258          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 259          * defines texture width, height, filters, and wrap modes.  It will be
 260          * found as a parameter to the second QOP_TEX_[STRB] instruction in a
 261          * sequence.
 262          */
 263         QUNIFORM_TEXTURE_CONFIG_P1,
 264
 265         /** A reference to a texture config parameter 2 cubemap stride uniform */
 266         QUNIFORM_TEXTURE_CONFIG_P2,
 267
 268         QUNIFORM_TEXTURE_FIRST_LEVEL,
 269
 270         QUNIFORM_TEXTURE_MSAA_ADDR,
 271
 272         QUNIFORM_UBO_ADDR,
 273
 274         QUNIFORM_TEXRECT_SCALE_X,
 275         QUNIFORM_TEXRECT_SCALE_Y,
 276
 277         QUNIFORM_TEXTURE_BORDER_COLOR,
 278
 279         QUNIFORM_BLEND_CONST_COLOR_X,
 280         QUNIFORM_BLEND_CONST_COLOR_Y,
 281         QUNIFORM_BLEND_CONST_COLOR_Z,
 282         QUNIFORM_BLEND_CONST_COLOR_W,
 283         QUNIFORM_BLEND_CONST_COLOR_RGBA,
 284         QUNIFORM_BLEND_CONST_COLOR_AAAA,
 285
 286         QUNIFORM_STENCIL,
 287
 288         QUNIFORM_ALPHA_REF,
 289         QUNIFORM_SAMPLE_MASK,
 290
 291         /* Placeholder uniform that will be updated by the kernel when used by
 292          * an instruction writing to QPU_W_UNIFORMS_ADDRESS.
 293          */
 294         QUNIFORM_UNIFORMS_ADDRESS,
 295 };
 296
 297 struct vc4_varying_slot {
 298         uint8_t slot;
 299         uint8_t swizzle;
 300 };
 301
 302 struct vc4_compiler_ubo_range {
 303         /**
 304          * offset in bytes from the start of the ubo where this range is
 305          * uploaded.
 306          *
 307          * Only set once used is set.
 308          */
 309         uint32_t dst_offset;
 310
 311         /**
 312          * offset in bytes from the start of the gallium uniforms where the
 313          * data comes from.
 314          */
 315         uint32_t src_offset;
 316
 317         /** size in bytes of this ubo range */
 318         uint32_t size;
 319
 320         /**
 321          * Set if this range is used by the shader for indirect uniforms
 322          * access.
 323          */
 324         bool used;
 325 };
 326
 327 struct vc4_key {
 328         struct vc4_uncompiled_shader *shader_state;
 329         struct {
 330                 enum pipe_format format;
 331                 uint8_t swizzle[4];
 332                 union {
 333                         struct {
 334                                 unsigned compare_mode:1;
 335                                 unsigned compare_func:3;
 336                                 unsigned wrap_s:3;
 337                                 unsigned wrap_t:3;
 338                                 bool force_first_level:1;
 339                         };
 340                         struct {
 341                                 uint16_t msaa_width, msaa_height;
 342                         };
 343                 };
 344         } tex[VC4_MAX_TEXTURE_SAMPLERS];
 345         uint8_t ucp_enables;
 346 };
 347
 348 struct vc4_fs_key {
 349         struct vc4_key base;
 350         enum pipe_format color_format;
 351         bool depth_enabled;
 352         bool stencil_enabled;
 353         bool stencil_twoside;
 354         bool stencil_full_writemasks;
 355         bool is_points;
 356         bool is_lines;
 357         bool alpha_test;
 358         bool point_coord_upper_left;
 359         bool light_twoside;
 360         bool msaa;
 361         bool sample_coverage;
 362         bool sample_alpha_to_coverage;
 363         bool sample_alpha_to_one;
 364         uint8_t alpha_test_func;
 365         uint8_t logicop_func;
 366         uint32_t point_sprite_mask;
 367
 368         struct pipe_rt_blend_state blend;
 369 };
 370
 371 struct vc4_vs_key {
 372         struct vc4_key base;
 373
 374         const struct vc4_fs_inputs *fs_inputs;
 375         enum pipe_format attr_formats[8];
 376         bool is_coord;
 377         bool per_vertex_point_size;
 378         bool clamp_color;
 379 };
 380
 381 /** A basic block of QIR intructions. */
 382 struct qblock {
 383         struct list_head link;
 384
 385         struct list_head instructions;
 386         struct list_head qpu_inst_list;
 387
 388         struct set *predecessors;
 389         struct qblock *successors[2];
 390
 391         int index;
 392
 393         /* Instruction IPs for the first and last instruction of the block.
 394          * Set by vc4_qpu_schedule.c.
 395          */
 396         uint32_t start_qpu_ip;
 397         uint32_t end_qpu_ip;
 398
 399         /* Instruction IP for the branch instruction of the block.  Set by
 400          * vc4_qpu_schedule.c.
 401          */
 402         uint32_t branch_qpu_ip;
 403
 404         /** @{ used by vc4_qir_live_variables.c */
 405         BITSET_WORD *def;
 406         BITSET_WORD *use;
 407         BITSET_WORD *live_in;
 408         BITSET_WORD *live_out;
 409         int start_ip, end_ip;
 410         /** @} */
 411 };
 412
 413 struct vc4_compile {
 414         struct vc4_context *vc4;
 415         nir_shader *s;
 416         nir_function_impl *impl;
 417         struct exec_list *cf_node_list;
 418
 419         /**
 420          * Mapping from nir_register * or nir_ssa_def * to array of struct
 421          * qreg for the values.
 422          */
 423         struct hash_table *def_ht;
 424
 425         /* For each temp, the instruction generating its value. */
 426         struct qinst **defs;
 427         uint32_t defs_array_size;
 428
 429         /**
 430          * Inputs to the shader, arranged by TGSI declaration order.
 431          *
 432          * Not all fragment shader QFILE_VARY reads are present in this array.
 433          */
 434         struct qreg *inputs;
 435         struct qreg *outputs;
 436         bool msaa_per_sample_output;
 437         struct qreg color_reads[VC4_MAX_SAMPLES];
 438         struct qreg sample_colors[VC4_MAX_SAMPLES];
 439         uint32_t inputs_array_size;
 440         uint32_t outputs_array_size;
 441         uint32_t uniforms_array_size;
 442
 443         struct vc4_compiler_ubo_range *ubo_ranges;
 444         uint32_t ubo_ranges_array_size;
 445         /** Number of uniform areas declared in ubo_ranges. */
 446         uint32_t num_uniform_ranges;
 447         /** Number of uniform areas used for indirect addressed loads. */
 448         uint32_t num_ubo_ranges;
 449         uint32_t next_ubo_dst_offset;
 450
 451         /* State for whether we're executing on each channel currently.  0 if
 452          * yes, otherwise a block number + 1 that the channel jumped to.
 453          */
 454         struct qreg execute;
 455
 456         struct qreg line_x, point_x, point_y;
 457         /** boolean (~0 -> true) if the fragment has been discarded. */
 458         struct qreg discard;
 459         struct qreg payload_FRAG_Z;
 460         struct qreg payload_FRAG_W;
 461
 462         uint8_t vattr_sizes[8];
 463
 464         /**
 465          * Order in which the vattrs were loaded by the program, to arrange
 466          * vattr_offsets[] in the program data appropriately.
 467          */
 468         uint8_t vpm_input_order[8];
 469         uint8_t next_vpm_input;
 470
 471         /**
 472          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 473          *
 474          * This includes those that aren't part of the VPM varyings, like
 475          * point/line coordinates.
 476          */
 477         struct vc4_varying_slot *input_slots;
 478         uint32_t num_input_slots;
 479         uint32_t input_slots_array_size;
 480
 481         /**
 482          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 483          * of the output is.  Used to emit from the VS in the order that the
 484          * FS needs.
 485          */
 486         struct vc4_varying_slot *output_slots;
 487
 488         struct pipe_shader_state *shader_state;
 489         struct vc4_key *key;
 490         struct vc4_fs_key *fs_key;
 491         struct vc4_vs_key *vs_key;
 492
 493         /* Live ranges of temps. */
 494         int *temp_start, *temp_end;
 495
 496         uint32_t *uniform_data;
 497         enum quniform_contents *uniform_contents;
 498         uint32_t uniform_array_size;
 499         uint32_t num_uniforms;
 500         uint32_t num_outputs;
 501         uint32_t num_texture_samples;
 502         uint32_t output_position_index;
 503         uint32_t output_color_index;
 504         uint32_t output_point_size_index;
 505         uint32_t output_sample_mask_index;
 506
 507         struct qreg undef;
 508         enum qstage stage;
 509         uint32_t num_temps;
 510
 511         struct list_head blocks;
 512         int next_block_index;
 513         struct qblock *cur_block;
 514         struct qblock *loop_cont_block;
 515         struct qblock *loop_break_block;
 516         struct qblock *last_top_block;
 517
 518         struct list_head qpu_inst_list;
 519
 520         /* Pre-QPU-scheduled instruction containing the last THRSW */
 521         uint64_t *last_thrsw;
 522
 523         uint64_t *qpu_insts;
 524         uint32_t qpu_inst_count;
 525         uint32_t qpu_inst_size;
 526         uint32_t num_inputs;
 527
 528         /**
 529          * Number of inputs from num_inputs remaining to be queued to the read
 530          * FIFO in the VS/CS.
 531          */
 532         uint32_t num_inputs_remaining;
 533
 534         /* Number of inputs currently in the read FIFO for the VS/CS */
 535         uint32_t num_inputs_in_fifo;
 536
 537         /** Next offset in the VPM to read from in the VS/CS */
 538         uint32_t vpm_read_offset;
 539
 540         uint32_t program_id;
 541         uint32_t variant_id;
 542
 543         /* Set to compile program in threaded FS mode, where SIG_THREAD_SWITCH
 544          * is used to hide texturing latency at the cost of limiting ourselves
 545          * to the bottom half of physical reg space.
 546          */
 547         bool fs_threaded;
 548
 549         bool last_thrsw_at_top_level;
 550
 551         bool failed;
 552 };
 553
 554 /* Special nir_load_input intrinsic index for loading the current TLB
 555  * destination color.
 556  */
 557 #define VC4_NIR_TLB_COLOR_READ_INPUT            2000000000
 558
 559 #define VC4_NIR_MS_MASK_OUTPUT                  2000000000
 560
 561 struct vc4_compile *qir_compile_init(void);
 562 void qir_compile_destroy(struct vc4_compile *c);
 563 struct qblock *qir_new_block(struct vc4_compile *c);
 564 void qir_set_emit_block(struct vc4_compile *c, struct qblock *block);
 565 void qir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 566 struct qblock *qir_entry_block(struct vc4_compile *c);
 567 struct qblock *qir_exit_block(struct vc4_compile *c);
 568 struct qinst *qir_inst(enum qop op, struct qreg dst,
 569                        struct qreg src0, struct qreg src1);
 570 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
 571 struct qreg qir_uniform(struct vc4_compile *c,
 572                         enum quniform_contents contents,
 573                         uint32_t data);
 574 void qir_schedule_instructions(struct vc4_compile *c);
 575 void qir_reorder_uniforms(struct vc4_compile *c);
 576 void qir_emit_uniform_stream_resets(struct vc4_compile *c);
 577
 578 struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
 579 struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
 580
 581 struct qreg qir_get_temp(struct vc4_compile *c);
 582 void qir_calculate_live_intervals(struct vc4_compile *c);
 583 int qir_get_nsrc(struct qinst *inst);
 584 int qir_get_non_sideband_nsrc(struct qinst *inst);
 585 int qir_get_tex_uniform_src(struct qinst *inst);
 586 bool qir_reg_equals(struct qreg a, struct qreg b);
 587 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
 588 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
 589 bool qir_has_uniform_read(struct qinst *inst);
 590 bool qir_is_mul(struct qinst *inst);
 591 bool qir_is_raw_mov(struct qinst *inst);
 592 bool qir_is_tex(struct qinst *inst);
 593 bool qir_has_implicit_tex_uniform(struct qinst *inst);
 594 bool qir_is_float_input(struct qinst *inst);
 595 bool qir_depends_on_flags(struct qinst *inst);
 596 bool qir_writes_r4(struct qinst *inst);
 597 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
 598 uint8_t qir_channels_written(struct qinst *inst);
 599
 600 void qir_dump(struct vc4_compile *c);
 601 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
 602 const char *qir_get_stage_name(enum qstage stage);
 603
 604 void qir_validate(struct vc4_compile *c);
 605
 606 void qir_optimize(struct vc4_compile *c);
 607 bool qir_opt_algebraic(struct vc4_compile *c);
 608 bool qir_opt_coalesce_ff_writes(struct vc4_compile *c);
 609 bool qir_opt_constant_folding(struct vc4_compile *c);
 610 bool qir_opt_copy_propagation(struct vc4_compile *c);
 611 bool qir_opt_dead_code(struct vc4_compile *c);
 612 bool qir_opt_peephole_sf(struct vc4_compile *c);
 613 bool qir_opt_small_immediates(struct vc4_compile *c);
 614 bool qir_opt_vpm(struct vc4_compile *c);
 615 void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
 616 void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
 617 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
 618                                           nir_ssa_def **srcs, int swiz);
 619 void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
 620 void qir_lower_uniforms(struct vc4_compile *c);
 621
 622 uint32_t qpu_schedule_instructions(struct vc4_compile *c);
 623
 624 void qir_SF(struct vc4_compile *c, struct qreg src);
 625
 626 static inline struct qreg
 627 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
 628 {
 629         return qir_uniform(c, QUNIFORM_CONSTANT, ui);
 630 }
 631
 632 static inline struct qreg
 633 qir_uniform_f(struct vc4_compile *c, float f)
 634 {
 635         return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 636 }
 637
 638 #define QIR_ALU0(name)                                                   \
 639 static inline struct qreg                                                \
 640 qir_##name(struct vc4_compile *c)                                        \
 641 {                                                                        \
 642         return qir_emit_def(c, qir_inst(QOP_##name, c->undef,            \
 643                                         c->undef, c->undef));            \
 644 }                                                                        \
 645 static inline struct qinst *                                             \
 646 qir_##name##_dest(struct vc4_compile *c, struct qreg dest)               \
 647 {                                                                        \
 648         return qir_emit_nondef(c, qir_inst(QOP_##name, dest,             \
 649                                            c->undef, c->undef));         \
 650 }
 651
 652 #define QIR_ALU1(name)                                                   \
 653 static inline struct qreg                                                \
 654 qir_##name(struct vc4_compile *c, struct qreg a)                         \
 655 {                                                                        \
 656         return qir_emit_def(c, qir_inst(QOP_##name, c->undef,            \
 657                                         a, c->undef));                   \
 658 }                                                                        \
 659 static inline struct qinst *                                             \
 660 qir_##name##_dest(struct vc4_compile *c, struct qreg dest,               \
 661                   struct qreg a)                                         \
 662 {                                                                        \
 663         return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a,          \
 664                                            c->undef));                   \
 665 }
 666
 667 #define QIR_ALU2(name)                                                   \
 668 static inline struct qreg                                                \
 669 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b)          \
 670 {                                                                        \
 671         return qir_emit_def(c, qir_inst(QOP_##name, c->undef, a, b));    \
 672 }                                                                        \
 673 static inline struct qinst *                                             \
 674 qir_##name##_dest(struct vc4_compile *c, struct qreg dest,               \
 675                   struct qreg a, struct qreg b)                          \
 676 {                                                                        \
 677         return qir_emit_nondef(c, qir_inst(QOP_##name, dest, a, b));     \
 678 }
 679
 680 #define QIR_NODST_1(name)                                               \
 681 static inline struct qinst *                                            \
 682 qir_##name(struct vc4_compile *c, struct qreg a)                        \
 683 {                                                                       \
 684         return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef,        \
 685                                            a, c->undef));               \
 686 }
 687
 688 #define QIR_NODST_2(name)                                               \
 689 static inline struct qinst *                                            \
 690 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b)         \
 691 {                                                                       \
 692         return qir_emit_nondef(c, qir_inst(QOP_##name, c->undef,        \
 693                                            a, b));                      \
 694 }
 695
 696 #define QIR_PAYLOAD(name)                                                \
 697 static inline struct qreg                                                \
 698 qir_##name(struct vc4_compile *c)                                        \
 699 {                                                                        \
 700         struct qreg *payload = &c->payload_##name;                       \
 701         if (payload->file != QFILE_NULL)                                 \
 702                 return *payload;                                         \
 703         *payload = qir_get_temp(c);                                      \
 704         struct qinst *inst = qir_inst(QOP_##name, *payload,              \
 705                                       c->undef, c->undef);               \
 706         struct qblock *entry = qir_entry_block(c);                       \
 707         list_add(&inst->link, &entry->instructions);                     \
 708         c->defs[payload->index] = inst;                                  \
 709         return *payload;                                                 \
 710 }
 711
 712 QIR_ALU1(MOV)
 713 QIR_ALU1(FMOV)
 714 QIR_ALU1(MMOV)
 715 QIR_ALU2(FADD)
 716 QIR_ALU2(FSUB)
 717 QIR_ALU2(FMUL)
 718 QIR_ALU2(V8MULD)
 719 QIR_ALU2(V8MIN)
 720 QIR_ALU2(V8MAX)
 721 QIR_ALU2(V8ADDS)
 722 QIR_ALU2(V8SUBS)
 723 QIR_ALU2(MUL24)
 724 QIR_ALU2(FMIN)
 725 QIR_ALU2(FMAX)
 726 QIR_ALU2(FMINABS)
 727 QIR_ALU2(FMAXABS)
 728 QIR_ALU1(FTOI)
 729 QIR_ALU1(ITOF)
 730
 731 QIR_ALU2(ADD)
 732 QIR_ALU2(SUB)
 733 QIR_ALU2(SHL)
 734 QIR_ALU2(SHR)
 735 QIR_ALU2(ASR)
 736 QIR_ALU2(MIN)
 737 QIR_ALU2(MIN_NOIMM)
 738 QIR_ALU2(MAX)
 739 QIR_ALU2(AND)
 740 QIR_ALU2(OR)
 741 QIR_ALU2(XOR)
 742 QIR_ALU1(NOT)
 743
 744 QIR_ALU1(RCP)
 745 QIR_ALU1(RSQ)
 746 QIR_ALU1(EXP2)
 747 QIR_ALU1(LOG2)
 748 QIR_ALU1(VARY_ADD_C)
 749 QIR_PAYLOAD(FRAG_Z)
 750 QIR_PAYLOAD(FRAG_W)
 751 QIR_ALU0(TEX_RESULT)
 752 QIR_ALU0(TLB_COLOR_READ)
 753 QIR_NODST_1(MS_MASK)
 754
 755 static inline struct qreg
 756 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
 757 {
 758         struct qreg t = qir_get_temp(c);
 759         qir_MOV_dest(c, t, src1);
 760         qir_MOV_dest(c, t, src0)->cond = cond;
 761         return t;
 762 }
 763
 764 static inline struct qreg
 765 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
 766 {
 767         struct qreg t = qir_FMOV(c, src);
 768         c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
 769         return t;
 770 }
 771
 772 static inline struct qreg
 773 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
 774 {
 775         struct qreg t = qir_MOV(c, src);
 776         c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
 777         return t;
 778 }
 779
 780 static inline struct qreg
 781 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
 782 {
 783         struct qreg t = qir_FMOV(c, src);
 784         c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
 785         return t;
 786 }
 787
 788 static inline struct qreg
 789 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
 790 {
 791         struct qreg t = qir_MOV(c, src);
 792         c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
 793         return t;
 794 }
 795
 796 static inline void
 797 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
 798 {
 799         assert(!dest.pack);
 800         dest.pack = QPU_PACK_MUL_8A + chan;
 801         qir_emit_nondef(c, qir_inst(QOP_MMOV, dest, val, c->undef));
 802 }
 803
 804 static inline struct qreg
 805 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
 806 {
 807         struct qreg dest = qir_MMOV(c, val);
 808         c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
 809         return dest;
 810 }
 811
 812 static inline struct qreg
 813 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
 814 {
 815         return qir_EXP2(c, qir_FMUL(c,
 816                                     y,
 817                                     qir_LOG2(c, x)));
 818 }
 819
 820 static inline void
 821 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
 822 {
 823         qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
 824 }
 825
 826 static inline struct qreg
 827 qir_LOAD_IMM(struct vc4_compile *c, uint32_t val)
 828 {
 829         return qir_emit_def(c, qir_inst(QOP_LOAD_IMM, c->undef,
 830                                         qir_reg(QFILE_LOAD_IMM, val), c->undef));
 831 }
 832
 833 static inline struct qreg
 834 qir_LOAD_IMM_U2(struct vc4_compile *c, uint32_t val)
 835 {
 836         return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_U2, c->undef,
 837                                         qir_reg(QFILE_LOAD_IMM, val),
 838                                         c->undef));
 839 }
 840
 841 static inline struct qreg
 842 qir_LOAD_IMM_I2(struct vc4_compile *c, uint32_t val)
 843 {
 844         return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_I2, c->undef,
 845                                         qir_reg(QFILE_LOAD_IMM, val),
 846                                         c->undef));
 847 }
 848
 849 /** Shifts the multiply output to the right by rot channels */
 850 static inline struct qreg
 851 qir_ROT_MUL(struct vc4_compile *c, struct qreg val, uint32_t rot)
 852 {
 853         return qir_emit_def(c, qir_inst(QOP_ROT_MUL, c->undef,
 854                                         val,
 855                                         qir_reg(QFILE_LOAD_IMM,
 856                                                 QPU_SMALL_IMM_MUL_ROT + rot)));
 857 }
 858
 859 static inline struct qinst *
 860 qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
 861              struct qreg dest, struct qreg src)
 862 {
 863         struct qinst *mov = qir_MOV_dest(c, dest, src);
 864         mov->cond = cond;
 865         return mov;
 866 }
 867
 868 static inline struct qinst *
 869 qir_BRANCH(struct vc4_compile *c, uint8_t cond)
 870 {
 871         struct qinst *inst = qir_inst(QOP_BRANCH, c->undef, c->undef, c->undef);
 872         inst->cond = cond;
 873         qir_emit_nondef(c, inst);
 874         return inst;
 875 }
 876
 877 #define qir_for_each_block(block, c)                                    \
 878         list_for_each_entry(struct qblock, block, &c->blocks, link)
 879
 880 #define qir_for_each_block_rev(block, c)                                \
 881         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
 882
 883 /* Loop over the non-NULL members of the successors array. */
 884 #define qir_for_each_successor(succ, block)                             \
 885         for (struct qblock *succ = block->successors[0];                \
 886              succ != NULL;                                              \
 887              succ = (succ == block->successors[1] ? NULL :              \
 888                      block->successors[1]))
 889
 890 #define qir_for_each_inst(inst, block)                                  \
 891         list_for_each_entry(struct qinst, inst, &block->instructions, link)
 892
 893 #define qir_for_each_inst_rev(inst, block)                                  \
 894         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
 895
 896 #define qir_for_each_inst_safe(inst, block)                             \
 897         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
 898
 899 #define qir_for_each_inst_inorder(inst, c)                              \
 900         qir_for_each_block(_block, c)                                   \
 901                 qir_for_each_inst_safe(inst, _block)
 902
 903 #endif /* VC4_QIR_H */