vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef VC4_QIR_H
25 #define VC4_QIR_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "compiler/nir/nir.h"
36 #include "util/list.h"
37 #include "util/u_math.h"
38
39 #include "vc4_screen.h"
40 #include "vc4_qpu_defines.h"
41 #include "kernel/vc4_packet.h"
42 #include "pipe/p_state.h"
43
44 struct nir_builder;
45
46 enum qfile {
47 QFILE_NULL,
48 QFILE_TEMP,
49 QFILE_VARY,
50 QFILE_UNIF,
51 QFILE_VPM,
52 QFILE_TLB_COLOR_WRITE,
53 QFILE_TLB_COLOR_WRITE_MS,
54 QFILE_TLB_Z_WRITE,
55 QFILE_TLB_STENCIL_SETUP,
56
57 /**
58 * Stores an immediate value in the index field that can be turned
59 * into a small immediate field by qpu_encode_small_immediate().
60 */
61 QFILE_SMALL_IMM,
62 };
63
64 struct qreg {
65 enum qfile file;
66 uint32_t index;
67 int pack;
68 };
69
70 static inline struct qreg qir_reg(enum qfile file, uint32_t index)
71 {
72 return (struct qreg){file, index};
73 }
74
75 enum qop {
76 QOP_UNDEF,
77 QOP_MOV,
78 QOP_FMOV,
79 QOP_MMOV,
80 QOP_FADD,
81 QOP_FSUB,
82 QOP_FMUL,
83 QOP_V8MULD,
84 QOP_V8MIN,
85 QOP_V8MAX,
86 QOP_V8ADDS,
87 QOP_V8SUBS,
88 QOP_MUL24,
89 QOP_FMIN,
90 QOP_FMAX,
91 QOP_FMINABS,
92 QOP_FMAXABS,
93 QOP_ADD,
94 QOP_SUB,
95 QOP_SHL,
96 QOP_SHR,
97 QOP_ASR,
98 QOP_MIN,
99 QOP_MAX,
100 QOP_AND,
101 QOP_OR,
102 QOP_XOR,
103 QOP_NOT,
104
105 QOP_FTOI,
106 QOP_ITOF,
107 QOP_RCP,
108 QOP_RSQ,
109 QOP_EXP2,
110 QOP_LOG2,
111 QOP_VW_SETUP,
112 QOP_VR_SETUP,
113 QOP_TLB_COLOR_READ,
114 QOP_MS_MASK,
115 QOP_VARY_ADD_C,
116
117 QOP_FRAG_X,
118 QOP_FRAG_Y,
119 QOP_FRAG_Z,
120 QOP_FRAG_W,
121 QOP_FRAG_REV_FLAG,
122
123 /** Texture x coordinate parameter write */
124 QOP_TEX_S,
125 /** Texture y coordinate parameter write */
126 QOP_TEX_T,
127 /** Texture border color parameter or cube map z coordinate write */
128 QOP_TEX_R,
129 /** Texture LOD bias parameter write */
130 QOP_TEX_B,
131
132 /**
133 * Texture-unit 4-byte read with address provided direct in S
134 * cooordinate.
135 *
136 * The first operand is the offset from the start of the UBO, and the
137 * second is the uniform that has the UBO's base pointer.
138 */
139 QOP_TEX_DIRECT,
140
141 /**
142 * Signal of texture read being necessary and then reading r4 into
143 * the destination
144 */
145 QOP_TEX_RESULT,
146 };
147
148 struct queued_qpu_inst {
149 struct list_head link;
150 uint64_t inst;
151 };
152
153 struct qinst {
154 struct list_head link;
155
156 enum qop op;
157 struct qreg dst;
158 struct qreg *src;
159 bool sf;
160 uint8_t cond;
161 };
162
163 enum qstage {
164 /**
165 * Coordinate shader, runs during binning, before the VS, and just
166 * outputs position.
167 */
168 QSTAGE_COORD,
169 QSTAGE_VERT,
170 QSTAGE_FRAG,
171 };
172
173 enum quniform_contents {
174 /**
175 * Indicates that a constant 32-bit value is copied from the program's
176 * uniform contents.
177 */
178 QUNIFORM_CONSTANT,
179 /**
180 * Indicates that the program's uniform contents are used as an index
181 * into the GL uniform storage.
182 */
183 QUNIFORM_UNIFORM,
184
185 /** @{
186 * Scaling factors from clip coordinates to relative to the viewport
187 * center.
188 *
189 * This is used by the coordinate and vertex shaders to produce the
190 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
191 * point offsets from the viewport ccenter.
192 */
193 QUNIFORM_VIEWPORT_X_SCALE,
194 QUNIFORM_VIEWPORT_Y_SCALE,
195 /** @} */
196
197 QUNIFORM_VIEWPORT_Z_OFFSET,
198 QUNIFORM_VIEWPORT_Z_SCALE,
199
200 QUNIFORM_USER_CLIP_PLANE,
201
202 /**
203 * A reference to a texture config parameter 0 uniform.
204 *
205 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
206 * defines texture type, miplevels, and such. It will be found as a
207 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
208 */
209 QUNIFORM_TEXTURE_CONFIG_P0,
210
211 /**
212 * A reference to a texture config parameter 1 uniform.
213 *
214 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
215 * defines texture width, height, filters, and wrap modes. It will be
216 * found as a parameter to the second QOP_TEX_[STRB] instruction in a
217 * sequence.
218 */
219 QUNIFORM_TEXTURE_CONFIG_P1,
220
221 /** A reference to a texture config parameter 2 cubemap stride uniform */
222 QUNIFORM_TEXTURE_CONFIG_P2,
223
224 QUNIFORM_TEXTURE_MSAA_ADDR,
225
226 QUNIFORM_UBO_ADDR,
227
228 QUNIFORM_TEXRECT_SCALE_X,
229 QUNIFORM_TEXRECT_SCALE_Y,
230
231 QUNIFORM_TEXTURE_BORDER_COLOR,
232
233 QUNIFORM_BLEND_CONST_COLOR_X,
234 QUNIFORM_BLEND_CONST_COLOR_Y,
235 QUNIFORM_BLEND_CONST_COLOR_Z,
236 QUNIFORM_BLEND_CONST_COLOR_W,
237 QUNIFORM_BLEND_CONST_COLOR_RGBA,
238 QUNIFORM_BLEND_CONST_COLOR_AAAA,
239
240 QUNIFORM_STENCIL,
241
242 QUNIFORM_ALPHA_REF,
243 QUNIFORM_SAMPLE_MASK,
244 };
245
246 struct vc4_varying_slot {
247 uint8_t slot;
248 uint8_t swizzle;
249 };
250
251 struct vc4_compiler_ubo_range {
252 /**
253 * offset in bytes from the start of the ubo where this range is
254 * uploaded.
255 *
256 * Only set once used is set.
257 */
258 uint32_t dst_offset;
259
260 /**
261 * offset in bytes from the start of the gallium uniforms where the
262 * data comes from.
263 */
264 uint32_t src_offset;
265
266 /** size in bytes of this ubo range */
267 uint32_t size;
268
269 /**
270 * Set if this range is used by the shader for indirect uniforms
271 * access.
272 */
273 bool used;
274 };
275
276 struct vc4_key {
277 struct vc4_uncompiled_shader *shader_state;
278 struct {
279 enum pipe_format format;
280 uint8_t swizzle[4];
281 union {
282 struct {
283 unsigned compare_mode:1;
284 unsigned compare_func:3;
285 unsigned wrap_s:3;
286 unsigned wrap_t:3;
287 };
288 struct {
289 uint16_t msaa_width, msaa_height;
290 };
291 };
292 } tex[VC4_MAX_TEXTURE_SAMPLERS];
293 uint8_t ucp_enables;
294 };
295
296 struct vc4_fs_key {
297 struct vc4_key base;
298 enum pipe_format color_format;
299 bool depth_enabled;
300 bool stencil_enabled;
301 bool stencil_twoside;
302 bool stencil_full_writemasks;
303 bool is_points;
304 bool is_lines;
305 bool alpha_test;
306 bool point_coord_upper_left;
307 bool light_twoside;
308 bool msaa;
309 bool sample_coverage;
310 bool sample_alpha_to_coverage;
311 bool sample_alpha_to_one;
312 uint8_t alpha_test_func;
313 uint8_t logicop_func;
314 uint32_t point_sprite_mask;
315
316 struct pipe_rt_blend_state blend;
317 };
318
319 struct vc4_vs_key {
320 struct vc4_key base;
321
322 /**
323 * This is a proxy for the array of FS input semantics, which is
324 * larger than we would want to put in the key.
325 */
326 uint64_t compiled_fs_id;
327
328 enum pipe_format attr_formats[8];
329 bool is_coord;
330 bool per_vertex_point_size;
331 };
332
333 struct vc4_compile {
334 struct vc4_context *vc4;
335 nir_shader *s;
336 nir_function_impl *impl;
337 struct exec_list *cf_node_list;
338
339 /**
340 * Mapping from nir_register * or nir_ssa_def * to array of struct
341 * qreg for the values.
342 */
343 struct hash_table *def_ht;
344
345 /* For each temp, the instruction generating its value. */
346 struct qinst **defs;
347 uint32_t defs_array_size;
348
349 /**
350 * Inputs to the shader, arranged by TGSI declaration order.
351 *
352 * Not all fragment shader QFILE_VARY reads are present in this array.
353 */
354 struct qreg *inputs;
355 struct qreg *outputs;
356 bool msaa_per_sample_output;
357 struct qreg color_reads[VC4_MAX_SAMPLES];
358 struct qreg sample_colors[VC4_MAX_SAMPLES];
359 uint32_t inputs_array_size;
360 uint32_t outputs_array_size;
361 uint32_t uniforms_array_size;
362
363 struct vc4_compiler_ubo_range *ubo_ranges;
364 uint32_t ubo_ranges_array_size;
365 /** Number of uniform areas declared in ubo_ranges. */
366 uint32_t num_uniform_ranges;
367 /** Number of uniform areas used for indirect addressed loads. */
368 uint32_t num_ubo_ranges;
369 uint32_t next_ubo_dst_offset;
370
371 struct qreg line_x, point_x, point_y;
372 struct qreg discard;
373
374 uint8_t vattr_sizes[8];
375
376 /* Bitfield for whether a given channel of a sampler needs sRGB
377 * decode.
378 */
379 uint8_t tex_srgb_decode[VC4_MAX_TEXTURE_SAMPLERS];
380
381 /**
382 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
383 *
384 * This includes those that aren't part of the VPM varyings, like
385 * point/line coordinates.
386 */
387 struct vc4_varying_slot *input_slots;
388 uint32_t num_input_slots;
389 uint32_t input_slots_array_size;
390
391 /**
392 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
393 * of the output is. Used to emit from the VS in the order that the
394 * FS needs.
395 */
396 struct vc4_varying_slot *output_slots;
397
398 struct pipe_shader_state *shader_state;
399 struct vc4_key *key;
400 struct vc4_fs_key *fs_key;
401 struct vc4_vs_key *vs_key;
402
403 uint32_t *uniform_data;
404 enum quniform_contents *uniform_contents;
405 uint32_t uniform_array_size;
406 uint32_t num_uniforms;
407 uint32_t num_outputs;
408 uint32_t num_texture_samples;
409 uint32_t output_position_index;
410 uint32_t output_color_index;
411 uint32_t output_point_size_index;
412 uint32_t output_sample_mask_index;
413
414 struct qreg undef;
415 enum qstage stage;
416 uint32_t num_temps;
417 struct list_head instructions;
418 uint32_t immediates[1024];
419
420 struct list_head qpu_inst_list;
421 uint64_t *qpu_insts;
422 uint32_t qpu_inst_count;
423 uint32_t qpu_inst_size;
424 uint32_t num_inputs;
425
426 uint32_t program_id;
427 uint32_t variant_id;
428 };
429
430 /* Special nir_load_input intrinsic index for loading the current TLB
431 * destination color.
432 */
433 #define VC4_NIR_TLB_COLOR_READ_INPUT 2000000000
434
435 #define VC4_NIR_MS_MASK_OUTPUT 2000000000
436
437 /* Special offset for nir_load_uniform values to get a QUNIFORM_*
438 * state-dependent value.
439 */
440 #define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
441
442 struct vc4_compile *qir_compile_init(void);
443 void qir_compile_destroy(struct vc4_compile *c);
444 struct qinst *qir_inst(enum qop op, struct qreg dst,
445 struct qreg src0, struct qreg src1);
446 struct qinst *qir_inst4(enum qop op, struct qreg dst,
447 struct qreg a,
448 struct qreg b,
449 struct qreg c,
450 struct qreg d);
451 void qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst);
452 struct qreg qir_uniform(struct vc4_compile *c,
453 enum quniform_contents contents,
454 uint32_t data);
455 void qir_schedule_instructions(struct vc4_compile *c);
456 void qir_reorder_uniforms(struct vc4_compile *c);
457
458 void qir_emit(struct vc4_compile *c, struct qinst *inst);
459 static inline struct qinst *
460 qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
461 {
462 list_addtail(&inst->link, &c->instructions);
463 return inst;
464 }
465
466 struct qreg qir_get_temp(struct vc4_compile *c);
467 int qir_get_op_nsrc(enum qop qop);
468 bool qir_reg_equals(struct qreg a, struct qreg b);
469 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
470 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
471 bool qir_is_mul(struct qinst *inst);
472 bool qir_is_raw_mov(struct qinst *inst);
473 bool qir_is_tex(struct qinst *inst);
474 bool qir_is_float_input(struct qinst *inst);
475 bool qir_depends_on_flags(struct qinst *inst);
476 bool qir_writes_r4(struct qinst *inst);
477 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
478
479 void qir_dump(struct vc4_compile *c);
480 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
481 const char *qir_get_stage_name(enum qstage stage);
482
483 void qir_optimize(struct vc4_compile *c);
484 bool qir_opt_algebraic(struct vc4_compile *c);
485 bool qir_opt_constant_folding(struct vc4_compile *c);
486 bool qir_opt_copy_propagation(struct vc4_compile *c);
487 bool qir_opt_cse(struct vc4_compile *c);
488 bool qir_opt_dead_code(struct vc4_compile *c);
489 bool qir_opt_small_immediates(struct vc4_compile *c);
490 bool qir_opt_vpm(struct vc4_compile *c);
491 void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
492 void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
493 nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
494 enum quniform_contents contents);
495 nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
496 nir_ssa_def **srcs, int swiz);
497 void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
498 void qir_lower_uniforms(struct vc4_compile *c);
499
500 uint32_t qpu_schedule_instructions(struct vc4_compile *c);
501
502 void qir_SF(struct vc4_compile *c, struct qreg src);
503
504 static inline struct qreg
505 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)
506 {
507 return qir_uniform(c, QUNIFORM_CONSTANT, ui);
508 }
509
510 static inline struct qreg
511 qir_uniform_f(struct vc4_compile *c, float f)
512 {
513 return qir_uniform(c, QUNIFORM_CONSTANT, fui(f));
514 }
515
516 #define QIR_ALU0(name) \
517 static inline struct qreg \
518 qir_##name(struct vc4_compile *c) \
519 { \
520 struct qreg t = qir_get_temp(c); \
521 qir_emit(c, qir_inst(QOP_##name, t, c->undef, c->undef)); \
522 return t; \
523 }
524
525 #define QIR_ALU1(name) \
526 static inline struct qreg \
527 qir_##name(struct vc4_compile *c, struct qreg a) \
528 { \
529 struct qreg t = qir_get_temp(c); \
530 qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
531 return t; \
532 } \
533 static inline struct qinst * \
534 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
535 struct qreg a) \
536 { \
537 return qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, \
538 c->undef)); \
539 }
540
541 #define QIR_ALU2(name) \
542 static inline struct qreg \
543 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
544 { \
545 struct qreg t = qir_get_temp(c); \
546 qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
547 return t; \
548 } \
549 static inline void \
550 qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
551 struct qreg a, struct qreg b) \
552 { \
553 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
554 }
555
556 #define QIR_NODST_1(name) \
557 static inline struct qinst * \
558 qir_##name(struct vc4_compile *c, struct qreg a) \
559 { \
560 struct qinst *inst = qir_inst(QOP_##name, c->undef, \
561 a, c->undef); \
562 qir_emit(c, inst); \
563 return inst; \
564 }
565
566 #define QIR_NODST_2(name) \
567 static inline struct qinst * \
568 qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
569 { \
570 struct qinst *inst = qir_inst(QOP_##name, c->undef, \
571 a, b); \
572 qir_emit(c, inst); \
573 return inst; \
574 }
575
576 #define QIR_PACK(name) \
577 static inline struct qreg \
578 qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
579 { \
580 qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
581 return dest; \
582 }
583
584 QIR_ALU1(MOV)
585 QIR_ALU1(FMOV)
586 QIR_ALU1(MMOV)
587 QIR_ALU2(FADD)
588 QIR_ALU2(FSUB)
589 QIR_ALU2(FMUL)
590 QIR_ALU2(V8MULD)
591 QIR_ALU2(V8MIN)
592 QIR_ALU2(V8MAX)
593 QIR_ALU2(V8ADDS)
594 QIR_ALU2(V8SUBS)
595 QIR_ALU2(MUL24)
596 QIR_ALU2(FMIN)
597 QIR_ALU2(FMAX)
598 QIR_ALU2(FMINABS)
599 QIR_ALU2(FMAXABS)
600 QIR_ALU1(FTOI)
601 QIR_ALU1(ITOF)
602
603 QIR_ALU2(ADD)
604 QIR_ALU2(SUB)
605 QIR_ALU2(SHL)
606 QIR_ALU2(SHR)
607 QIR_ALU2(ASR)
608 QIR_ALU2(MIN)
609 QIR_ALU2(MAX)
610 QIR_ALU2(AND)
611 QIR_ALU2(OR)
612 QIR_ALU2(XOR)
613 QIR_ALU1(NOT)
614
615 QIR_ALU1(RCP)
616 QIR_ALU1(RSQ)
617 QIR_ALU1(EXP2)
618 QIR_ALU1(LOG2)
619 QIR_ALU1(VARY_ADD_C)
620 QIR_NODST_2(TEX_S)
621 QIR_NODST_2(TEX_T)
622 QIR_NODST_2(TEX_R)
623 QIR_NODST_2(TEX_B)
624 QIR_NODST_2(TEX_DIRECT)
625 QIR_ALU0(FRAG_X)
626 QIR_ALU0(FRAG_Y)
627 QIR_ALU0(FRAG_Z)
628 QIR_ALU0(FRAG_W)
629 QIR_ALU0(FRAG_REV_FLAG)
630 QIR_ALU0(TEX_RESULT)
631 QIR_ALU0(TLB_COLOR_READ)
632 QIR_NODST_1(MS_MASK)
633
634 static inline struct qreg
635 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1)
636 {
637 struct qreg t = qir_get_temp(c);
638 struct qinst *a = qir_MOV_dest(c, t, src0);
639 struct qinst *b = qir_MOV_dest(c, t, src1);
640 a->cond = cond;
641 b->cond = cond ^ 1;
642 return t;
643 }
644
645 static inline struct qreg
646 qir_UNPACK_8_F(struct vc4_compile *c, struct qreg src, int i)
647 {
648 struct qreg t = qir_FMOV(c, src);
649 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
650 return t;
651 }
652
653 static inline struct qreg
654 qir_UNPACK_8_I(struct vc4_compile *c, struct qreg src, int i)
655 {
656 struct qreg t = qir_MOV(c, src);
657 c->defs[t.index]->src[0].pack = QPU_UNPACK_8A + i;
658 return t;
659 }
660
661 static inline struct qreg
662 qir_UNPACK_16_F(struct vc4_compile *c, struct qreg src, int i)
663 {
664 struct qreg t = qir_FMOV(c, src);
665 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
666 return t;
667 }
668
669 static inline struct qreg
670 qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
671 {
672 struct qreg t = qir_MOV(c, src);
673 c->defs[t.index]->src[0].pack = QPU_UNPACK_16A + i;
674 return t;
675 }
676
677 static inline void
678 qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
679 {
680 assert(!dest.pack);
681 dest.pack = QPU_PACK_MUL_8A + chan;
682 qir_emit(c, qir_inst(QOP_MMOV, dest, val, c->undef));
683 if (dest.file == QFILE_TEMP)
684 c->defs[dest.index] = NULL;
685 }
686
687 static inline struct qreg
688 qir_PACK_8888_F(struct vc4_compile *c, struct qreg val)
689 {
690 struct qreg dest = qir_MMOV(c, val);
691 c->defs[dest.index]->dst.pack = QPU_PACK_MUL_8888;
692 return dest;
693 }
694
695 static inline struct qreg
696 qir_POW(struct vc4_compile *c, struct qreg x, struct qreg y)
697 {
698 return qir_EXP2(c, qir_FMUL(c,
699 y,
700 qir_LOG2(c, x)));
701 }
702
703 static inline void
704 qir_VPM_WRITE(struct vc4_compile *c, struct qreg val)
705 {
706 qir_MOV_dest(c, qir_reg(QFILE_VPM, 0), val);
707 }
708
709 #endif /* VC4_QIR_H */