2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2015 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @file vc4_qir_schedule.c
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies from the bottom up, and make a list of the DAG
30 * heads. Heuristically pick a DAG head and schedule (remove) it, then put
31 * all the parents that are now DAG heads into the list of things to
34 * The goal of scheduling here, before register allocation and conversion to
35 * QPU instructions, is to reduce register pressure by reordering instructions
36 * to consume values when possible.
43 struct schedule_node
{
44 struct list_head link
;
47 struct schedule_node
**children
;
49 uint32_t child_array_size
;
50 uint32_t parent_count
;
52 /* Length of the longest (latency) chain from a DAG head to the this
57 /* Longest time + latency_between(parent, this) of any parent of this
60 uint32_t unblocked_time
;
63 struct schedule_state
{
64 /* List of struct schedule_node *. This starts out with all
65 * instructions, and after dependency updates it's trimmed to be just
68 struct list_head worklist
;
72 uint32_t *temp_writes
;
74 BITSET_WORD
*temp_live
;
77 /* When walking the instructions in reverse, we need to swap before/after in
80 enum direction
{ F
, R
};
83 * Marks a dependency between two intructions, that \p after must appear after
86 * Our dependencies are tracked as a DAG. Since we're scheduling bottom-up,
87 * the latest instructions with nothing left to schedule are the DAG heads,
88 * and their inputs are their children.
91 add_dep(enum direction dir
,
92 struct schedule_node
*before
,
93 struct schedule_node
*after
)
95 if (!before
|| !after
)
98 assert(before
!= after
);
101 struct schedule_node
*t
= before
;
106 for (int i
= 0; i
< after
->child_count
; i
++) {
107 if (after
->children
[i
] == after
)
111 if (after
->child_array_size
<= after
->child_count
) {
112 after
->child_array_size
= MAX2(after
->child_array_size
* 2, 16);
113 after
->children
= reralloc(after
, after
->children
,
114 struct schedule_node
*,
115 after
->child_array_size
);
118 after
->children
[after
->child_count
] = before
;
119 after
->child_count
++;
120 before
->parent_count
++;
124 add_write_dep(enum direction dir
,
125 struct schedule_node
**before
,
126 struct schedule_node
*after
)
128 add_dep(dir
, *before
, after
);
132 struct schedule_setup_state
{
133 struct schedule_node
**last_temp_write
;
134 struct schedule_node
*last_sf
;
135 struct schedule_node
*last_vary_read
;
136 struct schedule_node
*last_vpm_read
;
137 struct schedule_node
*last_vpm_write
;
138 struct schedule_node
*last_tex_coord
;
139 struct schedule_node
*last_tex_result
;
140 struct schedule_node
*last_tlb
;
141 struct schedule_node
*last_uniforms_reset
;
145 * Texture FIFO tracking. This is done top-to-bottom, and is used to
146 * track the QOP_TEX_RESULTs and add dependencies on previous ones
147 * when trying to submit texture coords with TFREQ full or new texture
148 * fetches with TXRCV full.
151 struct schedule_node
*node
;
154 int tfreq_count
; /**< Number of texture coords outstanding. */
155 int tfrcv_count
; /**< Number of texture results outstanding. */
160 block_until_tex_result(struct schedule_setup_state
*state
, struct schedule_node
*n
)
162 add_dep(state
->dir
, state
->tex_fifo
[0].node
, n
);
164 state
->tfreq_count
-= state
->tex_fifo
[0].coords
;
165 state
->tfrcv_count
--;
167 memmove(&state
->tex_fifo
[0],
169 state
->tex_fifo_pos
* sizeof(state
->tex_fifo
[0]));
170 state
->tex_fifo_pos
--;
174 * Common code for dependencies that need to be tracked both forward and
177 * This is for things like "all VPM reads have to happen in order."
180 calculate_deps(struct schedule_setup_state
*state
, struct schedule_node
*n
)
182 struct qinst
*inst
= n
->inst
;
183 enum direction dir
= state
->dir
;
186 /* Add deps for temp registers and varyings accesses. Note that we
187 * ignore uniforms accesses, because qir_reorder_uniforms() happens
190 for (int i
= 0; i
< qir_get_nsrc(inst
); i
++) {
191 switch (inst
->src
[i
].file
) {
194 state
->last_temp_write
[inst
->src
[i
].index
], n
);
198 add_write_dep(dir
, &state
->last_vary_read
, n
);
202 add_write_dep(dir
, &state
->last_vpm_read
, n
);
212 add_dep(dir
, state
->last_vary_read
, n
);
216 /* Results have to be fetched in order. */
217 add_write_dep(dir
, &state
->last_tex_result
, n
);
221 /* After a new THRSW, one must collect all texture samples
222 * queued since the previous THRSW/program start. For now, we
223 * have one THRSW in between each texture setup and its
224 * results collection as our input, and we just make sure that
225 * that ordering is maintained.
227 add_write_dep(dir
, &state
->last_tex_coord
, n
);
228 add_write_dep(dir
, &state
->last_tex_result
, n
);
230 /* accumulators and flags are lost across thread switches. */
231 add_write_dep(dir
, &state
->last_sf
, n
);
233 /* Setup, like the varyings, will need to be drained before we
236 add_write_dep(dir
, &state
->last_vary_read
, n
);
238 /* The TLB-locking operations have to stay after the last
241 add_write_dep(dir
, &state
->last_tlb
, n
);
244 case QOP_TLB_COLOR_READ
:
246 add_write_dep(dir
, &state
->last_tlb
, n
);
253 switch (inst
->dst
.file
) {
255 add_write_dep(dir
, &state
->last_vpm_write
, n
);
259 add_write_dep(dir
, &state
->last_temp_write
[inst
->dst
.index
], n
);
262 case QFILE_TLB_COLOR_WRITE
:
263 case QFILE_TLB_COLOR_WRITE_MS
:
264 case QFILE_TLB_Z_WRITE
:
265 case QFILE_TLB_STENCIL_SETUP
:
266 add_write_dep(dir
, &state
->last_tlb
, n
);
269 case QFILE_TEX_S_DIRECT
:
274 /* Texturing setup gets scheduled in order, because
275 * the uniforms referenced by them have to land in a
278 add_write_dep(dir
, &state
->last_tex_coord
, n
);
285 if (qir_depends_on_flags(inst
))
286 add_dep(dir
, state
->last_sf
, n
);
289 add_write_dep(dir
, &state
->last_sf
, n
);
293 calculate_forward_deps(struct vc4_compile
*c
, void *mem_ctx
,
294 struct list_head
*schedule_list
)
296 struct schedule_setup_state state
;
298 memset(&state
, 0, sizeof(state
));
299 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
303 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
304 struct qinst
*inst
= n
->inst
;
306 calculate_deps(&state
, n
);
308 for (int i
= 0; i
< qir_get_nsrc(inst
); i
++) {
309 switch (inst
->src
[i
].file
) {
311 add_dep(state
.dir
, state
.last_uniforms_reset
, n
);
318 switch (inst
->dst
.file
) {
319 case QFILE_TEX_S_DIRECT
:
324 /* From the VC4 spec:
326 * "The TFREQ input FIFO holds two full lots of s,
327 * t, r, b data, plus associated setup data, per
328 * QPU, that is, there are eight data slots. For
329 * each texture request, slots are only consumed
330 * for the components of s, t, r, and b actually
331 * written. Thus the FIFO can hold four requests
332 * of just (s, t) data, or eight requests of just
333 * s data (for direct addressed data lookups).
335 * Note that there is one FIFO per QPU, and the
336 * FIFO has no concept of threads - that is,
337 * multi-threaded shaders must be careful to use
338 * only 1/2 the FIFO depth before reading
339 * back. Multi-threaded programs must also
340 * therefore always thread switch on texture
341 * fetch as the other thread may have data
342 * waiting in the FIFO."
344 * If the texture coordinate fifo is full, block this
345 * on the last QOP_TEX_RESULT.
347 if (state
.tfreq_count
== (c
->fs_threaded
? 4 : 8)) {
348 block_until_tex_result(&state
, n
);
351 /* From the VC4 spec:
353 * "Since the maximum number of texture requests
354 * in the input (TFREQ) FIFO is four lots of (s,
355 * t) data, the output (TFRCV) FIFO is sized to
356 * holds four lots of max-size color data per
357 * QPU. For non-float color, reads are packed
358 * RGBA8888 data (one read per pixel). For 16-bit
359 * float color, two reads are necessary per
360 * pixel, with reads packed as RG1616 then
361 * BA1616. So per QPU there are eight color slots
362 * in the TFRCV FIFO."
364 * If the texture result fifo is full, block adding
365 * any more to it until the last QOP_TEX_RESULT.
367 if (inst
->dst
.file
== QFILE_TEX_S
||
368 inst
->dst
.file
== QFILE_TEX_S_DIRECT
) {
369 if (state
.tfrcv_count
==
370 (c
->fs_threaded
? 2 : 4))
371 block_until_tex_result(&state
, n
);
375 state
.tex_fifo
[state
.tex_fifo_pos
].coords
++;
385 /* Results have to be fetched after the
386 * coordinate setup. Note that we're assuming
387 * here that our input shader has the texture
388 * coord setup and result fetch in order,
389 * which is true initially but not of our
390 * instruction stream after this pass.
392 add_dep(state
.dir
, state
.last_tex_coord
, n
);
394 state
.tex_fifo
[state
.tex_fifo_pos
].node
= n
;
396 state
.tex_fifo_pos
++;
397 memset(&state
.tex_fifo
[state
.tex_fifo_pos
], 0,
398 sizeof(state
.tex_fifo
[0]));
401 case QOP_UNIFORMS_RESET
:
402 add_write_dep(state
.dir
, &state
.last_uniforms_reset
, n
);
412 calculate_reverse_deps(struct vc4_compile
*c
, void *mem_ctx
,
413 struct list_head
*schedule_list
)
415 struct schedule_setup_state state
;
417 memset(&state
, 0, sizeof(state
));
419 state
.last_temp_write
= rzalloc_array(mem_ctx
, struct schedule_node
*,
422 list_for_each_entry_rev(struct schedule_node
, n
, schedule_list
, link
) {
423 calculate_deps(&state
, n
);
428 get_register_pressure_cost(struct schedule_state
*state
, struct qinst
*inst
)
432 if (inst
->dst
.file
== QFILE_TEMP
&&
433 state
->temp_writes
[inst
->dst
.index
] == 1)
436 for (int i
= 0; i
< qir_get_nsrc(inst
); i
++) {
437 if (inst
->src
[i
].file
!= QFILE_TEMP
||
438 BITSET_TEST(state
->temp_live
, inst
->src
[i
].index
)) {
442 bool already_counted
= false;
443 for (int j
= 0; j
< i
; j
++) {
444 if (inst
->src
[i
].file
== inst
->src
[j
].file
&&
445 inst
->src
[i
].index
== inst
->src
[j
].index
) {
446 already_counted
= true;
449 if (!already_counted
)
457 locks_scoreboard(struct qinst
*inst
)
459 if (inst
->op
== QOP_TLB_COLOR_READ
)
462 switch (inst
->dst
.file
) {
463 case QFILE_TLB_Z_WRITE
:
464 case QFILE_TLB_COLOR_WRITE
:
465 case QFILE_TLB_COLOR_WRITE_MS
:
472 static struct schedule_node
*
473 choose_instruction(struct schedule_state
*state
)
475 struct schedule_node
*chosen
= NULL
;
477 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
478 /* The branches aren't being tracked as dependencies. Make
479 * sure that they stay scheduled as the last instruction of
480 * the block, which is to say the first one we choose to
483 if (n
->inst
->op
== QOP_BRANCH
)
491 /* Prefer scheduling things that lock the scoreboard, so that
492 * they appear late in the program and we get more parallelism
493 * between shaders on multiple QPUs hitting the same fragment.
495 if (locks_scoreboard(n
->inst
) &&
496 !locks_scoreboard(chosen
->inst
)) {
499 } else if (!locks_scoreboard(n
->inst
) &&
500 locks_scoreboard(chosen
->inst
)) {
504 /* If we would block on the previously chosen node, but would
505 * block less on this one, then prefer it.
507 if (chosen
->unblocked_time
> state
->time
&&
508 n
->unblocked_time
< chosen
->unblocked_time
) {
511 } else if (n
->unblocked_time
> state
->time
&&
512 n
->unblocked_time
> chosen
->unblocked_time
) {
516 /* If we can definitely reduce register pressure, do so
519 int register_pressure_cost
=
520 get_register_pressure_cost(state
, n
->inst
);
521 int chosen_register_pressure_cost
=
522 get_register_pressure_cost(state
, chosen
->inst
);
524 if (register_pressure_cost
< chosen_register_pressure_cost
) {
527 } else if (register_pressure_cost
>
528 chosen_register_pressure_cost
) {
532 /* Otherwise, prefer instructions with the deepest chain to
533 * the end of the program. This avoids the problem of
534 * "everything generates a temp, nothing finishes freeing one,
535 * guess I'll just keep emitting varying mul/adds".
537 if (n
->delay
> chosen
->delay
) {
540 } else if (n
->delay
< chosen
->delay
) {
549 dump_state(struct vc4_compile
*c
, struct schedule_state
*state
)
552 list_for_each_entry(struct schedule_node
, n
, &state
->worklist
, link
) {
553 fprintf(stderr
, "%3d: ", i
++);
554 qir_dump_inst(c
, n
->inst
);
555 fprintf(stderr
, " (%d cost)\n",
556 get_register_pressure_cost(state
, n
->inst
));
558 for (int i
= 0; i
< n
->child_count
; i
++) {
559 struct schedule_node
*child
= n
->children
[i
];
560 fprintf(stderr
, " - ");
561 qir_dump_inst(c
, child
->inst
);
562 fprintf(stderr
, " (%d parents)\n", child
->parent_count
);
567 /* Estimate of how many instructions we should schedule between operations.
569 * These aren't in real cycle counts, because we're just estimating cycle
570 * times anyway. QIR instructions will get paired up when turned into QPU
571 * instructions, or extra NOP delays will have to be added due to register
572 * allocation choices.
575 latency_between(struct schedule_node
*before
, struct schedule_node
*after
)
577 if ((before
->inst
->dst
.file
== QFILE_TEX_S
||
578 before
->inst
->dst
.file
== QFILE_TEX_S_DIRECT
) &&
579 after
->inst
->op
== QOP_TEX_RESULT
)
582 switch (before
->inst
->op
) {
587 for (int i
= 0; i
< qir_get_nsrc(after
->inst
); i
++) {
588 if (after
->inst
->src
[i
].file
==
589 before
->inst
->dst
.file
&&
590 after
->inst
->src
[i
].index
==
591 before
->inst
->dst
.index
) {
592 /* There are two QPU delay slots before we can
593 * read a math result, which could be up to 4
594 * QIR instructions if they packed well.
607 /** Recursive computation of the delay member of a node. */
609 compute_delay(struct schedule_node
*n
)
611 if (!n
->child_count
) {
612 /* The color read needs to be scheduled late, to avoid locking
613 * the scoreboard early. This is our best tool for
614 * encouraging that. The other scoreboard locking ops will
615 * have this happen by default, since they are generally the
616 * DAG heads or close to them.
618 if (n
->inst
->op
== QOP_TLB_COLOR_READ
)
623 for (int i
= 0; i
< n
->child_count
; i
++) {
624 if (!n
->children
[i
]->delay
)
625 compute_delay(n
->children
[i
]);
626 n
->delay
= MAX2(n
->delay
,
627 n
->children
[i
]->delay
+
628 latency_between(n
->children
[i
], n
));
634 schedule_instructions(struct vc4_compile
*c
,
635 struct qblock
*block
, struct schedule_state
*state
)
638 fprintf(stderr
, "initial deps:\n");
639 dump_state(c
, state
);
642 /* Remove non-DAG heads from the list. */
643 list_for_each_entry_safe(struct schedule_node
, n
,
644 &state
->worklist
, link
) {
645 if (n
->parent_count
!= 0)
650 while (!list_empty(&state
->worklist
)) {
651 struct schedule_node
*chosen
= choose_instruction(state
);
652 struct qinst
*inst
= chosen
->inst
;
655 fprintf(stderr
, "current list:\n");
656 dump_state(c
, state
);
657 fprintf(stderr
, "chose: ");
658 qir_dump_inst(c
, inst
);
659 fprintf(stderr
, " (%d cost)\n",
660 get_register_pressure_cost(state
, inst
));
663 state
->time
= MAX2(state
->time
, chosen
->unblocked_time
);
665 /* Schedule this instruction back onto the QIR list. */
666 list_del(&chosen
->link
);
667 list_add(&inst
->link
, &block
->instructions
);
669 /* Now that we've scheduled a new instruction, some of its
670 * children can be promoted to the list of instructions ready to
671 * be scheduled. Update the children's unblocked time for this
672 * DAG edge as we do so.
674 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
675 struct schedule_node
*child
= chosen
->children
[i
];
677 child
->unblocked_time
= MAX2(child
->unblocked_time
,
679 latency_between(child
,
681 child
->parent_count
--;
682 if (child
->parent_count
== 0)
683 list_add(&child
->link
, &state
->worklist
);
686 /* Update our tracking of register pressure. */
687 for (int i
= 0; i
< qir_get_nsrc(inst
); i
++) {
688 if (inst
->src
[i
].file
== QFILE_TEMP
)
689 BITSET_SET(state
->temp_live
, inst
->src
[i
].index
);
691 if (inst
->dst
.file
== QFILE_TEMP
) {
692 state
->temp_writes
[inst
->dst
.index
]--;
693 if (state
->temp_writes
[inst
->dst
.index
] == 0)
694 BITSET_CLEAR(state
->temp_live
, inst
->dst
.index
);
702 qir_schedule_instructions_block(struct vc4_compile
*c
,
703 struct qblock
*block
)
705 void *mem_ctx
= ralloc_context(NULL
);
706 struct schedule_state state
= { { 0 } };
708 state
.temp_writes
= rzalloc_array(mem_ctx
, uint32_t, c
->num_temps
);
709 state
.temp_live
= rzalloc_array(mem_ctx
, BITSET_WORD
,
710 BITSET_WORDS(c
->num_temps
));
711 list_inithead(&state
.worklist
);
713 /* Wrap each instruction in a scheduler structure. */
714 qir_for_each_inst_safe(inst
, block
) {
715 struct schedule_node
*n
= rzalloc(mem_ctx
, struct schedule_node
);
718 list_del(&inst
->link
);
719 list_addtail(&n
->link
, &state
.worklist
);
721 if (inst
->dst
.file
== QFILE_TEMP
)
722 state
.temp_writes
[inst
->dst
.index
]++;
725 /* Dependencies tracked top-to-bottom. */
726 calculate_forward_deps(c
, mem_ctx
, &state
.worklist
);
727 /* Dependencies tracked bottom-to-top. */
728 calculate_reverse_deps(c
, mem_ctx
, &state
.worklist
);
730 list_for_each_entry(struct schedule_node
, n
, &state
.worklist
, link
)
733 schedule_instructions(c
, block
, &state
);
735 ralloc_free(mem_ctx
);
739 qir_schedule_instructions(struct vc4_compile
*c
)
743 fprintf(stderr
, "Pre-schedule instructions\n");
747 qir_for_each_block(block
, c
)
748 qir_schedule_instructions_block(c
, block
);
751 fprintf(stderr
, "Post-schedule instructions\n");