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vc4: Add support for QPU scheduling of thread switch instructions.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file vc4_qpu_schedule.c
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "vc4_qir.h"
38 #include "vc4_qpu.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct queued_qpu_inst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68
69 /**
70 * Which uniform from uniform_data[] this instruction read, or -1 if
71 * not reading a uniform.
72 */
73 int uniform;
74 };
75
76 struct schedule_node_child {
77 struct schedule_node *node;
78 bool write_after_read;
79 };
80
81 /* When walking the instructions in reverse, we need to swap before/after in
82 * add_dep().
83 */
84 enum direction { F, R };
85
86 struct schedule_state {
87 struct schedule_node *last_r[6];
88 struct schedule_node *last_ra[32];
89 struct schedule_node *last_rb[32];
90 struct schedule_node *last_sf;
91 struct schedule_node *last_vpm_read;
92 struct schedule_node *last_tmu_write;
93 struct schedule_node *last_tlb;
94 struct schedule_node *last_vpm;
95 struct schedule_node *last_uniforms_reset;
96 enum direction dir;
97 /* Estimated cycle when the current instruction would start. */
98 uint32_t time;
99 };
100
101 static void
102 add_dep(struct schedule_state *state,
103 struct schedule_node *before,
104 struct schedule_node *after,
105 bool write)
106 {
107 bool write_after_read = !write && state->dir == R;
108
109 if (!before || !after)
110 return;
111
112 assert(before != after);
113
114 if (state->dir == R) {
115 struct schedule_node *t = before;
116 before = after;
117 after = t;
118 }
119
120 for (int i = 0; i < before->child_count; i++) {
121 if (before->children[i].node == after &&
122 (before->children[i].write_after_read == write_after_read)) {
123 return;
124 }
125 }
126
127 if (before->child_array_size <= before->child_count) {
128 before->child_array_size = MAX2(before->child_array_size * 2, 16);
129 before->children = reralloc(before, before->children,
130 struct schedule_node_child,
131 before->child_array_size);
132 }
133
134 before->children[before->child_count].node = after;
135 before->children[before->child_count].write_after_read =
136 write_after_read;
137 before->child_count++;
138 after->parent_count++;
139 }
140
141 static void
142 add_read_dep(struct schedule_state *state,
143 struct schedule_node *before,
144 struct schedule_node *after)
145 {
146 add_dep(state, before, after, false);
147 }
148
149 static void
150 add_write_dep(struct schedule_state *state,
151 struct schedule_node **before,
152 struct schedule_node *after)
153 {
154 add_dep(state, *before, after, true);
155 *before = after;
156 }
157
158 static bool
159 qpu_writes_r4(uint64_t inst)
160 {
161 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
162
163 switch(sig) {
164 case QPU_SIG_COLOR_LOAD:
165 case QPU_SIG_LOAD_TMU0:
166 case QPU_SIG_LOAD_TMU1:
167 case QPU_SIG_ALPHA_MASK_LOAD:
168 return true;
169 default:
170 return false;
171 }
172 }
173
174 static void
175 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
176 uint32_t raddr, bool is_a)
177 {
178 switch (raddr) {
179 case QPU_R_VARY:
180 add_write_dep(state, &state->last_r[5], n);
181 break;
182
183 case QPU_R_VPM:
184 add_write_dep(state, &state->last_vpm_read, n);
185 break;
186
187 case QPU_R_UNIF:
188 add_read_dep(state, state->last_uniforms_reset, n);
189 break;
190
191 case QPU_R_NOP:
192 case QPU_R_ELEM_QPU:
193 case QPU_R_XY_PIXEL_COORD:
194 case QPU_R_MS_REV_FLAGS:
195 break;
196
197 default:
198 if (raddr < 32) {
199 if (is_a)
200 add_read_dep(state, state->last_ra[raddr], n);
201 else
202 add_read_dep(state, state->last_rb[raddr], n);
203 } else {
204 fprintf(stderr, "unknown raddr %d\n", raddr);
205 abort();
206 }
207 break;
208 }
209 }
210
211 static bool
212 is_tmu_write(uint32_t waddr)
213 {
214 switch (waddr) {
215 case QPU_W_TMU0_S:
216 case QPU_W_TMU0_T:
217 case QPU_W_TMU0_R:
218 case QPU_W_TMU0_B:
219 case QPU_W_TMU1_S:
220 case QPU_W_TMU1_T:
221 case QPU_W_TMU1_R:
222 case QPU_W_TMU1_B:
223 return true;
224 default:
225 return false;
226 }
227 }
228
229 static bool
230 reads_uniform(uint64_t inst)
231 {
232 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
233 return false;
234
235 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
236 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
237 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
238 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
239 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
240 }
241
242 static void
243 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
244 uint32_t mux)
245 {
246 if (mux != QPU_MUX_A && mux != QPU_MUX_B)
247 add_read_dep(state, state->last_r[mux], n);
248 }
249
250
251 static void
252 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
253 uint32_t waddr, bool is_add)
254 {
255 uint64_t inst = n->inst->inst;
256 bool is_a = is_add ^ ((inst & QPU_WS) != 0);
257
258 if (waddr < 32) {
259 if (is_a) {
260 add_write_dep(state, &state->last_ra[waddr], n);
261 } else {
262 add_write_dep(state, &state->last_rb[waddr], n);
263 }
264 } else if (is_tmu_write(waddr)) {
265 add_write_dep(state, &state->last_tmu_write, n);
266 add_read_dep(state, state->last_uniforms_reset, n);
267 } else if (qpu_waddr_is_tlb(waddr) ||
268 waddr == QPU_W_MS_FLAGS) {
269 add_write_dep(state, &state->last_tlb, n);
270 } else {
271 switch (waddr) {
272 case QPU_W_ACC0:
273 case QPU_W_ACC1:
274 case QPU_W_ACC2:
275 case QPU_W_ACC3:
276 case QPU_W_ACC5:
277 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
278 n);
279 break;
280
281 case QPU_W_VPM:
282 add_write_dep(state, &state->last_vpm, n);
283 break;
284
285 case QPU_W_VPMVCD_SETUP:
286 if (is_a)
287 add_write_dep(state, &state->last_vpm_read, n);
288 else
289 add_write_dep(state, &state->last_vpm, n);
290 break;
291
292 case QPU_W_SFU_RECIP:
293 case QPU_W_SFU_RECIPSQRT:
294 case QPU_W_SFU_EXP:
295 case QPU_W_SFU_LOG:
296 add_write_dep(state, &state->last_r[4], n);
297 break;
298
299 case QPU_W_TLB_STENCIL_SETUP:
300 /* This isn't a TLB operation that does things like
301 * implicitly lock the scoreboard, but it does have to
302 * appear before TLB_Z, and each of the TLB_STENCILs
303 * have to schedule in the same order relative to each
304 * other.
305 */
306 add_write_dep(state, &state->last_tlb, n);
307 break;
308
309 case QPU_W_MS_FLAGS:
310 add_write_dep(state, &state->last_tlb, n);
311 break;
312
313 case QPU_W_UNIFORMS_ADDRESS:
314 add_write_dep(state, &state->last_uniforms_reset, n);
315 break;
316
317 case QPU_W_NOP:
318 break;
319
320 default:
321 fprintf(stderr, "Unknown waddr %d\n", waddr);
322 abort();
323 }
324 }
325 }
326
327 static void
328 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
329 uint32_t cond)
330 {
331 switch (cond) {
332 case QPU_COND_NEVER:
333 case QPU_COND_ALWAYS:
334 break;
335 default:
336 add_read_dep(state, state->last_sf, n);
337 break;
338 }
339 }
340
341 /**
342 * Common code for dependencies that need to be tracked both forward and
343 * backward.
344 *
345 * This is for things like "all reads of r4 have to happen between the r4
346 * writes that surround them".
347 */
348 static void
349 calculate_deps(struct schedule_state *state, struct schedule_node *n)
350 {
351 uint64_t inst = n->inst->inst;
352 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
353 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
354 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
355 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
356 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
357 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
358 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
359 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
360 uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
361 uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
362 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
363
364 if (sig != QPU_SIG_LOAD_IMM) {
365 process_raddr_deps(state, n, raddr_a, true);
366 if (sig != QPU_SIG_SMALL_IMM &&
367 sig != QPU_SIG_BRANCH)
368 process_raddr_deps(state, n, raddr_b, false);
369 }
370
371 if (add_op != QPU_A_NOP) {
372 process_mux_deps(state, n, add_a);
373 process_mux_deps(state, n, add_b);
374 }
375 if (mul_op != QPU_M_NOP) {
376 process_mux_deps(state, n, mul_a);
377 process_mux_deps(state, n, mul_b);
378 }
379
380 process_waddr_deps(state, n, waddr_add, true);
381 process_waddr_deps(state, n, waddr_mul, false);
382 if (qpu_writes_r4(inst))
383 add_write_dep(state, &state->last_r[4], n);
384
385 switch (sig) {
386 case QPU_SIG_SW_BREAKPOINT:
387 case QPU_SIG_NONE:
388 case QPU_SIG_SMALL_IMM:
389 case QPU_SIG_LOAD_IMM:
390 break;
391
392 case QPU_SIG_THREAD_SWITCH:
393 case QPU_SIG_LAST_THREAD_SWITCH:
394 /* All accumulator contents and flags are undefined after the
395 * switch.
396 */
397 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
398 add_write_dep(state, &state->last_r[i], n);
399 add_write_dep(state, &state->last_sf, n);
400
401 /* Scoreboard-locking operations have to stay after the last
402 * thread switch.
403 */
404 add_write_dep(state, &state->last_tlb, n);
405
406 add_write_dep(state, &state->last_tmu_write, n);
407 break;
408
409 case QPU_SIG_LOAD_TMU0:
410 case QPU_SIG_LOAD_TMU1:
411 /* TMU loads are coming from a FIFO, so ordering is important.
412 */
413 add_write_dep(state, &state->last_tmu_write, n);
414 break;
415
416 case QPU_SIG_COLOR_LOAD:
417 add_read_dep(state, state->last_tlb, n);
418 break;
419
420 case QPU_SIG_BRANCH:
421 add_read_dep(state, state->last_sf, n);
422 break;
423
424 case QPU_SIG_PROG_END:
425 case QPU_SIG_WAIT_FOR_SCOREBOARD:
426 case QPU_SIG_SCOREBOARD_UNLOCK:
427 case QPU_SIG_COVERAGE_LOAD:
428 case QPU_SIG_COLOR_LOAD_END:
429 case QPU_SIG_ALPHA_MASK_LOAD:
430 fprintf(stderr, "Unhandled signal bits %d\n", sig);
431 abort();
432 }
433
434 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
435 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
436 if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
437 add_write_dep(state, &state->last_sf, n);
438 }
439
440 static void
441 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
442 {
443 struct schedule_state state;
444
445 memset(&state, 0, sizeof(state));
446 state.dir = F;
447
448 list_for_each_entry(struct schedule_node, node, schedule_list, link)
449 calculate_deps(&state, node);
450 }
451
452 static void
453 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
454 {
455 struct list_head *node;
456 struct schedule_state state;
457
458 memset(&state, 0, sizeof(state));
459 state.dir = R;
460
461 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
462 calculate_deps(&state, (struct schedule_node *)node);
463 }
464 }
465
466 struct choose_scoreboard {
467 int tick;
468 int last_sfu_write_tick;
469 int last_uniforms_reset_tick;
470 uint32_t last_waddr_a, last_waddr_b;
471 bool tlb_locked;
472 };
473
474 static bool
475 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
476 {
477 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
478 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
479 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
480 uint32_t src_muxes[] = {
481 QPU_GET_FIELD(inst, QPU_ADD_A),
482 QPU_GET_FIELD(inst, QPU_ADD_B),
483 QPU_GET_FIELD(inst, QPU_MUL_A),
484 QPU_GET_FIELD(inst, QPU_MUL_B),
485 };
486 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
487 if ((src_muxes[i] == QPU_MUX_A &&
488 raddr_a < 32 &&
489 scoreboard->last_waddr_a == raddr_a) ||
490 (src_muxes[i] == QPU_MUX_B &&
491 sig != QPU_SIG_SMALL_IMM &&
492 raddr_b < 32 &&
493 scoreboard->last_waddr_b == raddr_b)) {
494 return true;
495 }
496
497 if (src_muxes[i] == QPU_MUX_R4) {
498 if (scoreboard->tick -
499 scoreboard->last_sfu_write_tick <= 2) {
500 return true;
501 }
502 }
503 }
504
505 if (sig == QPU_SIG_SMALL_IMM &&
506 QPU_GET_FIELD(inst, QPU_SMALL_IMM) >= QPU_SMALL_IMM_MUL_ROT) {
507 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
508 uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
509
510 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
511 scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
512 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
513 scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
514 return true;
515 }
516 }
517
518 if (reads_uniform(inst) &&
519 scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
520 return true;
521 }
522
523 return false;
524 }
525
526 static bool
527 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
528 {
529 return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
530 }
531
532 static int
533 get_instruction_priority(uint64_t inst)
534 {
535 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
536 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
537 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
538 uint32_t baseline_score;
539 uint32_t next_score = 0;
540
541 /* Schedule TLB operations as late as possible, to get more
542 * parallelism between shaders.
543 */
544 if (qpu_inst_is_tlb(inst))
545 return next_score;
546 next_score++;
547
548 /* Schedule texture read results collection late to hide latency. */
549 if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
550 return next_score;
551 next_score++;
552
553 /* Default score for things that aren't otherwise special. */
554 baseline_score = next_score;
555 next_score++;
556
557 /* Schedule texture read setup early to hide their latency better. */
558 if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
559 return next_score;
560 next_score++;
561
562 return baseline_score;
563 }
564
565 static struct schedule_node *
566 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
567 struct list_head *schedule_list,
568 struct schedule_node *prev_inst)
569 {
570 struct schedule_node *chosen = NULL;
571 int chosen_prio = 0;
572
573 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
574 uint64_t inst = n->inst->inst;
575
576 /* Don't choose the branch instruction until it's the last one
577 * left. XXX: We could potentially choose it before it's the
578 * last one, if the remaining instructions fit in the delay
579 * slots.
580 */
581 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
582 !list_is_singular(schedule_list)) {
583 continue;
584 }
585
586 /* "An instruction must not read from a location in physical
587 * regfile A or B that was written to by the previous
588 * instruction."
589 */
590 if (reads_too_soon_after_write(scoreboard, inst))
591 continue;
592
593 /* "A scoreboard wait must not occur in the first two
594 * instructions of a fragment shader. This is either the
595 * explicit Wait for Scoreboard signal or an implicit wait
596 * with the first tile-buffer read or write instruction."
597 */
598 if (pixel_scoreboard_too_soon(scoreboard, inst))
599 continue;
600
601 /* If we're trying to pair with another instruction, check
602 * that they're compatible.
603 */
604 if (prev_inst) {
605 if (prev_inst->uniform != -1 && n->uniform != -1)
606 continue;
607
608 /* Don't merge in something that will lock the TLB.
609 * Hopwefully what we have in inst will release some
610 * other instructions, allowing us to delay the
611 * TLB-locking instruction until later.
612 */
613 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
614 continue;
615
616 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
617 if (!inst)
618 continue;
619 }
620
621 int prio = get_instruction_priority(inst);
622
623 /* Found a valid instruction. If nothing better comes along,
624 * this one works.
625 */
626 if (!chosen) {
627 chosen = n;
628 chosen_prio = prio;
629 continue;
630 }
631
632 if (prio > chosen_prio) {
633 chosen = n;
634 chosen_prio = prio;
635 } else if (prio < chosen_prio) {
636 continue;
637 }
638
639 if (n->delay > chosen->delay) {
640 chosen = n;
641 chosen_prio = prio;
642 } else if (n->delay < chosen->delay) {
643 continue;
644 }
645 }
646
647 return chosen;
648 }
649
650 static void
651 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
652 uint64_t inst)
653 {
654 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
655 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
656
657 if (!(inst & QPU_WS)) {
658 scoreboard->last_waddr_a = waddr_add;
659 scoreboard->last_waddr_b = waddr_mul;
660 } else {
661 scoreboard->last_waddr_b = waddr_add;
662 scoreboard->last_waddr_a = waddr_mul;
663 }
664
665 if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
666 (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
667 scoreboard->last_sfu_write_tick = scoreboard->tick;
668 }
669
670 if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
671 waddr_mul == QPU_W_UNIFORMS_ADDRESS) {
672 scoreboard->last_uniforms_reset_tick = scoreboard->tick;
673 }
674
675 if (qpu_inst_is_tlb(inst))
676 scoreboard->tlb_locked = true;
677 }
678
679 static void
680 dump_state(struct list_head *schedule_list)
681 {
682 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
683 fprintf(stderr, " t=%4d: ", n->unblocked_time);
684 vc4_qpu_disasm(&n->inst->inst, 1);
685 fprintf(stderr, "\n");
686
687 for (int i = 0; i < n->child_count; i++) {
688 struct schedule_node *child = n->children[i].node;
689 if (!child)
690 continue;
691
692 fprintf(stderr, " - ");
693 vc4_qpu_disasm(&child->inst->inst, 1);
694 fprintf(stderr, " (%d parents, %c)\n",
695 child->parent_count,
696 n->children[i].write_after_read ? 'w' : 'r');
697 }
698 }
699 }
700
701 static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
702 {
703 if (waddr < 32)
704 return 2;
705
706 /* Apply some huge latency between texture fetch requests and getting
707 * their results back.
708 */
709 if (waddr == QPU_W_TMU0_S) {
710 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
711 return 100;
712 }
713 if (waddr == QPU_W_TMU1_S) {
714 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
715 return 100;
716 }
717
718 switch(waddr) {
719 case QPU_W_SFU_RECIP:
720 case QPU_W_SFU_RECIPSQRT:
721 case QPU_W_SFU_EXP:
722 case QPU_W_SFU_LOG:
723 return 3;
724 default:
725 return 1;
726 }
727 }
728
729 static uint32_t
730 instruction_latency(struct schedule_node *before, struct schedule_node *after)
731 {
732 uint64_t before_inst = before->inst->inst;
733 uint64_t after_inst = after->inst->inst;
734
735 return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
736 after_inst),
737 waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
738 after_inst));
739 }
740
741 /** Recursive computation of the delay member of a node. */
742 static void
743 compute_delay(struct schedule_node *n)
744 {
745 if (!n->child_count) {
746 n->delay = 1;
747 } else {
748 for (int i = 0; i < n->child_count; i++) {
749 if (!n->children[i].node->delay)
750 compute_delay(n->children[i].node);
751 n->delay = MAX2(n->delay,
752 n->children[i].node->delay +
753 instruction_latency(n, n->children[i].node));
754 }
755 }
756 }
757
758 static void
759 mark_instruction_scheduled(struct list_head *schedule_list,
760 uint32_t time,
761 struct schedule_node *node,
762 bool war_only)
763 {
764 if (!node)
765 return;
766
767 for (int i = node->child_count - 1; i >= 0; i--) {
768 struct schedule_node *child =
769 node->children[i].node;
770
771 if (!child)
772 continue;
773
774 if (war_only && !node->children[i].write_after_read)
775 continue;
776
777 /* If the requirement is only that the node not appear before
778 * the last read of its destination, then it can be scheduled
779 * immediately after (or paired with!) the thing reading the
780 * destination.
781 */
782 uint32_t latency = 0;
783 if (!war_only) {
784 latency = instruction_latency(node,
785 node->children[i].node);
786 }
787
788 child->unblocked_time = MAX2(child->unblocked_time,
789 time + latency);
790 child->parent_count--;
791 if (child->parent_count == 0)
792 list_add(&child->link, schedule_list);
793
794 node->children[i].node = NULL;
795 }
796 }
797
798 static uint32_t
799 schedule_instructions(struct vc4_compile *c,
800 struct choose_scoreboard *scoreboard,
801 struct qblock *block,
802 struct list_head *schedule_list,
803 enum quniform_contents *orig_uniform_contents,
804 uint32_t *orig_uniform_data,
805 uint32_t *next_uniform)
806 {
807 uint32_t time = 0;
808
809 if (debug) {
810 fprintf(stderr, "initial deps:\n");
811 dump_state(schedule_list);
812 fprintf(stderr, "\n");
813 }
814
815 /* Remove non-DAG heads from the list. */
816 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
817 if (n->parent_count != 0)
818 list_del(&n->link);
819 }
820
821 while (!list_empty(schedule_list)) {
822 struct schedule_node *chosen =
823 choose_instruction_to_schedule(scoreboard,
824 schedule_list,
825 NULL);
826 struct schedule_node *merge = NULL;
827
828 /* If there are no valid instructions to schedule, drop a NOP
829 * in.
830 */
831 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
832
833 if (debug) {
834 fprintf(stderr, "t=%4d: current list:\n",
835 time);
836 dump_state(schedule_list);
837 fprintf(stderr, "t=%4d: chose: ", time);
838 vc4_qpu_disasm(&inst, 1);
839 fprintf(stderr, "\n");
840 }
841
842 /* Schedule this instruction onto the QPU list. Also try to
843 * find an instruction to pair with it.
844 */
845 if (chosen) {
846 time = MAX2(chosen->unblocked_time, time);
847 list_del(&chosen->link);
848 mark_instruction_scheduled(schedule_list, time,
849 chosen, true);
850 if (chosen->uniform != -1) {
851 c->uniform_data[*next_uniform] =
852 orig_uniform_data[chosen->uniform];
853 c->uniform_contents[*next_uniform] =
854 orig_uniform_contents[chosen->uniform];
855 (*next_uniform)++;
856 }
857
858 merge = choose_instruction_to_schedule(scoreboard,
859 schedule_list,
860 chosen);
861 if (merge) {
862 time = MAX2(merge->unblocked_time, time);
863 list_del(&merge->link);
864 inst = qpu_merge_inst(inst, merge->inst->inst);
865 assert(inst != 0);
866 if (merge->uniform != -1) {
867 c->uniform_data[*next_uniform] =
868 orig_uniform_data[merge->uniform];
869 c->uniform_contents[*next_uniform] =
870 orig_uniform_contents[merge->uniform];
871 (*next_uniform)++;
872 }
873
874 if (debug) {
875 fprintf(stderr, "t=%4d: merging: ",
876 time);
877 vc4_qpu_disasm(&merge->inst->inst, 1);
878 fprintf(stderr, "\n");
879 fprintf(stderr, " resulting in: ");
880 vc4_qpu_disasm(&inst, 1);
881 fprintf(stderr, "\n");
882 }
883 }
884 }
885
886 if (debug) {
887 fprintf(stderr, "\n");
888 }
889
890 qpu_serialize_one_inst(c, inst);
891
892 update_scoreboard_for_chosen(scoreboard, inst);
893
894 /* Now that we've scheduled a new instruction, some of its
895 * children can be promoted to the list of instructions ready to
896 * be scheduled. Update the children's unblocked time for this
897 * DAG edge as we do so.
898 */
899 mark_instruction_scheduled(schedule_list, time, chosen, false);
900 mark_instruction_scheduled(schedule_list, time, merge, false);
901
902 scoreboard->tick++;
903 time++;
904
905 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) {
906 block->branch_qpu_ip = c->qpu_inst_count - 1;
907 /* Fill the delay slots.
908 *
909 * We should fill these with actual instructions,
910 * instead, but that will probably need to be done
911 * after this, once we know what the leading
912 * instructions of the successors are (so we can
913 * handle A/B register file write latency)
914 */
915 inst = qpu_NOP();
916 update_scoreboard_for_chosen(scoreboard, inst);
917 qpu_serialize_one_inst(c, inst);
918 qpu_serialize_one_inst(c, inst);
919 qpu_serialize_one_inst(c, inst);
920 } else if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_THREAD_SWITCH ||
921 QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LAST_THREAD_SWITCH) {
922 /* The thread switch occurs after two delay slots. We
923 * should fit things in these slots, but we don't
924 * currently.
925 */
926 inst = qpu_NOP();
927 update_scoreboard_for_chosen(scoreboard, inst);
928 qpu_serialize_one_inst(c, inst);
929 qpu_serialize_one_inst(c, inst);
930 }
931 }
932
933 return time;
934 }
935
936 static uint32_t
937 qpu_schedule_instructions_block(struct vc4_compile *c,
938 struct choose_scoreboard *scoreboard,
939 struct qblock *block,
940 enum quniform_contents *orig_uniform_contents,
941 uint32_t *orig_uniform_data,
942 uint32_t *next_uniform)
943 {
944 void *mem_ctx = ralloc_context(NULL);
945 struct list_head schedule_list;
946
947 list_inithead(&schedule_list);
948
949 /* Wrap each instruction in a scheduler structure. */
950 uint32_t next_sched_uniform = *next_uniform;
951 while (!list_empty(&block->qpu_inst_list)) {
952 struct queued_qpu_inst *inst =
953 (struct queued_qpu_inst *)block->qpu_inst_list.next;
954 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
955
956 n->inst = inst;
957
958 if (reads_uniform(inst->inst)) {
959 n->uniform = next_sched_uniform++;
960 } else {
961 n->uniform = -1;
962 }
963 list_del(&inst->link);
964 list_addtail(&n->link, &schedule_list);
965 }
966
967 calculate_forward_deps(c, &schedule_list);
968 calculate_reverse_deps(c, &schedule_list);
969
970 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
971 compute_delay(n);
972 }
973
974 uint32_t cycles = schedule_instructions(c, scoreboard, block,
975 &schedule_list,
976 orig_uniform_contents,
977 orig_uniform_data,
978 next_uniform);
979
980 ralloc_free(mem_ctx);
981
982 return cycles;
983 }
984
985 static void
986 qpu_set_branch_targets(struct vc4_compile *c)
987 {
988 qir_for_each_block(block, c) {
989 /* The end block of the program has no branch. */
990 if (!block->successors[0])
991 continue;
992
993 /* If there was no branch instruction, then the successor
994 * block must follow immediately after this one.
995 */
996 if (block->branch_qpu_ip == ~0) {
997 assert(block->end_qpu_ip + 1 ==
998 block->successors[0]->start_qpu_ip);
999 continue;
1000 }
1001
1002 /* Set the branch target for the block that doesn't follow
1003 * immediately after ours.
1004 */
1005 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
1006 assert(QPU_GET_FIELD(*branch_inst, QPU_SIG) == QPU_SIG_BRANCH);
1007 assert(QPU_GET_FIELD(*branch_inst, QPU_BRANCH_TARGET) == 0);
1008
1009 uint32_t branch_target =
1010 (block->successors[0]->start_qpu_ip -
1011 (block->branch_qpu_ip + 4)) * sizeof(uint64_t);
1012 *branch_inst = (*branch_inst |
1013 QPU_SET_FIELD(branch_target, QPU_BRANCH_TARGET));
1014
1015 /* Make sure that the if-we-don't-jump successor was scheduled
1016 * just after the delay slots.
1017 */
1018 if (block->successors[1]) {
1019 assert(block->successors[1]->start_qpu_ip ==
1020 block->branch_qpu_ip + 4);
1021 }
1022 }
1023 }
1024
1025 uint32_t
1026 qpu_schedule_instructions(struct vc4_compile *c)
1027 {
1028 /* We reorder the uniforms as we schedule instructions, so save the
1029 * old data off and replace it.
1030 */
1031 uint32_t *uniform_data = c->uniform_data;
1032 enum quniform_contents *uniform_contents = c->uniform_contents;
1033 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1034 c->num_uniforms);
1035 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1036 c->uniform_array_size = c->num_uniforms;
1037 uint32_t next_uniform = 0;
1038
1039 struct choose_scoreboard scoreboard;
1040 memset(&scoreboard, 0, sizeof(scoreboard));
1041 scoreboard.last_waddr_a = ~0;
1042 scoreboard.last_waddr_b = ~0;
1043 scoreboard.last_sfu_write_tick = -10;
1044 scoreboard.last_uniforms_reset_tick = -10;
1045
1046 if (debug) {
1047 fprintf(stderr, "Pre-schedule instructions\n");
1048 qir_for_each_block(block, c) {
1049 fprintf(stderr, "BLOCK %d\n", block->index);
1050 list_for_each_entry(struct queued_qpu_inst, q,
1051 &block->qpu_inst_list, link) {
1052 vc4_qpu_disasm(&q->inst, 1);
1053 fprintf(stderr, "\n");
1054 }
1055 }
1056 fprintf(stderr, "\n");
1057 }
1058
1059 uint32_t cycles = 0;
1060 qir_for_each_block(block, c) {
1061 block->start_qpu_ip = c->qpu_inst_count;
1062 block->branch_qpu_ip = ~0;
1063
1064 cycles += qpu_schedule_instructions_block(c,
1065 &scoreboard,
1066 block,
1067 uniform_contents,
1068 uniform_data,
1069 &next_uniform);
1070
1071 block->end_qpu_ip = c->qpu_inst_count - 1;
1072 }
1073
1074 qpu_set_branch_targets(c);
1075
1076 assert(next_uniform == c->num_uniforms);
1077
1078 if (debug) {
1079 fprintf(stderr, "Post-schedule instructions\n");
1080 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
1081 fprintf(stderr, "\n");
1082 }
1083
1084 return cycles;
1085 }