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vc4: Avoid false scheduling dependencies for LOAD_IMMs.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file vc4_qpu_schedule.c
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "vc4_qir.h"
38 #include "vc4_qpu.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct queued_qpu_inst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68
69 /**
70 * Which uniform from uniform_data[] this instruction read, or -1 if
71 * not reading a uniform.
72 */
73 int uniform;
74 };
75
76 struct schedule_node_child {
77 struct schedule_node *node;
78 bool write_after_read;
79 };
80
81 /* When walking the instructions in reverse, we need to swap before/after in
82 * add_dep().
83 */
84 enum direction { F, R };
85
86 struct schedule_state {
87 struct schedule_node *last_r[6];
88 struct schedule_node *last_ra[32];
89 struct schedule_node *last_rb[32];
90 struct schedule_node *last_sf;
91 struct schedule_node *last_vpm_read;
92 struct schedule_node *last_tmu_write;
93 struct schedule_node *last_tlb;
94 struct schedule_node *last_vpm;
95 struct schedule_node *last_uniforms_reset;
96 enum direction dir;
97 /* Estimated cycle when the current instruction would start. */
98 uint32_t time;
99 };
100
101 static void
102 add_dep(struct schedule_state *state,
103 struct schedule_node *before,
104 struct schedule_node *after,
105 bool write)
106 {
107 bool write_after_read = !write && state->dir == R;
108
109 if (!before || !after)
110 return;
111
112 assert(before != after);
113
114 if (state->dir == R) {
115 struct schedule_node *t = before;
116 before = after;
117 after = t;
118 }
119
120 for (int i = 0; i < before->child_count; i++) {
121 if (before->children[i].node == after &&
122 (before->children[i].write_after_read == write_after_read)) {
123 return;
124 }
125 }
126
127 if (before->child_array_size <= before->child_count) {
128 before->child_array_size = MAX2(before->child_array_size * 2, 16);
129 before->children = reralloc(before, before->children,
130 struct schedule_node_child,
131 before->child_array_size);
132 }
133
134 before->children[before->child_count].node = after;
135 before->children[before->child_count].write_after_read =
136 write_after_read;
137 before->child_count++;
138 after->parent_count++;
139 }
140
141 static void
142 add_read_dep(struct schedule_state *state,
143 struct schedule_node *before,
144 struct schedule_node *after)
145 {
146 add_dep(state, before, after, false);
147 }
148
149 static void
150 add_write_dep(struct schedule_state *state,
151 struct schedule_node **before,
152 struct schedule_node *after)
153 {
154 add_dep(state, *before, after, true);
155 *before = after;
156 }
157
158 static bool
159 qpu_writes_r4(uint64_t inst)
160 {
161 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
162
163 switch(sig) {
164 case QPU_SIG_COLOR_LOAD:
165 case QPU_SIG_LOAD_TMU0:
166 case QPU_SIG_LOAD_TMU1:
167 case QPU_SIG_ALPHA_MASK_LOAD:
168 return true;
169 default:
170 return false;
171 }
172 }
173
174 static void
175 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
176 uint32_t raddr, bool is_a)
177 {
178 switch (raddr) {
179 case QPU_R_VARY:
180 add_write_dep(state, &state->last_r[5], n);
181 break;
182
183 case QPU_R_VPM:
184 add_write_dep(state, &state->last_vpm_read, n);
185 break;
186
187 case QPU_R_UNIF:
188 add_read_dep(state, state->last_uniforms_reset, n);
189 break;
190
191 case QPU_R_NOP:
192 case QPU_R_ELEM_QPU:
193 case QPU_R_XY_PIXEL_COORD:
194 case QPU_R_MS_REV_FLAGS:
195 break;
196
197 default:
198 if (raddr < 32) {
199 if (is_a)
200 add_read_dep(state, state->last_ra[raddr], n);
201 else
202 add_read_dep(state, state->last_rb[raddr], n);
203 } else {
204 fprintf(stderr, "unknown raddr %d\n", raddr);
205 abort();
206 }
207 break;
208 }
209 }
210
211 static bool
212 is_tmu_write(uint32_t waddr)
213 {
214 switch (waddr) {
215 case QPU_W_TMU0_S:
216 case QPU_W_TMU0_T:
217 case QPU_W_TMU0_R:
218 case QPU_W_TMU0_B:
219 case QPU_W_TMU1_S:
220 case QPU_W_TMU1_T:
221 case QPU_W_TMU1_R:
222 case QPU_W_TMU1_B:
223 return true;
224 default:
225 return false;
226 }
227 }
228
229 static bool
230 reads_uniform(uint64_t inst)
231 {
232 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
233 return false;
234
235 return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
236 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
237 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
238 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
239 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
240 }
241
242 static void
243 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
244 uint32_t mux)
245 {
246 if (mux != QPU_MUX_A && mux != QPU_MUX_B)
247 add_read_dep(state, state->last_r[mux], n);
248 }
249
250
251 static void
252 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
253 uint32_t waddr, bool is_add)
254 {
255 uint64_t inst = n->inst->inst;
256 bool is_a = is_add ^ ((inst & QPU_WS) != 0);
257
258 if (waddr < 32) {
259 if (is_a) {
260 add_write_dep(state, &state->last_ra[waddr], n);
261 } else {
262 add_write_dep(state, &state->last_rb[waddr], n);
263 }
264 } else if (is_tmu_write(waddr)) {
265 add_write_dep(state, &state->last_tmu_write, n);
266 add_read_dep(state, state->last_uniforms_reset, n);
267 } else if (qpu_waddr_is_tlb(waddr) ||
268 waddr == QPU_W_MS_FLAGS) {
269 add_write_dep(state, &state->last_tlb, n);
270 } else {
271 switch (waddr) {
272 case QPU_W_ACC0:
273 case QPU_W_ACC1:
274 case QPU_W_ACC2:
275 case QPU_W_ACC3:
276 case QPU_W_ACC5:
277 add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
278 n);
279 break;
280
281 case QPU_W_VPM:
282 add_write_dep(state, &state->last_vpm, n);
283 break;
284
285 case QPU_W_VPMVCD_SETUP:
286 if (is_a)
287 add_write_dep(state, &state->last_vpm_read, n);
288 else
289 add_write_dep(state, &state->last_vpm, n);
290 break;
291
292 case QPU_W_SFU_RECIP:
293 case QPU_W_SFU_RECIPSQRT:
294 case QPU_W_SFU_EXP:
295 case QPU_W_SFU_LOG:
296 add_write_dep(state, &state->last_r[4], n);
297 break;
298
299 case QPU_W_TLB_STENCIL_SETUP:
300 /* This isn't a TLB operation that does things like
301 * implicitly lock the scoreboard, but it does have to
302 * appear before TLB_Z, and each of the TLB_STENCILs
303 * have to schedule in the same order relative to each
304 * other.
305 */
306 add_write_dep(state, &state->last_tlb, n);
307 break;
308
309 case QPU_W_MS_FLAGS:
310 add_write_dep(state, &state->last_tlb, n);
311 break;
312
313 case QPU_W_UNIFORMS_ADDRESS:
314 add_write_dep(state, &state->last_uniforms_reset, n);
315 break;
316
317 case QPU_W_NOP:
318 break;
319
320 default:
321 fprintf(stderr, "Unknown waddr %d\n", waddr);
322 abort();
323 }
324 }
325 }
326
327 static void
328 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
329 uint32_t cond)
330 {
331 switch (cond) {
332 case QPU_COND_NEVER:
333 case QPU_COND_ALWAYS:
334 break;
335 default:
336 add_read_dep(state, state->last_sf, n);
337 break;
338 }
339 }
340
341 /**
342 * Common code for dependencies that need to be tracked both forward and
343 * backward.
344 *
345 * This is for things like "all reads of r4 have to happen between the r4
346 * writes that surround them".
347 */
348 static void
349 calculate_deps(struct schedule_state *state, struct schedule_node *n)
350 {
351 uint64_t inst = n->inst->inst;
352 uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
353 uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
354 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
355 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
356 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
357 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
358 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
359 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
360 uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
361 uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
362 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
363
364 if (sig != QPU_SIG_LOAD_IMM) {
365 process_raddr_deps(state, n, raddr_a, true);
366 if (sig != QPU_SIG_SMALL_IMM &&
367 sig != QPU_SIG_BRANCH)
368 process_raddr_deps(state, n, raddr_b, false);
369 }
370
371 if (add_op != QPU_A_NOP) {
372 process_mux_deps(state, n, add_a);
373 process_mux_deps(state, n, add_b);
374 }
375 if (mul_op != QPU_M_NOP) {
376 process_mux_deps(state, n, mul_a);
377 process_mux_deps(state, n, mul_b);
378 }
379
380 process_waddr_deps(state, n, waddr_add, true);
381 process_waddr_deps(state, n, waddr_mul, false);
382 if (qpu_writes_r4(inst))
383 add_write_dep(state, &state->last_r[4], n);
384
385 switch (sig) {
386 case QPU_SIG_SW_BREAKPOINT:
387 case QPU_SIG_NONE:
388 case QPU_SIG_SMALL_IMM:
389 case QPU_SIG_LOAD_IMM:
390 break;
391
392 case QPU_SIG_THREAD_SWITCH:
393 case QPU_SIG_LAST_THREAD_SWITCH:
394 /* All accumulator contents and flags are undefined after the
395 * switch.
396 */
397 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
398 add_write_dep(state, &state->last_r[i], n);
399 add_write_dep(state, &state->last_sf, n);
400
401 /* Scoreboard-locking operations have to stay after the last
402 * thread switch.
403 */
404 add_write_dep(state, &state->last_tlb, n);
405
406 add_write_dep(state, &state->last_tmu_write, n);
407 break;
408
409 case QPU_SIG_LOAD_TMU0:
410 case QPU_SIG_LOAD_TMU1:
411 /* TMU loads are coming from a FIFO, so ordering is important.
412 */
413 add_write_dep(state, &state->last_tmu_write, n);
414 break;
415
416 case QPU_SIG_COLOR_LOAD:
417 add_read_dep(state, state->last_tlb, n);
418 break;
419
420 case QPU_SIG_BRANCH:
421 add_read_dep(state, state->last_sf, n);
422 break;
423
424 case QPU_SIG_PROG_END:
425 case QPU_SIG_WAIT_FOR_SCOREBOARD:
426 case QPU_SIG_SCOREBOARD_UNLOCK:
427 case QPU_SIG_COVERAGE_LOAD:
428 case QPU_SIG_COLOR_LOAD_END:
429 case QPU_SIG_ALPHA_MASK_LOAD:
430 fprintf(stderr, "Unhandled signal bits %d\n", sig);
431 abort();
432 }
433
434 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
435 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
436 if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
437 add_write_dep(state, &state->last_sf, n);
438 }
439
440 static void
441 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
442 {
443 struct schedule_state state;
444
445 memset(&state, 0, sizeof(state));
446 state.dir = F;
447
448 list_for_each_entry(struct schedule_node, node, schedule_list, link)
449 calculate_deps(&state, node);
450 }
451
452 static void
453 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
454 {
455 struct list_head *node;
456 struct schedule_state state;
457
458 memset(&state, 0, sizeof(state));
459 state.dir = R;
460
461 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
462 calculate_deps(&state, (struct schedule_node *)node);
463 }
464 }
465
466 struct choose_scoreboard {
467 int tick;
468 int last_sfu_write_tick;
469 int last_uniforms_reset_tick;
470 uint32_t last_waddr_a, last_waddr_b;
471 bool tlb_locked;
472 };
473
474 static bool
475 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
476 {
477 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
478 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
479 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
480
481 /* Full immediate loads don't read any registers. */
482 if (sig == QPU_SIG_LOAD_IMM)
483 return false;
484
485 uint32_t src_muxes[] = {
486 QPU_GET_FIELD(inst, QPU_ADD_A),
487 QPU_GET_FIELD(inst, QPU_ADD_B),
488 QPU_GET_FIELD(inst, QPU_MUL_A),
489 QPU_GET_FIELD(inst, QPU_MUL_B),
490 };
491 for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
492 if ((src_muxes[i] == QPU_MUX_A &&
493 raddr_a < 32 &&
494 scoreboard->last_waddr_a == raddr_a) ||
495 (src_muxes[i] == QPU_MUX_B &&
496 sig != QPU_SIG_SMALL_IMM &&
497 raddr_b < 32 &&
498 scoreboard->last_waddr_b == raddr_b)) {
499 return true;
500 }
501
502 if (src_muxes[i] == QPU_MUX_R4) {
503 if (scoreboard->tick -
504 scoreboard->last_sfu_write_tick <= 2) {
505 return true;
506 }
507 }
508 }
509
510 if (sig == QPU_SIG_SMALL_IMM &&
511 QPU_GET_FIELD(inst, QPU_SMALL_IMM) >= QPU_SMALL_IMM_MUL_ROT) {
512 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
513 uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
514
515 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
516 scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
517 scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
518 scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
519 return true;
520 }
521 }
522
523 if (reads_uniform(inst) &&
524 scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
525 return true;
526 }
527
528 return false;
529 }
530
531 static bool
532 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
533 {
534 return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
535 }
536
537 static int
538 get_instruction_priority(uint64_t inst)
539 {
540 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
541 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
542 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
543 uint32_t baseline_score;
544 uint32_t next_score = 0;
545
546 /* Schedule TLB operations as late as possible, to get more
547 * parallelism between shaders.
548 */
549 if (qpu_inst_is_tlb(inst))
550 return next_score;
551 next_score++;
552
553 /* Schedule texture read results collection late to hide latency. */
554 if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
555 return next_score;
556 next_score++;
557
558 /* Default score for things that aren't otherwise special. */
559 baseline_score = next_score;
560 next_score++;
561
562 /* Schedule texture read setup early to hide their latency better. */
563 if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
564 return next_score;
565 next_score++;
566
567 return baseline_score;
568 }
569
570 static struct schedule_node *
571 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
572 struct list_head *schedule_list,
573 struct schedule_node *prev_inst)
574 {
575 struct schedule_node *chosen = NULL;
576 int chosen_prio = 0;
577
578 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
579 uint64_t inst = n->inst->inst;
580
581 /* Don't choose the branch instruction until it's the last one
582 * left. XXX: We could potentially choose it before it's the
583 * last one, if the remaining instructions fit in the delay
584 * slots.
585 */
586 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
587 !list_is_singular(schedule_list)) {
588 continue;
589 }
590
591 /* "An instruction must not read from a location in physical
592 * regfile A or B that was written to by the previous
593 * instruction."
594 */
595 if (reads_too_soon_after_write(scoreboard, inst))
596 continue;
597
598 /* "A scoreboard wait must not occur in the first two
599 * instructions of a fragment shader. This is either the
600 * explicit Wait for Scoreboard signal or an implicit wait
601 * with the first tile-buffer read or write instruction."
602 */
603 if (pixel_scoreboard_too_soon(scoreboard, inst))
604 continue;
605
606 /* If we're trying to pair with another instruction, check
607 * that they're compatible.
608 */
609 if (prev_inst) {
610 if (prev_inst->uniform != -1 && n->uniform != -1)
611 continue;
612
613 /* Don't merge in something that will lock the TLB.
614 * Hopwefully what we have in inst will release some
615 * other instructions, allowing us to delay the
616 * TLB-locking instruction until later.
617 */
618 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
619 continue;
620
621 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
622 if (!inst)
623 continue;
624 }
625
626 int prio = get_instruction_priority(inst);
627
628 /* Found a valid instruction. If nothing better comes along,
629 * this one works.
630 */
631 if (!chosen) {
632 chosen = n;
633 chosen_prio = prio;
634 continue;
635 }
636
637 if (prio > chosen_prio) {
638 chosen = n;
639 chosen_prio = prio;
640 } else if (prio < chosen_prio) {
641 continue;
642 }
643
644 if (n->delay > chosen->delay) {
645 chosen = n;
646 chosen_prio = prio;
647 } else if (n->delay < chosen->delay) {
648 continue;
649 }
650 }
651
652 return chosen;
653 }
654
655 static void
656 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
657 uint64_t inst)
658 {
659 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
660 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
661
662 if (!(inst & QPU_WS)) {
663 scoreboard->last_waddr_a = waddr_add;
664 scoreboard->last_waddr_b = waddr_mul;
665 } else {
666 scoreboard->last_waddr_b = waddr_add;
667 scoreboard->last_waddr_a = waddr_mul;
668 }
669
670 if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
671 (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
672 scoreboard->last_sfu_write_tick = scoreboard->tick;
673 }
674
675 if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
676 waddr_mul == QPU_W_UNIFORMS_ADDRESS) {
677 scoreboard->last_uniforms_reset_tick = scoreboard->tick;
678 }
679
680 if (qpu_inst_is_tlb(inst))
681 scoreboard->tlb_locked = true;
682 }
683
684 static void
685 dump_state(struct list_head *schedule_list)
686 {
687 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
688 fprintf(stderr, " t=%4d: ", n->unblocked_time);
689 vc4_qpu_disasm(&n->inst->inst, 1);
690 fprintf(stderr, "\n");
691
692 for (int i = 0; i < n->child_count; i++) {
693 struct schedule_node *child = n->children[i].node;
694 if (!child)
695 continue;
696
697 fprintf(stderr, " - ");
698 vc4_qpu_disasm(&child->inst->inst, 1);
699 fprintf(stderr, " (%d parents, %c)\n",
700 child->parent_count,
701 n->children[i].write_after_read ? 'w' : 'r');
702 }
703 }
704 }
705
706 static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
707 {
708 if (waddr < 32)
709 return 2;
710
711 /* Apply some huge latency between texture fetch requests and getting
712 * their results back.
713 *
714 * FIXME: This is actually pretty bogus. If we do:
715 *
716 * mov tmu0_s, a
717 * <a bit of math>
718 * mov tmu0_s, b
719 * load_tmu0
720 * <more math>
721 * load_tmu0
722 *
723 * we count that as worse than
724 *
725 * mov tmu0_s, a
726 * mov tmu0_s, b
727 * <lots of math>
728 * load_tmu0
729 * <more math>
730 * load_tmu0
731 *
732 * because we associate the first load_tmu0 with the *second* tmu0_s.
733 */
734 if (waddr == QPU_W_TMU0_S) {
735 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
736 return 100;
737 }
738 if (waddr == QPU_W_TMU1_S) {
739 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
740 return 100;
741 }
742
743 switch(waddr) {
744 case QPU_W_SFU_RECIP:
745 case QPU_W_SFU_RECIPSQRT:
746 case QPU_W_SFU_EXP:
747 case QPU_W_SFU_LOG:
748 return 3;
749 default:
750 return 1;
751 }
752 }
753
754 static uint32_t
755 instruction_latency(struct schedule_node *before, struct schedule_node *after)
756 {
757 uint64_t before_inst = before->inst->inst;
758 uint64_t after_inst = after->inst->inst;
759
760 return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
761 after_inst),
762 waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
763 after_inst));
764 }
765
766 /** Recursive computation of the delay member of a node. */
767 static void
768 compute_delay(struct schedule_node *n)
769 {
770 if (!n->child_count) {
771 n->delay = 1;
772 } else {
773 for (int i = 0; i < n->child_count; i++) {
774 if (!n->children[i].node->delay)
775 compute_delay(n->children[i].node);
776 n->delay = MAX2(n->delay,
777 n->children[i].node->delay +
778 instruction_latency(n, n->children[i].node));
779 }
780 }
781 }
782
783 static void
784 mark_instruction_scheduled(struct list_head *schedule_list,
785 uint32_t time,
786 struct schedule_node *node,
787 bool war_only)
788 {
789 if (!node)
790 return;
791
792 for (int i = node->child_count - 1; i >= 0; i--) {
793 struct schedule_node *child =
794 node->children[i].node;
795
796 if (!child)
797 continue;
798
799 if (war_only && !node->children[i].write_after_read)
800 continue;
801
802 /* If the requirement is only that the node not appear before
803 * the last read of its destination, then it can be scheduled
804 * immediately after (or paired with!) the thing reading the
805 * destination.
806 */
807 uint32_t latency = 0;
808 if (!war_only) {
809 latency = instruction_latency(node,
810 node->children[i].node);
811 }
812
813 child->unblocked_time = MAX2(child->unblocked_time,
814 time + latency);
815 child->parent_count--;
816 if (child->parent_count == 0)
817 list_add(&child->link, schedule_list);
818
819 node->children[i].node = NULL;
820 }
821 }
822
823 static uint32_t
824 schedule_instructions(struct vc4_compile *c,
825 struct choose_scoreboard *scoreboard,
826 struct qblock *block,
827 struct list_head *schedule_list,
828 enum quniform_contents *orig_uniform_contents,
829 uint32_t *orig_uniform_data,
830 uint32_t *next_uniform)
831 {
832 uint32_t time = 0;
833
834 if (debug) {
835 fprintf(stderr, "initial deps:\n");
836 dump_state(schedule_list);
837 fprintf(stderr, "\n");
838 }
839
840 /* Remove non-DAG heads from the list. */
841 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
842 if (n->parent_count != 0)
843 list_del(&n->link);
844 }
845
846 while (!list_empty(schedule_list)) {
847 struct schedule_node *chosen =
848 choose_instruction_to_schedule(scoreboard,
849 schedule_list,
850 NULL);
851 struct schedule_node *merge = NULL;
852
853 /* If there are no valid instructions to schedule, drop a NOP
854 * in.
855 */
856 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
857
858 if (debug) {
859 fprintf(stderr, "t=%4d: current list:\n",
860 time);
861 dump_state(schedule_list);
862 fprintf(stderr, "t=%4d: chose: ", time);
863 vc4_qpu_disasm(&inst, 1);
864 fprintf(stderr, "\n");
865 }
866
867 /* Schedule this instruction onto the QPU list. Also try to
868 * find an instruction to pair with it.
869 */
870 if (chosen) {
871 time = MAX2(chosen->unblocked_time, time);
872 list_del(&chosen->link);
873 mark_instruction_scheduled(schedule_list, time,
874 chosen, true);
875 if (chosen->uniform != -1) {
876 c->uniform_data[*next_uniform] =
877 orig_uniform_data[chosen->uniform];
878 c->uniform_contents[*next_uniform] =
879 orig_uniform_contents[chosen->uniform];
880 (*next_uniform)++;
881 }
882
883 merge = choose_instruction_to_schedule(scoreboard,
884 schedule_list,
885 chosen);
886 if (merge) {
887 time = MAX2(merge->unblocked_time, time);
888 list_del(&merge->link);
889 inst = qpu_merge_inst(inst, merge->inst->inst);
890 assert(inst != 0);
891 if (merge->uniform != -1) {
892 c->uniform_data[*next_uniform] =
893 orig_uniform_data[merge->uniform];
894 c->uniform_contents[*next_uniform] =
895 orig_uniform_contents[merge->uniform];
896 (*next_uniform)++;
897 }
898
899 if (debug) {
900 fprintf(stderr, "t=%4d: merging: ",
901 time);
902 vc4_qpu_disasm(&merge->inst->inst, 1);
903 fprintf(stderr, "\n");
904 fprintf(stderr, " resulting in: ");
905 vc4_qpu_disasm(&inst, 1);
906 fprintf(stderr, "\n");
907 }
908 }
909 }
910
911 if (debug) {
912 fprintf(stderr, "\n");
913 }
914
915 qpu_serialize_one_inst(c, inst);
916
917 update_scoreboard_for_chosen(scoreboard, inst);
918
919 /* Now that we've scheduled a new instruction, some of its
920 * children can be promoted to the list of instructions ready to
921 * be scheduled. Update the children's unblocked time for this
922 * DAG edge as we do so.
923 */
924 mark_instruction_scheduled(schedule_list, time, chosen, false);
925 mark_instruction_scheduled(schedule_list, time, merge, false);
926
927 scoreboard->tick++;
928 time++;
929
930 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) {
931 block->branch_qpu_ip = c->qpu_inst_count - 1;
932 /* Fill the delay slots.
933 *
934 * We should fill these with actual instructions,
935 * instead, but that will probably need to be done
936 * after this, once we know what the leading
937 * instructions of the successors are (so we can
938 * handle A/B register file write latency)
939 */
940 inst = qpu_NOP();
941 update_scoreboard_for_chosen(scoreboard, inst);
942 qpu_serialize_one_inst(c, inst);
943 qpu_serialize_one_inst(c, inst);
944 qpu_serialize_one_inst(c, inst);
945 } else if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_THREAD_SWITCH ||
946 QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LAST_THREAD_SWITCH) {
947 /* The thread switch occurs after two delay slots. We
948 * should fit things in these slots, but we don't
949 * currently.
950 */
951 inst = qpu_NOP();
952 update_scoreboard_for_chosen(scoreboard, inst);
953 qpu_serialize_one_inst(c, inst);
954 qpu_serialize_one_inst(c, inst);
955 }
956 }
957
958 return time;
959 }
960
961 static uint32_t
962 qpu_schedule_instructions_block(struct vc4_compile *c,
963 struct choose_scoreboard *scoreboard,
964 struct qblock *block,
965 enum quniform_contents *orig_uniform_contents,
966 uint32_t *orig_uniform_data,
967 uint32_t *next_uniform)
968 {
969 void *mem_ctx = ralloc_context(NULL);
970 struct list_head schedule_list;
971
972 list_inithead(&schedule_list);
973
974 /* Wrap each instruction in a scheduler structure. */
975 uint32_t next_sched_uniform = *next_uniform;
976 while (!list_empty(&block->qpu_inst_list)) {
977 struct queued_qpu_inst *inst =
978 (struct queued_qpu_inst *)block->qpu_inst_list.next;
979 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
980
981 n->inst = inst;
982
983 if (reads_uniform(inst->inst)) {
984 n->uniform = next_sched_uniform++;
985 } else {
986 n->uniform = -1;
987 }
988 list_del(&inst->link);
989 list_addtail(&n->link, &schedule_list);
990 }
991
992 calculate_forward_deps(c, &schedule_list);
993 calculate_reverse_deps(c, &schedule_list);
994
995 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
996 compute_delay(n);
997 }
998
999 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1000 &schedule_list,
1001 orig_uniform_contents,
1002 orig_uniform_data,
1003 next_uniform);
1004
1005 ralloc_free(mem_ctx);
1006
1007 return cycles;
1008 }
1009
1010 static void
1011 qpu_set_branch_targets(struct vc4_compile *c)
1012 {
1013 qir_for_each_block(block, c) {
1014 /* The end block of the program has no branch. */
1015 if (!block->successors[0])
1016 continue;
1017
1018 /* If there was no branch instruction, then the successor
1019 * block must follow immediately after this one.
1020 */
1021 if (block->branch_qpu_ip == ~0) {
1022 assert(block->end_qpu_ip + 1 ==
1023 block->successors[0]->start_qpu_ip);
1024 continue;
1025 }
1026
1027 /* Set the branch target for the block that doesn't follow
1028 * immediately after ours.
1029 */
1030 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
1031 assert(QPU_GET_FIELD(*branch_inst, QPU_SIG) == QPU_SIG_BRANCH);
1032 assert(QPU_GET_FIELD(*branch_inst, QPU_BRANCH_TARGET) == 0);
1033
1034 uint32_t branch_target =
1035 (block->successors[0]->start_qpu_ip -
1036 (block->branch_qpu_ip + 4)) * sizeof(uint64_t);
1037 *branch_inst = (*branch_inst |
1038 QPU_SET_FIELD(branch_target, QPU_BRANCH_TARGET));
1039
1040 /* Make sure that the if-we-don't-jump successor was scheduled
1041 * just after the delay slots.
1042 */
1043 if (block->successors[1]) {
1044 assert(block->successors[1]->start_qpu_ip ==
1045 block->branch_qpu_ip + 4);
1046 }
1047 }
1048 }
1049
1050 uint32_t
1051 qpu_schedule_instructions(struct vc4_compile *c)
1052 {
1053 /* We reorder the uniforms as we schedule instructions, so save the
1054 * old data off and replace it.
1055 */
1056 uint32_t *uniform_data = c->uniform_data;
1057 enum quniform_contents *uniform_contents = c->uniform_contents;
1058 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1059 c->num_uniforms);
1060 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1061 c->uniform_array_size = c->num_uniforms;
1062 uint32_t next_uniform = 0;
1063
1064 struct choose_scoreboard scoreboard;
1065 memset(&scoreboard, 0, sizeof(scoreboard));
1066 scoreboard.last_waddr_a = ~0;
1067 scoreboard.last_waddr_b = ~0;
1068 scoreboard.last_sfu_write_tick = -10;
1069 scoreboard.last_uniforms_reset_tick = -10;
1070
1071 if (debug) {
1072 fprintf(stderr, "Pre-schedule instructions\n");
1073 qir_for_each_block(block, c) {
1074 fprintf(stderr, "BLOCK %d\n", block->index);
1075 list_for_each_entry(struct queued_qpu_inst, q,
1076 &block->qpu_inst_list, link) {
1077 vc4_qpu_disasm(&q->inst, 1);
1078 fprintf(stderr, "\n");
1079 }
1080 }
1081 fprintf(stderr, "\n");
1082 }
1083
1084 uint32_t cycles = 0;
1085 qir_for_each_block(block, c) {
1086 block->start_qpu_ip = c->qpu_inst_count;
1087 block->branch_qpu_ip = ~0;
1088
1089 cycles += qpu_schedule_instructions_block(c,
1090 &scoreboard,
1091 block,
1092 uniform_contents,
1093 uniform_data,
1094 &next_uniform);
1095
1096 block->end_qpu_ip = c->qpu_inst_count - 1;
1097 }
1098
1099 qpu_set_branch_targets(c);
1100
1101 assert(next_uniform == c->num_uniforms);
1102
1103 if (debug) {
1104 fprintf(stderr, "Post-schedule instructions\n");
1105 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
1106 fprintf(stderr, "\n");
1107 }
1108
1109 return cycles;
1110 }