src/gallium/drivers/vc4/vc4_qpu_schedule.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * @file vc4_qpu_schedule.c
  27  *
  28  * The basic model of the list scheduler is to take a basic block, compute a
  29  * DAG of the dependencies, and make a list of the DAG heads.  Heuristically
  30  * pick a DAG head, then put all the children that are now DAG heads into the
  31  * list of things to schedule.
  32  *
  33  * The goal of scheduling here is to pack pairs of operations together in a
  34  * single QPU instruction.
  35  */
  36
  37 #include "vc4_qir.h"
  38 #include "vc4_qpu.h"
  39 #include "util/ralloc.h"
  40
  41 static bool debug;
  42
  43 struct schedule_node_child;
  44
  45 struct schedule_node {
  46         struct list_head link;
  47         struct queued_qpu_inst *inst;
  48         struct schedule_node_child *children;
  49         uint32_t child_count;
  50         uint32_t child_array_size;
  51         uint32_t parent_count;
  52
  53         /* Longest cycles + instruction_latency() of any parent of this node. */
  54         uint32_t unblocked_time;
  55
  56         /**
  57          * Minimum number of cycles from scheduling this instruction until the
  58          * end of the program, based on the slowest dependency chain through
  59          * the children.
  60          */
  61         uint32_t delay;
  62
  63         /**
  64          * cycles between this instruction being scheduled and when its result
  65          * can be consumed.
  66          */
  67         uint32_t latency;
  68
  69         /**
  70          * Which uniform from uniform_data[] this instruction read, or -1 if
  71          * not reading a uniform.
  72          */
  73         int uniform;
  74 };
  75
  76 struct schedule_node_child {
  77         struct schedule_node *node;
  78         bool write_after_read;
  79 };
  80
  81 /* When walking the instructions in reverse, we need to swap before/after in
  82  * add_dep().
  83  */
  84 enum direction { F, R };
  85
  86 struct schedule_state {
  87         struct schedule_node *last_r[6];
  88         struct schedule_node *last_ra[32];
  89         struct schedule_node *last_rb[32];
  90         struct schedule_node *last_sf;
  91         struct schedule_node *last_vpm_read;
  92         struct schedule_node *last_tmu_write;
  93         struct schedule_node *last_tlb;
  94         struct schedule_node *last_vpm;
  95         struct schedule_node *last_uniforms_reset;
  96         enum direction dir;
  97         /* Estimated cycle when the current instruction would start. */
  98         uint32_t time;
  99 };
 100
 101 static void
 102 add_dep(struct schedule_state *state,
 103         struct schedule_node *before,
 104         struct schedule_node *after,
 105         bool write)
 106 {
 107         bool write_after_read = !write && state->dir == R;
 108
 109         if (!before || !after)
 110                 return;
 111
 112         assert(before != after);
 113
 114         if (state->dir == R) {
 115                 struct schedule_node *t = before;
 116                 before = after;
 117                 after = t;
 118         }
 119
 120         for (int i = 0; i < before->child_count; i++) {
 121                 if (before->children[i].node == after &&
 122                     (before->children[i].write_after_read == write_after_read)) {
 123                         return;
 124                 }
 125         }
 126
 127         if (before->child_array_size <= before->child_count) {
 128                 before->child_array_size = MAX2(before->child_array_size * 2, 16);
 129                 before->children = reralloc(before, before->children,
 130                                             struct schedule_node_child,
 131                                             before->child_array_size);
 132         }
 133
 134         before->children[before->child_count].node = after;
 135         before->children[before->child_count].write_after_read =
 136                 write_after_read;
 137         before->child_count++;
 138         after->parent_count++;
 139 }
 140
 141 static void
 142 add_read_dep(struct schedule_state *state,
 143               struct schedule_node *before,
 144               struct schedule_node *after)
 145 {
 146         add_dep(state, before, after, false);
 147 }
 148
 149 static void
 150 add_write_dep(struct schedule_state *state,
 151               struct schedule_node **before,
 152               struct schedule_node *after)
 153 {
 154         add_dep(state, *before, after, true);
 155         *before = after;
 156 }
 157
 158 static bool
 159 qpu_writes_r4(uint64_t inst)
 160 {
 161         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 162
 163         switch(sig) {
 164         case QPU_SIG_COLOR_LOAD:
 165         case QPU_SIG_LOAD_TMU0:
 166         case QPU_SIG_LOAD_TMU1:
 167         case QPU_SIG_ALPHA_MASK_LOAD:
 168                 return true;
 169         default:
 170                 return false;
 171         }
 172 }
 173
 174 static void
 175 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
 176                    uint32_t raddr, bool is_a)
 177 {
 178         switch (raddr) {
 179         case QPU_R_VARY:
 180                 add_write_dep(state, &state->last_r[5], n);
 181                 break;
 182
 183         case QPU_R_VPM:
 184                 add_write_dep(state, &state->last_vpm_read, n);
 185                 break;
 186
 187         case QPU_R_UNIF:
 188                 add_read_dep(state, state->last_uniforms_reset, n);
 189                 break;
 190
 191         case QPU_R_NOP:
 192         case QPU_R_ELEM_QPU:
 193         case QPU_R_XY_PIXEL_COORD:
 194         case QPU_R_MS_REV_FLAGS:
 195                 break;
 196
 197         default:
 198                 if (raddr < 32) {
 199                         if (is_a)
 200                                 add_read_dep(state, state->last_ra[raddr], n);
 201                         else
 202                                 add_read_dep(state, state->last_rb[raddr], n);
 203                 } else {
 204                         fprintf(stderr, "unknown raddr %d\n", raddr);
 205                         abort();
 206                 }
 207                 break;
 208         }
 209 }
 210
 211 static bool
 212 is_tmu_write(uint32_t waddr)
 213 {
 214         switch (waddr) {
 215         case QPU_W_TMU0_S:
 216         case QPU_W_TMU0_T:
 217         case QPU_W_TMU0_R:
 218         case QPU_W_TMU0_B:
 219         case QPU_W_TMU1_S:
 220         case QPU_W_TMU1_T:
 221         case QPU_W_TMU1_R:
 222         case QPU_W_TMU1_B:
 223                 return true;
 224         default:
 225                 return false;
 226         }
 227 }
 228
 229 static bool
 230 reads_uniform(uint64_t inst)
 231 {
 232         if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
 233                 return false;
 234
 235         return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
 236                 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
 237                  QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
 238                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
 239                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
 240 }
 241
 242 static void
 243 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
 244                  uint32_t mux)
 245 {
 246         if (mux != QPU_MUX_A && mux != QPU_MUX_B)
 247                 add_read_dep(state, state->last_r[mux], n);
 248 }
 249
 250
 251 static void
 252 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
 253                    uint32_t waddr, bool is_add)
 254 {
 255         uint64_t inst = n->inst->inst;
 256         bool is_a = is_add ^ ((inst & QPU_WS) != 0);
 257
 258         if (waddr < 32) {
 259                 if (is_a) {
 260                         add_write_dep(state, &state->last_ra[waddr], n);
 261                 } else {
 262                         add_write_dep(state, &state->last_rb[waddr], n);
 263                 }
 264         } else if (is_tmu_write(waddr)) {
 265                 add_write_dep(state, &state->last_tmu_write, n);
 266                 add_read_dep(state, state->last_uniforms_reset, n);
 267         } else if (qpu_waddr_is_tlb(waddr) ||
 268                    waddr == QPU_W_MS_FLAGS) {
 269                 add_write_dep(state, &state->last_tlb, n);
 270         } else {
 271                 switch (waddr) {
 272                 case QPU_W_ACC0:
 273                 case QPU_W_ACC1:
 274                 case QPU_W_ACC2:
 275                 case QPU_W_ACC3:
 276                 case QPU_W_ACC5:
 277                         add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
 278                                       n);
 279                         break;
 280
 281                 case QPU_W_VPM:
 282                         add_write_dep(state, &state->last_vpm, n);
 283                         break;
 284
 285                 case QPU_W_VPMVCD_SETUP:
 286                         if (is_a)
 287                                 add_write_dep(state, &state->last_vpm_read, n);
 288                         else
 289                                 add_write_dep(state, &state->last_vpm, n);
 290                         break;
 291
 292                 case QPU_W_SFU_RECIP:
 293                 case QPU_W_SFU_RECIPSQRT:
 294                 case QPU_W_SFU_EXP:
 295                 case QPU_W_SFU_LOG:
 296                         add_write_dep(state, &state->last_r[4], n);
 297                         break;
 298
 299                 case QPU_W_TLB_STENCIL_SETUP:
 300                         /* This isn't a TLB operation that does things like
 301                          * implicitly lock the scoreboard, but it does have to
 302                          * appear before TLB_Z, and each of the TLB_STENCILs
 303                          * have to schedule in the same order relative to each
 304                          * other.
 305                          */
 306                         add_write_dep(state, &state->last_tlb, n);
 307                         break;
 308
 309                 case QPU_W_MS_FLAGS:
 310                         add_write_dep(state, &state->last_tlb, n);
 311                         break;
 312
 313                 case QPU_W_UNIFORMS_ADDRESS:
 314                         add_write_dep(state, &state->last_uniforms_reset, n);
 315                         break;
 316
 317                 case QPU_W_NOP:
 318                         break;
 319
 320                 default:
 321                         fprintf(stderr, "Unknown waddr %d\n", waddr);
 322                         abort();
 323                 }
 324         }
 325 }
 326
 327 static void
 328 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
 329                   uint32_t cond)
 330 {
 331         switch (cond) {
 332         case QPU_COND_NEVER:
 333         case QPU_COND_ALWAYS:
 334                 break;
 335         default:
 336                 add_read_dep(state, state->last_sf, n);
 337                 break;
 338         }
 339 }
 340
 341 /**
 342  * Common code for dependencies that need to be tracked both forward and
 343  * backward.
 344  *
 345  * This is for things like "all reads of r4 have to happen between the r4
 346  * writes that surround them".
 347  */
 348 static void
 349 calculate_deps(struct schedule_state *state, struct schedule_node *n)
 350 {
 351         uint64_t inst = n->inst->inst;
 352         uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
 353         uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
 354         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 355         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 356         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 357         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 358         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 359         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 360         uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 361         uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 362         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 363
 364         if (sig != QPU_SIG_LOAD_IMM) {
 365                 process_raddr_deps(state, n, raddr_a, true);
 366                 if (sig != QPU_SIG_SMALL_IMM &&
 367                     sig != QPU_SIG_BRANCH)
 368                         process_raddr_deps(state, n, raddr_b, false);
 369         }
 370
 371         if (add_op != QPU_A_NOP) {
 372                 process_mux_deps(state, n, add_a);
 373                 process_mux_deps(state, n, add_b);
 374         }
 375         if (mul_op != QPU_M_NOP) {
 376                 process_mux_deps(state, n, mul_a);
 377                 process_mux_deps(state, n, mul_b);
 378         }
 379
 380         process_waddr_deps(state, n, waddr_add, true);
 381         process_waddr_deps(state, n, waddr_mul, false);
 382         if (qpu_writes_r4(inst))
 383                 add_write_dep(state, &state->last_r[4], n);
 384
 385         switch (sig) {
 386         case QPU_SIG_SW_BREAKPOINT:
 387         case QPU_SIG_NONE:
 388         case QPU_SIG_THREAD_SWITCH:
 389         case QPU_SIG_LAST_THREAD_SWITCH:
 390         case QPU_SIG_SMALL_IMM:
 391         case QPU_SIG_LOAD_IMM:
 392                 break;
 393
 394         case QPU_SIG_LOAD_TMU0:
 395         case QPU_SIG_LOAD_TMU1:
 396                 /* TMU loads are coming from a FIFO, so ordering is important.
 397                  */
 398                 add_write_dep(state, &state->last_tmu_write, n);
 399                 break;
 400
 401         case QPU_SIG_COLOR_LOAD:
 402                 add_read_dep(state, state->last_tlb, n);
 403                 break;
 404
 405         case QPU_SIG_BRANCH:
 406                 add_read_dep(state, state->last_sf, n);
 407                 break;
 408
 409         case QPU_SIG_PROG_END:
 410         case QPU_SIG_WAIT_FOR_SCOREBOARD:
 411         case QPU_SIG_SCOREBOARD_UNLOCK:
 412         case QPU_SIG_COVERAGE_LOAD:
 413         case QPU_SIG_COLOR_LOAD_END:
 414         case QPU_SIG_ALPHA_MASK_LOAD:
 415                 fprintf(stderr, "Unhandled signal bits %d\n", sig);
 416                 abort();
 417         }
 418
 419         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 420         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
 421         if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
 422                 add_write_dep(state, &state->last_sf, n);
 423 }
 424
 425 static void
 426 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
 427 {
 428         struct schedule_state state;
 429
 430         memset(&state, 0, sizeof(state));
 431         state.dir = F;
 432
 433         list_for_each_entry(struct schedule_node, node, schedule_list, link)
 434                 calculate_deps(&state, node);
 435 }
 436
 437 static void
 438 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
 439 {
 440         struct list_head *node;
 441         struct schedule_state state;
 442
 443         memset(&state, 0, sizeof(state));
 444         state.dir = R;
 445
 446         for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
 447                 calculate_deps(&state, (struct schedule_node *)node);
 448         }
 449 }
 450
 451 struct choose_scoreboard {
 452         int tick;
 453         int last_sfu_write_tick;
 454         int last_uniforms_reset_tick;
 455         uint32_t last_waddr_a, last_waddr_b;
 456 };
 457
 458 static bool
 459 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
 460 {
 461         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 462         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 463         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 464         uint32_t src_muxes[] = {
 465                 QPU_GET_FIELD(inst, QPU_ADD_A),
 466                 QPU_GET_FIELD(inst, QPU_ADD_B),
 467                 QPU_GET_FIELD(inst, QPU_MUL_A),
 468                 QPU_GET_FIELD(inst, QPU_MUL_B),
 469         };
 470         for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
 471                 if ((src_muxes[i] == QPU_MUX_A &&
 472                      raddr_a < 32 &&
 473                      scoreboard->last_waddr_a == raddr_a) ||
 474                     (src_muxes[i] == QPU_MUX_B &&
 475                      sig != QPU_SIG_SMALL_IMM &&
 476                      raddr_b < 32 &&
 477                      scoreboard->last_waddr_b == raddr_b)) {
 478                         return true;
 479                 }
 480
 481                 if (src_muxes[i] == QPU_MUX_R4) {
 482                         if (scoreboard->tick -
 483                             scoreboard->last_sfu_write_tick <= 2) {
 484                                 return true;
 485                         }
 486                 }
 487         }
 488
 489         if (reads_uniform(inst) &&
 490             scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
 491                 return true;
 492         }
 493
 494         return false;
 495 }
 496
 497 static bool
 498 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
 499 {
 500         return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
 501 }
 502
 503 static int
 504 get_instruction_priority(uint64_t inst)
 505 {
 506         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 507         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 508         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 509         uint32_t baseline_score;
 510         uint32_t next_score = 0;
 511
 512         /* Schedule TLB operations as late as possible, to get more
 513          * parallelism between shaders.
 514          */
 515         if (qpu_inst_is_tlb(inst))
 516                 return next_score;
 517         next_score++;
 518
 519         /* Schedule texture read results collection late to hide latency. */
 520         if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
 521                 return next_score;
 522         next_score++;
 523
 524         /* Default score for things that aren't otherwise special. */
 525         baseline_score = next_score;
 526         next_score++;
 527
 528         /* Schedule texture read setup early to hide their latency better. */
 529         if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
 530                 return next_score;
 531         next_score++;
 532
 533         return baseline_score;
 534 }
 535
 536 static struct schedule_node *
 537 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
 538                                struct list_head *schedule_list,
 539                                struct schedule_node *prev_inst)
 540 {
 541         struct schedule_node *chosen = NULL;
 542         int chosen_prio = 0;
 543
 544         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 545                 uint64_t inst = n->inst->inst;
 546
 547                 /* Don't choose the branch instruction until it's the last one
 548                  * left.  XXX: We could potentially choose it before it's the
 549                  * last one, if the remaining instructions fit in the delay
 550                  * slots.
 551                  */
 552                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
 553                     !list_is_singular(schedule_list)) {
 554                         continue;
 555                 }
 556
 557                 /* "An instruction must not read from a location in physical
 558                  *  regfile A or B that was written to by the previous
 559                  *  instruction."
 560                  */
 561                 if (reads_too_soon_after_write(scoreboard, inst))
 562                         continue;
 563
 564                 /* "A scoreboard wait must not occur in the first two
 565                  *  instructions of a fragment shader. This is either the
 566                  *  explicit Wait for Scoreboard signal or an implicit wait
 567                  *  with the first tile-buffer read or write instruction."
 568                  */
 569                 if (pixel_scoreboard_too_soon(scoreboard, inst))
 570                         continue;
 571
 572                 /* If we're trying to pair with another instruction, check
 573                  * that they're compatible.
 574                  */
 575                 if (prev_inst) {
 576                         if (prev_inst->uniform != -1 && n->uniform != -1)
 577                                 continue;
 578
 579                         inst = qpu_merge_inst(prev_inst->inst->inst, inst);
 580                         if (!inst)
 581                                 continue;
 582                 }
 583
 584                 int prio = get_instruction_priority(inst);
 585
 586                 /* Found a valid instruction.  If nothing better comes along,
 587                  * this one works.
 588                  */
 589                 if (!chosen) {
 590                         chosen = n;
 591                         chosen_prio = prio;
 592                         continue;
 593                 }
 594
 595                 if (prio > chosen_prio) {
 596                         chosen = n;
 597                         chosen_prio = prio;
 598                 } else if (prio < chosen_prio) {
 599                         continue;
 600                 }
 601
 602                 if (n->delay > chosen->delay) {
 603                         chosen = n;
 604                         chosen_prio = prio;
 605                 } else if (n->delay < chosen->delay) {
 606                         continue;
 607                 }
 608         }
 609
 610         return chosen;
 611 }
 612
 613 static void
 614 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
 615                              uint64_t inst)
 616 {
 617         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 618         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 619
 620         if (!(inst & QPU_WS)) {
 621                 scoreboard->last_waddr_a = waddr_add;
 622                 scoreboard->last_waddr_b = waddr_mul;
 623         } else {
 624                 scoreboard->last_waddr_b = waddr_add;
 625                 scoreboard->last_waddr_a = waddr_mul;
 626         }
 627
 628         if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
 629             (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
 630                 scoreboard->last_sfu_write_tick = scoreboard->tick;
 631         }
 632
 633         if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
 634             waddr_mul == QPU_W_UNIFORMS_ADDRESS) {
 635                 scoreboard->last_uniforms_reset_tick = scoreboard->tick;
 636         }
 637 }
 638
 639 static void
 640 dump_state(struct list_head *schedule_list)
 641 {
 642         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 643                 fprintf(stderr, "         t=%4d: ", n->unblocked_time);
 644                 vc4_qpu_disasm(&n->inst->inst, 1);
 645                 fprintf(stderr, "\n");
 646
 647                 for (int i = 0; i < n->child_count; i++) {
 648                         struct schedule_node *child = n->children[i].node;
 649                         if (!child)
 650                                 continue;
 651
 652                         fprintf(stderr, "                 - ");
 653                         vc4_qpu_disasm(&child->inst->inst, 1);
 654                         fprintf(stderr, " (%d parents, %c)\n",
 655                                 child->parent_count,
 656                                 n->children[i].write_after_read ? 'w' : 'r');
 657                 }
 658         }
 659 }
 660
 661 static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
 662 {
 663         if (waddr < 32)
 664                 return 2;
 665
 666         /* Apply some huge latency between texture fetch requests and getting
 667          * their results back.
 668          */
 669         if (waddr == QPU_W_TMU0_S) {
 670                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
 671                         return 100;
 672         }
 673         if (waddr == QPU_W_TMU1_S) {
 674                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
 675                         return 100;
 676         }
 677
 678         switch(waddr) {
 679         case QPU_W_SFU_RECIP:
 680         case QPU_W_SFU_RECIPSQRT:
 681         case QPU_W_SFU_EXP:
 682         case QPU_W_SFU_LOG:
 683                 return 3;
 684         default:
 685                 return 1;
 686         }
 687 }
 688
 689 static uint32_t
 690 instruction_latency(struct schedule_node *before, struct schedule_node *after)
 691 {
 692         uint64_t before_inst = before->inst->inst;
 693         uint64_t after_inst = after->inst->inst;
 694
 695         return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
 696                                   after_inst),
 697                     waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
 698                                   after_inst));
 699 }
 700
 701 /** Recursive computation of the delay member of a node. */
 702 static void
 703 compute_delay(struct schedule_node *n)
 704 {
 705         if (!n->child_count) {
 706                 n->delay = 1;
 707         } else {
 708                 for (int i = 0; i < n->child_count; i++) {
 709                         if (!n->children[i].node->delay)
 710                                 compute_delay(n->children[i].node);
 711                         n->delay = MAX2(n->delay,
 712                                         n->children[i].node->delay +
 713                                         instruction_latency(n, n->children[i].node));
 714                 }
 715         }
 716 }
 717
 718 static void
 719 mark_instruction_scheduled(struct list_head *schedule_list,
 720                            uint32_t time,
 721                            struct schedule_node *node,
 722                            bool war_only)
 723 {
 724         if (!node)
 725                 return;
 726
 727         for (int i = node->child_count - 1; i >= 0; i--) {
 728                 struct schedule_node *child =
 729                         node->children[i].node;
 730
 731                 if (!child)
 732                         continue;
 733
 734                 if (war_only && !node->children[i].write_after_read)
 735                         continue;
 736
 737                 /* If the requirement is only that the node not appear before
 738                  * the last read of its destination, then it can be scheduled
 739                  * immediately after (or paired with!) the thing reading the
 740                  * destination.
 741                  */
 742                 uint32_t latency = 0;
 743                 if (!war_only) {
 744                         latency = instruction_latency(node,
 745                                                       node->children[i].node);
 746                 }
 747
 748                 child->unblocked_time = MAX2(child->unblocked_time,
 749                                              time + latency);
 750                 child->parent_count--;
 751                 if (child->parent_count == 0)
 752                         list_add(&child->link, schedule_list);
 753
 754                 node->children[i].node = NULL;
 755         }
 756 }
 757
 758 static uint32_t
 759 schedule_instructions(struct vc4_compile *c,
 760                       struct choose_scoreboard *scoreboard,
 761                       struct qblock *block,
 762                       struct list_head *schedule_list,
 763                       enum quniform_contents *orig_uniform_contents,
 764                       uint32_t *orig_uniform_data,
 765                       uint32_t *next_uniform)
 766 {
 767         uint32_t time = 0;
 768
 769         if (debug) {
 770                 fprintf(stderr, "initial deps:\n");
 771                 dump_state(schedule_list);
 772                 fprintf(stderr, "\n");
 773         }
 774
 775         /* Remove non-DAG heads from the list. */
 776         list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
 777                 if (n->parent_count != 0)
 778                         list_del(&n->link);
 779         }
 780
 781         while (!list_empty(schedule_list)) {
 782                 struct schedule_node *chosen =
 783                         choose_instruction_to_schedule(scoreboard,
 784                                                        schedule_list,
 785                                                        NULL);
 786                 struct schedule_node *merge = NULL;
 787
 788                 /* If there are no valid instructions to schedule, drop a NOP
 789                  * in.
 790                  */
 791                 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
 792
 793                 if (debug) {
 794                         fprintf(stderr, "t=%4d: current list:\n",
 795                                 time);
 796                         dump_state(schedule_list);
 797                         fprintf(stderr, "t=%4d: chose: ", time);
 798                         vc4_qpu_disasm(&inst, 1);
 799                         fprintf(stderr, "\n");
 800                 }
 801
 802                 /* Schedule this instruction onto the QPU list. Also try to
 803                  * find an instruction to pair with it.
 804                  */
 805                 if (chosen) {
 806                         time = MAX2(chosen->unblocked_time, time);
 807                         list_del(&chosen->link);
 808                         mark_instruction_scheduled(schedule_list, time,
 809                                                    chosen, true);
 810                         if (chosen->uniform != -1) {
 811                                 c->uniform_data[*next_uniform] =
 812                                         orig_uniform_data[chosen->uniform];
 813                                 c->uniform_contents[*next_uniform] =
 814                                         orig_uniform_contents[chosen->uniform];
 815                                 (*next_uniform)++;
 816                         }
 817
 818                         merge = choose_instruction_to_schedule(scoreboard,
 819                                                                schedule_list,
 820                                                                chosen);
 821                         if (merge) {
 822                                 time = MAX2(merge->unblocked_time, time);
 823                                 list_del(&merge->link);
 824                                 inst = qpu_merge_inst(inst, merge->inst->inst);
 825                                 assert(inst != 0);
 826                                 if (merge->uniform != -1) {
 827                                         c->uniform_data[*next_uniform] =
 828                                                 orig_uniform_data[merge->uniform];
 829                                         c->uniform_contents[*next_uniform] =
 830                                                 orig_uniform_contents[merge->uniform];
 831                                         (*next_uniform)++;
 832                                 }
 833
 834                                 if (debug) {
 835                                         fprintf(stderr, "t=%4d: merging: ",
 836                                                 time);
 837                                         vc4_qpu_disasm(&merge->inst->inst, 1);
 838                                         fprintf(stderr, "\n");
 839                                         fprintf(stderr, "            resulting in: ");
 840                                         vc4_qpu_disasm(&inst, 1);
 841                                         fprintf(stderr, "\n");
 842                                 }
 843                         }
 844                 }
 845
 846                 if (debug) {
 847                         fprintf(stderr, "\n");
 848                 }
 849
 850                 qpu_serialize_one_inst(c, inst);
 851
 852                 update_scoreboard_for_chosen(scoreboard, inst);
 853
 854                 /* Now that we've scheduled a new instruction, some of its
 855                  * children can be promoted to the list of instructions ready to
 856                  * be scheduled.  Update the children's unblocked time for this
 857                  * DAG edge as we do so.
 858                  */
 859                 mark_instruction_scheduled(schedule_list, time, chosen, false);
 860                 mark_instruction_scheduled(schedule_list, time, merge, false);
 861
 862                 scoreboard->tick++;
 863                 time++;
 864
 865                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) {
 866                         block->branch_qpu_ip = c->qpu_inst_count - 1;
 867                         /* Fill the delay slots.
 868                          *
 869                          * We should fill these with actual instructions,
 870                          * instead, but that will probably need to be done
 871                          * after this, once we know what the leading
 872                          * instructions of the successors are (so we can
 873                          * handle A/B register file write latency)
 874                         */
 875                         inst = qpu_NOP();
 876                         update_scoreboard_for_chosen(scoreboard, inst);
 877                         qpu_serialize_one_inst(c, inst);
 878                         qpu_serialize_one_inst(c, inst);
 879                         qpu_serialize_one_inst(c, inst);
 880                 }
 881         }
 882
 883         return time;
 884 }
 885
 886 static uint32_t
 887 qpu_schedule_instructions_block(struct vc4_compile *c,
 888                                 struct choose_scoreboard *scoreboard,
 889                                 struct qblock *block,
 890                                 enum quniform_contents *orig_uniform_contents,
 891                                 uint32_t *orig_uniform_data,
 892                                 uint32_t *next_uniform)
 893 {
 894         void *mem_ctx = ralloc_context(NULL);
 895         struct list_head schedule_list;
 896
 897         list_inithead(&schedule_list);
 898
 899         /* Wrap each instruction in a scheduler structure. */
 900         uint32_t next_sched_uniform = *next_uniform;
 901         while (!list_empty(&block->qpu_inst_list)) {
 902                 struct queued_qpu_inst *inst =
 903                         (struct queued_qpu_inst *)block->qpu_inst_list.next;
 904                 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
 905
 906                 n->inst = inst;
 907
 908                 if (reads_uniform(inst->inst)) {
 909                         n->uniform = next_sched_uniform++;
 910                 } else {
 911                         n->uniform = -1;
 912                 }
 913                 list_del(&inst->link);
 914                 list_addtail(&n->link, &schedule_list);
 915         }
 916
 917         calculate_forward_deps(c, &schedule_list);
 918         calculate_reverse_deps(c, &schedule_list);
 919
 920         list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
 921                 compute_delay(n);
 922         }
 923
 924         uint32_t cycles = schedule_instructions(c, scoreboard, block,
 925                                                 &schedule_list,
 926                                                 orig_uniform_contents,
 927                                                 orig_uniform_data,
 928                                                 next_uniform);
 929
 930         ralloc_free(mem_ctx);
 931
 932         return cycles;
 933 }
 934
 935 static void
 936 qpu_set_branch_targets(struct vc4_compile *c)
 937 {
 938         qir_for_each_block(block, c) {
 939                 /* The end block of the program has no branch. */
 940                 if (!block->successors[0])
 941                         continue;
 942
 943                 /* If there was no branch instruction, then the successor
 944                  * block must follow immediately after this one.
 945                  */
 946                 if (block->branch_qpu_ip == ~0) {
 947                         assert(block->end_qpu_ip + 1 ==
 948                                block->successors[0]->start_qpu_ip);
 949                         continue;
 950                 }
 951
 952                 /* Set the branch target for the block that doesn't follow
 953                  * immediately after ours.
 954                  */
 955                 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
 956                 assert(QPU_GET_FIELD(*branch_inst, QPU_SIG) == QPU_SIG_BRANCH);
 957                 assert(QPU_GET_FIELD(*branch_inst, QPU_BRANCH_TARGET) == 0);
 958
 959                 uint32_t branch_target =
 960                         (block->successors[0]->start_qpu_ip -
 961                          (block->branch_qpu_ip + 4)) * sizeof(uint64_t);
 962                 *branch_inst = (*branch_inst |
 963                                 QPU_SET_FIELD(branch_target, QPU_BRANCH_TARGET));
 964
 965                 /* Make sure that the if-we-don't-jump successor was scheduled
 966                  * just after the delay slots.
 967                  */
 968                 if (block->successors[1]) {
 969                         assert(block->successors[1]->start_qpu_ip ==
 970                                block->branch_qpu_ip + 4);
 971                 }
 972         }
 973 }
 974
 975 uint32_t
 976 qpu_schedule_instructions(struct vc4_compile *c)
 977 {
 978         /* We reorder the uniforms as we schedule instructions, so save the
 979          * old data off and replace it.
 980          */
 981         uint32_t *uniform_data = c->uniform_data;
 982         enum quniform_contents *uniform_contents = c->uniform_contents;
 983         c->uniform_contents = ralloc_array(c, enum quniform_contents,
 984                                            c->num_uniforms);
 985         c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
 986         c->uniform_array_size = c->num_uniforms;
 987         uint32_t next_uniform = 0;
 988
 989         struct choose_scoreboard scoreboard;
 990         memset(&scoreboard, 0, sizeof(scoreboard));
 991         scoreboard.last_waddr_a = ~0;
 992         scoreboard.last_waddr_b = ~0;
 993         scoreboard.last_sfu_write_tick = -10;
 994         scoreboard.last_uniforms_reset_tick = -10;
 995
 996         if (debug) {
 997                 fprintf(stderr, "Pre-schedule instructions\n");
 998                 qir_for_each_block(block, c) {
 999                         fprintf(stderr, "BLOCK %d\n", block->index);
1000                         list_for_each_entry(struct queued_qpu_inst, q,
1001                                             &block->qpu_inst_list, link) {
1002                                 vc4_qpu_disasm(&q->inst, 1);
1003                                 fprintf(stderr, "\n");
1004                         }
1005                 }
1006                 fprintf(stderr, "\n");
1007         }
1008
1009         uint32_t cycles = 0;
1010         qir_for_each_block(block, c) {
1011                 block->start_qpu_ip = c->qpu_inst_count;
1012                 block->branch_qpu_ip = ~0;
1013
1014                 cycles += qpu_schedule_instructions_block(c,
1015                                                           &scoreboard,
1016                                                           block,
1017                                                           uniform_contents,
1018                                                           uniform_data,
1019                                                           &next_uniform);
1020
1021                 block->end_qpu_ip = c->qpu_inst_count - 1;
1022         }
1023
1024         qpu_set_branch_targets(c);
1025
1026         assert(next_uniform == c->num_uniforms);
1027
1028         if (debug) {
1029                 fprintf(stderr, "Post-schedule instructions\n");
1030                 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
1031                 fprintf(stderr, "\n");
1032         }
1033
1034         return cycles;
1035 }