src/gallium/drivers/vc4/vc4_screen.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "os/os_misc.h"
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_screen.h"
  28 #include "pipe/p_state.h"
  29
  30 #include "util/u_debug.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format.h"
  33 #include "util/u_hash_table.h"
  34 #include "util/ralloc.h"
  35
  36 #include <xf86drm.h>
  37 #include "vc4_drm.h"
  38 #include "vc4_screen.h"
  39 #include "vc4_context.h"
  40 #include "vc4_resource.h"
  41
  42 static const struct debug_named_value debug_options[] = {
  43         { "cl",       VC4_DEBUG_CL,
  44           "Dump command list during creation" },
  45         { "qpu",      VC4_DEBUG_QPU,
  46           "Dump generated QPU instructions" },
  47         { "qir",      VC4_DEBUG_QIR,
  48           "Dump QPU IR during program compile" },
  49         { "nir",      VC4_DEBUG_NIR,
  50           "Dump NIR during program compile" },
  51         { "tgsi",     VC4_DEBUG_TGSI,
  52           "Dump TGSI during program compile" },
  53         { "shaderdb", VC4_DEBUG_SHADERDB,
  54           "Dump program compile information for shader-db analysis" },
  55         { "perf",     VC4_DEBUG_PERF,
  56           "Print during performance-related events" },
  57         { "norast",   VC4_DEBUG_NORAST,
  58           "Skip actual hardware execution of commands" },
  59         { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
  60           "Flush after each draw call" },
  61         { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
  62           "Wait for finish after each flush" },
  63 #if USE_VC4_SIMULATOR
  64         { "dump", VC4_DEBUG_DUMP,
  65           "Write a GPU command stream trace file" },
  66 #endif
  67         { NULL }
  68 };
  69
  70 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
  71 uint32_t vc4_debug;
  72
  73 static const char *
  74 vc4_screen_get_name(struct pipe_screen *pscreen)
  75 {
  76         struct vc4_screen *screen = vc4_screen(pscreen);
  77
  78         if (!screen->name) {
  79                 screen->name = ralloc_asprintf(screen,
  80                                                "VC4 V3D %d.%d",
  81                                                screen->v3d_ver / 10,
  82                                                screen->v3d_ver % 10);
  83         }
  84
  85         return screen->name;
  86 }
  87
  88 static const char *
  89 vc4_screen_get_vendor(struct pipe_screen *pscreen)
  90 {
  91         return "Broadcom";
  92 }
  93
  94 static void
  95 vc4_screen_destroy(struct pipe_screen *pscreen)
  96 {
  97         struct vc4_screen *screen = vc4_screen(pscreen);
  98
  99         vc4_bufmgr_destroy(pscreen);
 100         close(screen->fd);
 101         ralloc_free(pscreen);
 102 }
 103
 104 static int
 105 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107         switch (param) {
 108                 /* Supported features (boolean caps). */
 109         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 110         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 111         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 112         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 113         case PIPE_CAP_NPOT_TEXTURES:
 114         case PIPE_CAP_SHAREABLE_SHADERS:
 115         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 116         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 117         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 118         case PIPE_CAP_TWO_SIDED_STENCIL:
 119         case PIPE_CAP_USER_INDEX_BUFFERS:
 120         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 121         case PIPE_CAP_TEXTURE_SWIZZLE:
 122                 return 1;
 123
 124                 /* lying for GL 2.0 */
 125         case PIPE_CAP_OCCLUSION_QUERY:
 126         case PIPE_CAP_POINT_SPRITE:
 127                 return 1;
 128
 129         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 130                 return 256;
 131
 132         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 133                 return 120;
 134
 135         case PIPE_CAP_MAX_VIEWPORTS:
 136                 return 1;
 137
 138         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 139         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 140                 return 1;
 141
 142         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 143                 return 1;
 144
 145                 /* Unsupported features. */
 146         case PIPE_CAP_ANISOTROPIC_FILTER:
 147         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 148         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 149         case PIPE_CAP_CUBE_MAP_ARRAY:
 150         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 151         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 152         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 153         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 154         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 155         case PIPE_CAP_TGSI_INSTANCEID:
 156         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 157         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 158         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 159         case PIPE_CAP_COMPUTE:
 160         case PIPE_CAP_START_INSTANCE:
 161         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 162         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 163         case PIPE_CAP_TGSI_TEXCOORD:
 164         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 165         case PIPE_CAP_CONDITIONAL_RENDER:
 166         case PIPE_CAP_PRIMITIVE_RESTART:
 167         case PIPE_CAP_TEXTURE_BARRIER:
 168         case PIPE_CAP_SM3:
 169         case PIPE_CAP_INDEP_BLEND_ENABLE:
 170         case PIPE_CAP_INDEP_BLEND_FUNC:
 171         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 172         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 173         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 174         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 175         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 176         case PIPE_CAP_USER_VERTEX_BUFFERS:
 177         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 178         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 179         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 180         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 181         case PIPE_CAP_TEXTURE_GATHER_SM5:
 182         case PIPE_CAP_FAKE_SW_MSAA:
 183         case PIPE_CAP_TEXTURE_QUERY_LOD:
 184         case PIPE_CAP_SAMPLE_SHADING:
 185         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 186         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 187         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 188         case PIPE_CAP_MAX_TEXEL_OFFSET:
 189         case PIPE_CAP_MAX_VERTEX_STREAMS:
 190         case PIPE_CAP_DRAW_INDIRECT:
 191         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 192         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 193         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 194         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 195         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 196         case PIPE_CAP_CLIP_HALFZ:
 197         case PIPE_CAP_VERTEXID_NOBASE:
 198         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 199         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 200         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 201         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 202         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 203         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 204         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 205         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 206         case PIPE_CAP_TGSI_TXQS:
 207         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 208         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 209         case PIPE_CAP_CLEAR_TEXTURE:
 210         case PIPE_CAP_DRAW_PARAMETERS:
 211         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 212         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 213         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 214         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 215         case PIPE_CAP_INVALIDATE_BUFFER:
 216         case PIPE_CAP_GENERATE_MIPMAP:
 217         case PIPE_CAP_STRING_MARKER:
 218         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 219         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 220         case PIPE_CAP_QUERY_MEMORY_INFO:
 221         case PIPE_CAP_PCI_GROUP:
 222         case PIPE_CAP_PCI_BUS:
 223         case PIPE_CAP_PCI_DEVICE:
 224         case PIPE_CAP_PCI_FUNCTION:
 225         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 226         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 227         case PIPE_CAP_CULL_DISTANCE:
 228         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 229         case PIPE_CAP_TGSI_VOTE:
 230         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 231         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 232         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 233                 return 0;
 234
 235                 /* Stream output. */
 236         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 237         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 238         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 239         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 240                 return 0;
 241
 242                 /* Geometry shader output, unsupported. */
 243         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 244         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 245                 return 0;
 246
 247                 /* Texturing. */
 248         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 249         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 250                 return VC4_MAX_MIP_LEVELS;
 251         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 252                 /* Note: Not supported in hardware, just faking it. */
 253                 return 5;
 254         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 255                 return 0;
 256
 257                 /* Render targets. */
 258         case PIPE_CAP_MAX_RENDER_TARGETS:
 259                 return 1;
 260
 261                 /* Queries. */
 262         case PIPE_CAP_QUERY_TIME_ELAPSED:
 263         case PIPE_CAP_QUERY_TIMESTAMP:
 264                 return 0;
 265
 266         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 267         case PIPE_CAP_MIN_TEXEL_OFFSET:
 268                 return 0;
 269
 270         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 271                 return 2048;
 272
 273         case PIPE_CAP_ENDIANNESS:
 274                 return PIPE_ENDIAN_LITTLE;
 275
 276         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 277                 return 64;
 278
 279         case PIPE_CAP_VENDOR_ID:
 280                 return 0x14E4;
 281         case PIPE_CAP_DEVICE_ID:
 282                 return 0xFFFFFFFF;
 283         case PIPE_CAP_ACCELERATED:
 284                 return 1;
 285         case PIPE_CAP_VIDEO_MEMORY: {
 286                 uint64_t system_memory;
 287
 288                 if (!os_get_total_physical_memory(&system_memory))
 289                         return 0;
 290
 291                 return (int)(system_memory >> 20);
 292         }
 293         case PIPE_CAP_UMA:
 294                 return 1;
 295
 296         default:
 297                 fprintf(stderr, "unknown param %d\n", param);
 298                 return 0;
 299         }
 300 }
 301
 302 static float
 303 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 304 {
 305         switch (param) {
 306         case PIPE_CAPF_MAX_LINE_WIDTH:
 307         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 308                 return 32;
 309
 310         case PIPE_CAPF_MAX_POINT_WIDTH:
 311         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 312                 return 512.0f;
 313
 314         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 315                 return 0.0f;
 316         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 317                 return 0.0f;
 318         case PIPE_CAPF_GUARD_BAND_LEFT:
 319         case PIPE_CAPF_GUARD_BAND_TOP:
 320         case PIPE_CAPF_GUARD_BAND_RIGHT:
 321         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 322                 return 0.0f;
 323         default:
 324                 fprintf(stderr, "unknown paramf %d\n", param);
 325                 return 0;
 326         }
 327 }
 328
 329 static int
 330 vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 331                            enum pipe_shader_cap param)
 332 {
 333         if (shader != PIPE_SHADER_VERTEX &&
 334             shader != PIPE_SHADER_FRAGMENT) {
 335                 return 0;
 336         }
 337
 338         /* this is probably not totally correct.. but it's a start: */
 339         switch (param) {
 340         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 341         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 342         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 343         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 344                 return 16384;
 345
 346         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 347                 return vc4_screen(pscreen)->has_control_flow;
 348
 349         case PIPE_SHADER_CAP_MAX_INPUTS:
 350                 if (shader == PIPE_SHADER_FRAGMENT)
 351                         return 8;
 352                 else
 353                         return 16;
 354         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 355                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 356         case PIPE_SHADER_CAP_MAX_TEMPS:
 357                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 358         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 359                 return 16 * 1024 * sizeof(float);
 360         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 361                 return 1;
 362         case PIPE_SHADER_CAP_MAX_PREDS:
 363                 return 0; /* nothing uses this */
 364         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 365                 return 0;
 366         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 367         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 368         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 369                 return 0;
 370         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 371                 return 1;
 372         case PIPE_SHADER_CAP_SUBROUTINES:
 373                 return 0;
 374         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 375                 return 0;
 376         case PIPE_SHADER_CAP_INTEGERS:
 377                 return 1;
 378         case PIPE_SHADER_CAP_DOUBLES:
 379         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 380         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 381         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 382         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 383                 return 0;
 384         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 385         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 386                 return VC4_MAX_TEXTURE_SAMPLERS;
 387         case PIPE_SHADER_CAP_PREFERRED_IR:
 388                 return PIPE_SHADER_IR_TGSI;
 389         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 390                 return 0;
 391         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 392                 return 32;
 393         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 394         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 395                 return 0;
 396         default:
 397                 fprintf(stderr, "unknown shader param %d\n", param);
 398                 return 0;
 399         }
 400         return 0;
 401 }
 402
 403 static boolean
 404 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
 405                                enum pipe_format format,
 406                                enum pipe_texture_target target,
 407                                unsigned sample_count,
 408                                unsigned usage)
 409 {
 410         unsigned retval = 0;
 411
 412         if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
 413                 return FALSE;
 414
 415         if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
 416             !util_format_is_supported(format, usage)) {
 417                 return FALSE;
 418         }
 419
 420         if (usage & PIPE_BIND_VERTEX_BUFFER) {
 421                 switch (format) {
 422                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 423                 case PIPE_FORMAT_R32G32B32_FLOAT:
 424                 case PIPE_FORMAT_R32G32_FLOAT:
 425                 case PIPE_FORMAT_R32_FLOAT:
 426                 case PIPE_FORMAT_R32G32B32A32_SNORM:
 427                 case PIPE_FORMAT_R32G32B32_SNORM:
 428                 case PIPE_FORMAT_R32G32_SNORM:
 429                 case PIPE_FORMAT_R32_SNORM:
 430                 case PIPE_FORMAT_R32G32B32A32_SSCALED:
 431                 case PIPE_FORMAT_R32G32B32_SSCALED:
 432                 case PIPE_FORMAT_R32G32_SSCALED:
 433                 case PIPE_FORMAT_R32_SSCALED:
 434                 case PIPE_FORMAT_R16G16B16A16_UNORM:
 435                 case PIPE_FORMAT_R16G16B16_UNORM:
 436                 case PIPE_FORMAT_R16G16_UNORM:
 437                 case PIPE_FORMAT_R16_UNORM:
 438                 case PIPE_FORMAT_R16G16B16A16_SNORM:
 439                 case PIPE_FORMAT_R16G16B16_SNORM:
 440                 case PIPE_FORMAT_R16G16_SNORM:
 441                 case PIPE_FORMAT_R16_SNORM:
 442                 case PIPE_FORMAT_R16G16B16A16_USCALED:
 443                 case PIPE_FORMAT_R16G16B16_USCALED:
 444                 case PIPE_FORMAT_R16G16_USCALED:
 445                 case PIPE_FORMAT_R16_USCALED:
 446                 case PIPE_FORMAT_R16G16B16A16_SSCALED:
 447                 case PIPE_FORMAT_R16G16B16_SSCALED:
 448                 case PIPE_FORMAT_R16G16_SSCALED:
 449                 case PIPE_FORMAT_R16_SSCALED:
 450                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 451                 case PIPE_FORMAT_R8G8B8_UNORM:
 452                 case PIPE_FORMAT_R8G8_UNORM:
 453                 case PIPE_FORMAT_R8_UNORM:
 454                 case PIPE_FORMAT_R8G8B8A8_SNORM:
 455                 case PIPE_FORMAT_R8G8B8_SNORM:
 456                 case PIPE_FORMAT_R8G8_SNORM:
 457                 case PIPE_FORMAT_R8_SNORM:
 458                 case PIPE_FORMAT_R8G8B8A8_USCALED:
 459                 case PIPE_FORMAT_R8G8B8_USCALED:
 460                 case PIPE_FORMAT_R8G8_USCALED:
 461                 case PIPE_FORMAT_R8_USCALED:
 462                 case PIPE_FORMAT_R8G8B8A8_SSCALED:
 463                 case PIPE_FORMAT_R8G8B8_SSCALED:
 464                 case PIPE_FORMAT_R8G8_SSCALED:
 465                 case PIPE_FORMAT_R8_SSCALED:
 466                         retval |= PIPE_BIND_VERTEX_BUFFER;
 467                         break;
 468                 default:
 469                         break;
 470                 }
 471         }
 472
 473         if ((usage & PIPE_BIND_RENDER_TARGET) &&
 474             vc4_rt_format_supported(format)) {
 475                 retval |= PIPE_BIND_RENDER_TARGET;
 476         }
 477
 478         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 479             vc4_tex_format_supported(format)) {
 480                 retval |= PIPE_BIND_SAMPLER_VIEW;
 481         }
 482
 483         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 484             (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
 485              format == PIPE_FORMAT_X8Z24_UNORM)) {
 486                 retval |= PIPE_BIND_DEPTH_STENCIL;
 487         }
 488
 489         if ((usage & PIPE_BIND_INDEX_BUFFER) &&
 490             (format == PIPE_FORMAT_I8_UINT ||
 491              format == PIPE_FORMAT_I16_UINT)) {
 492                 retval |= PIPE_BIND_INDEX_BUFFER;
 493         }
 494
 495         if (usage & PIPE_BIND_TRANSFER_READ)
 496                 retval |= PIPE_BIND_TRANSFER_READ;
 497         if (usage & PIPE_BIND_TRANSFER_WRITE)
 498                 retval |= PIPE_BIND_TRANSFER_WRITE;
 499
 500 #if 0
 501         if (retval != usage) {
 502                 fprintf(stderr,
 503                         "not supported: format=%s, target=%d, sample_count=%d, "
 504                         "usage=0x%x, retval=0x%x\n", util_format_name(format),
 505                         target, sample_count, usage, retval);
 506         }
 507 #endif
 508
 509         return retval == usage;
 510 }
 511
 512 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 513
 514 static unsigned handle_hash(void *key)
 515 {
 516     return PTR_TO_UINT(key);
 517 }
 518
 519 static int handle_compare(void *key1, void *key2)
 520 {
 521     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 522 }
 523
 524 static bool
 525 vc4_supports_branches(struct vc4_screen *screen)
 526 {
 527 #if USE_VC4_SIMULATOR
 528         return true;
 529 #endif
 530
 531         struct drm_vc4_get_param p = {
 532                 .param = DRM_VC4_PARAM_SUPPORTS_BRANCHES,
 533         };
 534         int ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
 535
 536         if (ret != 0)
 537                 return false;
 538
 539         return p.value;
 540 }
 541
 542 static bool
 543 vc4_get_chip_info(struct vc4_screen *screen)
 544 {
 545 #if USE_VC4_SIMULATOR
 546         screen->v3d_ver = 21;
 547         return true;
 548 #endif
 549
 550         struct drm_vc4_get_param ident0 = {
 551                 .param = DRM_VC4_PARAM_V3D_IDENT0,
 552         };
 553         struct drm_vc4_get_param ident1 = {
 554                 .param = DRM_VC4_PARAM_V3D_IDENT1,
 555         };
 556         int ret;
 557
 558         ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
 559         if (ret != 0) {
 560                 if (errno == EINVAL) {
 561                         /* Backwards compatibility with 2835 kernels which
 562                          * only do V3D 2.1.
 563                          */
 564                         screen->v3d_ver = 21;
 565                         return true;
 566                 } else {
 567                         fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
 568                                 strerror(errno));
 569                         return false;
 570                 }
 571         }
 572         ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
 573         if (ret != 0) {
 574                 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
 575                         strerror(errno));
 576                 return false;
 577         }
 578
 579         uint32_t major = (ident0.value >> 24) & 0xff;
 580         uint32_t minor = (ident1.value >> 0) & 0xf;
 581         screen->v3d_ver = major * 10 + minor;
 582
 583         if (screen->v3d_ver != 21) {
 584                 fprintf(stderr,
 585                         "V3D %d.%d not supported by this version of Mesa.\n",
 586                         screen->v3d_ver / 10,
 587                         screen->v3d_ver % 10);
 588                 return false;
 589         }
 590
 591         return true;
 592 }
 593
 594 struct pipe_screen *
 595 vc4_screen_create(int fd)
 596 {
 597         struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
 598         struct pipe_screen *pscreen;
 599
 600         pscreen = &screen->base;
 601
 602         pscreen->destroy = vc4_screen_destroy;
 603         pscreen->get_param = vc4_screen_get_param;
 604         pscreen->get_paramf = vc4_screen_get_paramf;
 605         pscreen->get_shader_param = vc4_screen_get_shader_param;
 606         pscreen->context_create = vc4_context_create;
 607         pscreen->is_format_supported = vc4_screen_is_format_supported;
 608
 609         screen->fd = fd;
 610         list_inithead(&screen->bo_cache.time_list);
 611         pipe_mutex_init(screen->bo_handles_mutex);
 612         screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 613
 614         if (vc4_supports_branches(screen))
 615                 screen->has_control_flow = true;
 616
 617         if (!vc4_get_chip_info(screen))
 618                 goto fail;
 619
 620         vc4_fence_init(screen);
 621
 622         vc4_debug = debug_get_option_vc4_debug();
 623         if (vc4_debug & VC4_DEBUG_SHADERDB)
 624                 vc4_debug |= VC4_DEBUG_NORAST;
 625
 626 #if USE_VC4_SIMULATOR
 627         vc4_simulator_init(screen);
 628 #endif
 629
 630         vc4_resource_screen_init(pscreen);
 631
 632         pscreen->get_name = vc4_screen_get_name;
 633         pscreen->get_vendor = vc4_screen_get_vendor;
 634         pscreen->get_device_vendor = vc4_screen_get_vendor;
 635
 636         return pscreen;
 637
 638 fail:
 639         close(fd);
 640         ralloc_free(pscreen);
 641         return NULL;
 642 }
 643
 644 boolean
 645 vc4_screen_bo_get_handle(struct pipe_screen *pscreen,
 646                          struct vc4_bo *bo,
 647                          unsigned stride,
 648                          struct winsys_handle *whandle)
 649 {
 650         whandle->stride = stride;
 651
 652         /* If we're passing some reference to our BO out to some other part of
 653          * the system, then we can't do any optimizations about only us being
 654          * the ones seeing it (like BO caching or shadow update avoidance).
 655          */
 656         bo->private = false;
 657
 658         switch (whandle->type) {
 659         case DRM_API_HANDLE_TYPE_SHARED:
 660                 return vc4_bo_flink(bo, &whandle->handle);
 661         case DRM_API_HANDLE_TYPE_KMS:
 662                 whandle->handle = bo->handle;
 663                 return TRUE;
 664         case DRM_API_HANDLE_TYPE_FD:
 665                 whandle->handle = vc4_bo_get_dmabuf(bo);
 666                 return whandle->handle != -1;
 667         }
 668
 669         return FALSE;
 670 }
 671
 672 struct vc4_bo *
 673 vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
 674                           struct winsys_handle *whandle)
 675 {
 676         struct vc4_screen *screen = vc4_screen(pscreen);
 677
 678         if (whandle->offset != 0) {
 679                 fprintf(stderr,
 680                         "Attempt to import unsupported winsys offset %u\n",
 681                         whandle->offset);
 682                 return NULL;
 683         }
 684
 685         switch (whandle->type) {
 686         case DRM_API_HANDLE_TYPE_SHARED:
 687                 return vc4_bo_open_name(screen, whandle->handle, whandle->stride);
 688         case DRM_API_HANDLE_TYPE_FD:
 689                 return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride);
 690         default:
 691                 fprintf(stderr,
 692                         "Attempt to import unsupported handle type %d\n",
 693                         whandle->type);
 694                 return NULL;
 695         }
 696 }