src/gallium/drivers/vc4/vc4_state.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_helpers.h"
  30
  31 #include "vc4_context.h"
  32
  33 static void *
  34 vc4_generic_cso_state_create(const void *src, uint32_t size)
  35 {
  36         void *dst = calloc(1, size);
  37         if (!dst)
  38                 return NULL;
  39         memcpy(dst, src, size);
  40         return dst;
  41 }
  42
  43 static void
  44 vc4_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
  45 {
  46         free(hwcso);
  47 }
  48
  49 static void
  50 vc4_set_blend_color(struct pipe_context *pctx,
  51                     const struct pipe_blend_color *blend_color)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         vc4->blend_color = *blend_color;
  55         vc4->dirty |= VC4_DIRTY_BLEND_COLOR;
  56 }
  57
  58 static void
  59 vc4_set_stencil_ref(struct pipe_context *pctx,
  60                     const struct pipe_stencil_ref *stencil_ref)
  61 {
  62         struct vc4_context *vc4 = vc4_context(pctx);
  63         vc4->stencil_ref =* stencil_ref;
  64         vc4->dirty |= VC4_DIRTY_STENCIL_REF;
  65 }
  66
  67 static void
  68 vc4_set_clip_state(struct pipe_context *pctx,
  69                    const struct pipe_clip_state *clip)
  70 {
  71         struct vc4_context *vc4 = vc4_context(pctx);
  72         vc4->clip = *clip;
  73         vc4->dirty |= VC4_DIRTY_CLIP;
  74 }
  75
  76 static void
  77 vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  78 {
  79         struct vc4_context *vc4 = vc4_context(pctx);
  80         vc4->sample_mask = (uint16_t)sample_mask;
  81         vc4->dirty |= VC4_DIRTY_SAMPLE_MASK;
  82 }
  83
  84 static uint16_t
  85 float_to_187_half(float f)
  86 {
  87         return fui(f) >> 16;
  88 }
  89
  90 static void *
  91 vc4_create_rasterizer_state(struct pipe_context *pctx,
  92                             const struct pipe_rasterizer_state *cso)
  93 {
  94         struct vc4_rasterizer_state *so;
  95
  96         so = CALLOC_STRUCT(vc4_rasterizer_state);
  97         if (!so)
  98                 return NULL;
  99
 100         so->base = *cso;
 101
 102         if (!(cso->cull_face & PIPE_FACE_FRONT))
 103                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
 104         if (!(cso->cull_face & PIPE_FACE_BACK))
 105                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
 106
 107         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
 108          * BCM21553).
 109          */
 110         so->point_size = MAX2(cso->point_size, .125);
 111
 112         if (cso->front_ccw)
 113                 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
 114
 115         if (cso->offset_tri) {
 116                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
 117
 118                 so->offset_units = float_to_187_half(cso->offset_units);
 119                 so->offset_factor = float_to_187_half(cso->offset_scale);
 120         }
 121
 122         return so;
 123 }
 124
 125 /* Blend state is baked into shaders. */
 126 static void *
 127 vc4_create_blend_state(struct pipe_context *pctx,
 128                        const struct pipe_blend_state *cso)
 129 {
 130         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 131 }
 132
 133 /**
 134  * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
 135  * values, so you don't have to do a separate writemask setup.
 136  */
 137 static uint8_t
 138 tlb_stencil_setup_writemask(uint8_t mask)
 139 {
 140         switch (mask) {
 141         case 0x1: return 0;
 142         case 0x3: return 1;
 143         case 0xf: return 2;
 144         case 0xff: return 3;
 145         default: return 0xff;
 146         }
 147 }
 148
 149 static uint32_t
 150 tlb_stencil_setup_bits(const struct pipe_stencil_state *state,
 151                        uint8_t writemask_bits)
 152 {
 153         static const uint8_t op_map[] = {
 154                 [PIPE_STENCIL_OP_ZERO] = 0,
 155                 [PIPE_STENCIL_OP_KEEP] = 1,
 156                 [PIPE_STENCIL_OP_REPLACE] = 2,
 157                 [PIPE_STENCIL_OP_INCR] = 3,
 158                 [PIPE_STENCIL_OP_DECR] = 4,
 159                 [PIPE_STENCIL_OP_INVERT] = 5,
 160                 [PIPE_STENCIL_OP_INCR_WRAP] = 6,
 161                 [PIPE_STENCIL_OP_DECR_WRAP] = 7,
 162         };
 163         uint32_t bits = 0;
 164
 165         if (writemask_bits != 0xff)
 166                 bits |= writemask_bits << 28;
 167         bits |= op_map[state->zfail_op] << 25;
 168         bits |= op_map[state->zpass_op] << 22;
 169         bits |= op_map[state->fail_op] << 19;
 170         bits |= state->func << 16;
 171         /* Ref is filled in at uniform upload time */
 172         bits |= state->valuemask << 0;
 173
 174         return bits;
 175 }
 176
 177 static void *
 178 vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 179                                      const struct pipe_depth_stencil_alpha_state *cso)
 180 {
 181         struct vc4_depth_stencil_alpha_state *so;
 182
 183         so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
 184         if (!so)
 185                 return NULL;
 186
 187         so->base = *cso;
 188
 189         if (cso->depth.enabled) {
 190                 if (cso->depth.writemask) {
 191                         so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
 192                 }
 193                 so->config_bits[1] |= (cso->depth.func <<
 194                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 195         } else {
 196                 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
 197                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 198         }
 199
 200         if (cso->stencil[0].enabled) {
 201                 const struct pipe_stencil_state *front = &cso->stencil[0];
 202                 const struct pipe_stencil_state *back = &cso->stencil[1];
 203
 204                 uint8_t front_writemask_bits =
 205                         tlb_stencil_setup_writemask(front->writemask);
 206                 uint8_t back_writemask_bits =
 207                         tlb_stencil_setup_writemask(back->writemask);
 208
 209                 so->stencil_uniforms[0] =
 210                         tlb_stencil_setup_bits(front, front_writemask_bits);
 211                 if (back->enabled) {
 212                         so->stencil_uniforms[0] |= (1 << 30);
 213                         so->stencil_uniforms[1] =
 214                                 tlb_stencil_setup_bits(back, back_writemask_bits);
 215                         so->stencil_uniforms[1] |= (2 << 30);
 216                 } else {
 217                         so->stencil_uniforms[0] |= (3 << 30);
 218                 }
 219
 220                 if (front_writemask_bits == 0xff ||
 221                     back_writemask_bits == 0xff) {
 222                         so->stencil_uniforms[2] = (front_writemask_bits |
 223                                                    (back_writemask_bits << 8));
 224                 }
 225         }
 226
 227         return so;
 228 }
 229
 230 static void
 231 vc4_set_polygon_stipple(struct pipe_context *pctx,
 232                         const struct pipe_poly_stipple *stipple)
 233 {
 234         struct vc4_context *vc4 = vc4_context(pctx);
 235         vc4->stipple = *stipple;
 236         vc4->dirty |= VC4_DIRTY_STIPPLE;
 237 }
 238
 239 static void
 240 vc4_set_scissor_states(struct pipe_context *pctx,
 241                        unsigned start_slot,
 242                        unsigned num_scissors,
 243                        const struct pipe_scissor_state *scissor)
 244 {
 245         struct vc4_context *vc4 = vc4_context(pctx);
 246
 247         vc4->scissor = *scissor;
 248         vc4->dirty |= VC4_DIRTY_SCISSOR;
 249 }
 250
 251 static void
 252 vc4_set_viewport_states(struct pipe_context *pctx,
 253                         unsigned start_slot,
 254                         unsigned num_viewports,
 255                         const struct pipe_viewport_state *viewport)
 256 {
 257         struct vc4_context *vc4 = vc4_context(pctx);
 258         vc4->viewport = *viewport;
 259         vc4->dirty |= VC4_DIRTY_VIEWPORT;
 260 }
 261
 262 static void
 263 vc4_set_vertex_buffers(struct pipe_context *pctx,
 264                        unsigned start_slot, unsigned count,
 265                        const struct pipe_vertex_buffer *vb)
 266 {
 267         struct vc4_context *vc4 = vc4_context(pctx);
 268         struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
 269
 270         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
 271                                      start_slot, count);
 272         so->count = util_last_bit(so->enabled_mask);
 273
 274         vc4->dirty |= VC4_DIRTY_VTXBUF;
 275 }
 276
 277 static void
 278 vc4_set_index_buffer(struct pipe_context *pctx,
 279                      const struct pipe_index_buffer *ib)
 280 {
 281         struct vc4_context *vc4 = vc4_context(pctx);
 282
 283         if (ib) {
 284                 pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer);
 285                 vc4->indexbuf.index_size = ib->index_size;
 286                 vc4->indexbuf.offset = ib->offset;
 287                 vc4->indexbuf.user_buffer = ib->user_buffer;
 288         } else {
 289                 pipe_resource_reference(&vc4->indexbuf.buffer, NULL);
 290         }
 291
 292         vc4->dirty |= VC4_DIRTY_INDEXBUF;
 293 }
 294
 295 static void
 296 vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso)
 297 {
 298         struct vc4_context *vc4 = vc4_context(pctx);
 299         vc4->blend = hwcso;
 300         vc4->dirty |= VC4_DIRTY_BLEND;
 301 }
 302
 303 static void
 304 vc4_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
 305 {
 306         struct vc4_context *vc4 = vc4_context(pctx);
 307         struct vc4_rasterizer_state *rast = hwcso;
 308
 309         if (vc4->rasterizer && rast &&
 310             vc4->rasterizer->base.flatshade != rast->base.flatshade) {
 311                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
 312         }
 313
 314         vc4->rasterizer = hwcso;
 315         vc4->dirty |= VC4_DIRTY_RASTERIZER;
 316 }
 317
 318 static void
 319 vc4_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
 320 {
 321         struct vc4_context *vc4 = vc4_context(pctx);
 322         vc4->zsa = hwcso;
 323         vc4->dirty |= VC4_DIRTY_ZSA;
 324 }
 325
 326 static void *
 327 vc4_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
 328                         const struct pipe_vertex_element *elements)
 329 {
 330         struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
 331
 332         if (!so)
 333                 return NULL;
 334
 335         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
 336         so->num_elements = num_elements;
 337
 338         return so;
 339 }
 340
 341 static void
 342 vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
 343 {
 344         struct vc4_context *vc4 = vc4_context(pctx);
 345         vc4->vtx = hwcso;
 346         vc4->dirty |= VC4_DIRTY_VTXSTATE;
 347 }
 348
 349 static void
 350 vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
 351                         struct pipe_constant_buffer *cb)
 352 {
 353         struct vc4_context *vc4 = vc4_context(pctx);
 354         struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
 355
 356         assert(index == 0);
 357
 358         /* Note that the state tracker can unbind constant buffers by
 359          * passing NULL here.
 360          */
 361         if (unlikely(!cb)) {
 362                 so->enabled_mask &= ~(1 << index);
 363                 so->dirty_mask &= ~(1 << index);
 364                 return;
 365         }
 366
 367         assert(!cb->buffer);
 368         so->cb[index].buffer_offset = cb->buffer_offset;
 369         so->cb[index].buffer_size   = cb->buffer_size;
 370         so->cb[index].user_buffer   = cb->user_buffer;
 371
 372         so->enabled_mask |= 1 << index;
 373         so->dirty_mask |= 1 << index;
 374         vc4->dirty |= VC4_DIRTY_CONSTBUF;
 375 }
 376
 377 static void
 378 vc4_set_framebuffer_state(struct pipe_context *pctx,
 379                           const struct pipe_framebuffer_state *framebuffer)
 380 {
 381         struct vc4_context *vc4 = vc4_context(pctx);
 382         struct pipe_framebuffer_state *cso = &vc4->framebuffer;
 383         unsigned i;
 384
 385         vc4_flush(pctx);
 386
 387         for (i = 0; i < framebuffer->nr_cbufs; i++)
 388                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 389         for (; i < vc4->framebuffer.nr_cbufs; i++)
 390                 pipe_surface_reference(&cso->cbufs[i], NULL);
 391
 392         cso->nr_cbufs = framebuffer->nr_cbufs;
 393
 394         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 395
 396         cso->width = framebuffer->width;
 397         cso->height = framebuffer->height;
 398
 399         /* Nonzero texture mipmap levels are laid out as if they were in
 400          * power-of-two-sized spaces.  The renderbuffer config infers its
 401          * stride from the width parameter, so we need to configure our
 402          * framebuffer.  Note that if the z/color buffers were mismatched
 403          * sizes, we wouldn't be able to do this.
 404          */
 405         if (cso->cbufs[0] && cso->cbufs[0]->u.tex.level) {
 406                 struct vc4_resource *rsc =
 407                         vc4_resource(cso->cbufs[0]->texture);
 408                 cso->width =
 409                         (rsc->slices[cso->cbufs[0]->u.tex.level].stride /
 410                          rsc->cpp);
 411         } else if (cso->zsbuf && cso->zsbuf->u.tex.level){
 412                 struct vc4_resource *rsc =
 413                         vc4_resource(cso->zsbuf->texture);
 414                 cso->width =
 415                         (rsc->slices[cso->zsbuf->u.tex.level].stride /
 416                          rsc->cpp);
 417         }
 418
 419         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 420 }
 421
 422 static struct vc4_texture_stateobj *
 423 vc4_get_stage_tex(struct vc4_context *vc4, unsigned shader)
 424 {
 425         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 426
 427         switch (shader) {
 428         case PIPE_SHADER_FRAGMENT:
 429                 vc4->dirty |= VC4_DIRTY_FRAGTEX;
 430                 return &vc4->fragtex;
 431                 break;
 432         case PIPE_SHADER_VERTEX:
 433                 vc4->dirty |= VC4_DIRTY_VERTTEX;
 434                 return &vc4->verttex;
 435                 break;
 436         default:
 437                 fprintf(stderr, "Unknown shader target %d\n", shader);
 438                 abort();
 439         }
 440 }
 441
 442 static void *
 443 vc4_create_sampler_state(struct pipe_context *pctx,
 444                          const struct pipe_sampler_state *cso)
 445 {
 446         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 447 }
 448
 449 static void
 450 vc4_sampler_states_bind(struct pipe_context *pctx,
 451                         unsigned shader, unsigned start,
 452                         unsigned nr, void **hwcso)
 453 {
 454         struct vc4_context *vc4 = vc4_context(pctx);
 455         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 456
 457         assert(start == 0);
 458         unsigned i;
 459         unsigned new_nr = 0;
 460
 461         for (i = 0; i < nr; i++) {
 462                 if (hwcso[i])
 463                         new_nr = i + 1;
 464                 stage_tex->samplers[i] = hwcso[i];
 465                 stage_tex->dirty_samplers |= (1 << i);
 466         }
 467
 468         for (; i < stage_tex->num_samplers; i++) {
 469                 stage_tex->samplers[i] = NULL;
 470                 stage_tex->dirty_samplers |= (1 << i);
 471         }
 472
 473         stage_tex->num_samplers = new_nr;
 474 }
 475
 476 static struct pipe_sampler_view *
 477 vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
 478                         const struct pipe_sampler_view *cso)
 479 {
 480         struct pipe_sampler_view *so = malloc(sizeof(*so));
 481
 482         if (!so)
 483                 return NULL;
 484
 485         *so = *cso;
 486
 487         pipe_reference(NULL, &prsc->reference);
 488
 489         /* There is no hardware level clamping, and the start address of a
 490          * texture may be misaligned, so in that case we have to copy to a
 491          * temporary.
 492          */
 493         if (so->u.tex.first_level) {
 494                 struct vc4_resource *shadow_parent = vc4_resource(prsc);
 495                 struct pipe_resource tmpl = shadow_parent->base.b;
 496                 struct vc4_resource *clone;
 497
 498                 tmpl.width0 = u_minify(tmpl.width0, so->u.tex.first_level);
 499                 tmpl.height0 = u_minify(tmpl.height0, so->u.tex.first_level);
 500                 tmpl.last_level = so->u.tex.last_level - so->u.tex.first_level;
 501
 502                 prsc = vc4_resource_create(pctx->screen, &tmpl);
 503                 clone = vc4_resource(prsc);
 504                 clone->shadow_parent = &shadow_parent->base.b;
 505                 /* Flag it as needing update of the contents from the parent. */
 506                 clone->writes = shadow_parent->writes - 1;
 507         }
 508         so->texture = prsc;
 509         so->reference.count = 1;
 510         so->context = pctx;
 511
 512         return so;
 513 }
 514
 515 static void
 516 vc4_sampler_view_destroy(struct pipe_context *pctx,
 517                          struct pipe_sampler_view *view)
 518 {
 519         pipe_resource_reference(&view->texture, NULL);
 520         free(view);
 521 }
 522
 523 static void
 524 vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader,
 525                       unsigned start, unsigned nr,
 526                       struct pipe_sampler_view **views)
 527 {
 528         struct vc4_context *vc4 = vc4_context(pctx);
 529         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 530         unsigned i;
 531         unsigned new_nr = 0;
 532
 533         assert(start == 0);
 534
 535         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 536
 537         for (i = 0; i < nr; i++) {
 538                 if (views[i]) {
 539                         new_nr = i + 1;
 540                         if (views[i]->u.tex.first_level != 0)
 541                                 vc4_update_shadow_baselevel_texture(pctx, views[i]);
 542                 }
 543                 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
 544                 stage_tex->dirty_samplers |= (1 << i);
 545         }
 546
 547         for (; i < stage_tex->num_textures; i++) {
 548                 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
 549                 stage_tex->dirty_samplers |= (1 << i);
 550         }
 551
 552         stage_tex->num_textures = new_nr;
 553 }
 554
 555 void
 556 vc4_state_init(struct pipe_context *pctx)
 557 {
 558         pctx->set_blend_color = vc4_set_blend_color;
 559         pctx->set_stencil_ref = vc4_set_stencil_ref;
 560         pctx->set_clip_state = vc4_set_clip_state;
 561         pctx->set_sample_mask = vc4_set_sample_mask;
 562         pctx->set_constant_buffer = vc4_set_constant_buffer;
 563         pctx->set_framebuffer_state = vc4_set_framebuffer_state;
 564         pctx->set_polygon_stipple = vc4_set_polygon_stipple;
 565         pctx->set_scissor_states = vc4_set_scissor_states;
 566         pctx->set_viewport_states = vc4_set_viewport_states;
 567
 568         pctx->set_vertex_buffers = vc4_set_vertex_buffers;
 569         pctx->set_index_buffer = vc4_set_index_buffer;
 570
 571         pctx->create_blend_state = vc4_create_blend_state;
 572         pctx->bind_blend_state = vc4_blend_state_bind;
 573         pctx->delete_blend_state = vc4_generic_cso_state_delete;
 574
 575         pctx->create_rasterizer_state = vc4_create_rasterizer_state;
 576         pctx->bind_rasterizer_state = vc4_rasterizer_state_bind;
 577         pctx->delete_rasterizer_state = vc4_generic_cso_state_delete;
 578
 579         pctx->create_depth_stencil_alpha_state = vc4_create_depth_stencil_alpha_state;
 580         pctx->bind_depth_stencil_alpha_state = vc4_zsa_state_bind;
 581         pctx->delete_depth_stencil_alpha_state = vc4_generic_cso_state_delete;
 582
 583         pctx->create_vertex_elements_state = vc4_vertex_state_create;
 584         pctx->delete_vertex_elements_state = vc4_generic_cso_state_delete;
 585         pctx->bind_vertex_elements_state = vc4_vertex_state_bind;
 586
 587         pctx->create_sampler_state = vc4_create_sampler_state;
 588         pctx->delete_sampler_state = vc4_generic_cso_state_delete;
 589         pctx->bind_sampler_states = vc4_sampler_states_bind;
 590
 591         pctx->create_sampler_view = vc4_create_sampler_view;
 592         pctx->sampler_view_destroy = vc4_sampler_view_destroy;
 593         pctx->set_sampler_views = vc4_set_sampler_views;
 594 }