src/gallium/drivers/virgl/virgl_screen.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "util/u_memory.h"
  24 #include "util/format/u_format.h"
  25 #include "util/format/u_format_s3tc.h"
  26 #include "util/u_screen.h"
  27 #include "util/u_video.h"
  28 #include "util/u_math.h"
  29 #include "util/os_time.h"
  30 #include "util/xmlconfig.h"
  31 #include "pipe/p_defines.h"
  32 #include "pipe/p_screen.h"
  33
  34 #include "tgsi/tgsi_exec.h"
  35
  36 #include "virgl_screen.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_public.h"
  39 #include "virgl_context.h"
  40 #include "virgl_protocol.h"
  41
  42 int virgl_debug = 0;
  43 static const struct debug_named_value debug_options[] = {
  44    { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
  45    { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
  46    { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
  47    { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
  48    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
  49    { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
  50    DEBUG_NAMED_VALUE_END
  51 };
  52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
  53
  54 static const char *
  55 virgl_get_vendor(struct pipe_screen *screen)
  56 {
  57    return "Mesa/X.org";
  58 }
  59
  60
  61 static const char *
  62 virgl_get_name(struct pipe_screen *screen)
  63 {
  64    return "virgl";
  65 }
  66
  67 static int
  68 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
  69 {
  70    struct virgl_screen *vscreen = virgl_screen(screen);
  71    switch (param) {
  72    case PIPE_CAP_NPOT_TEXTURES:
  73       return 1;
  74    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77       return 1;
  78    case PIPE_CAP_ANISOTROPIC_FILTER:
  79       return 1;
  80    case PIPE_CAP_POINT_SPRITE:
  81       return 1;
  82    case PIPE_CAP_MAX_RENDER_TARGETS:
  83       return vscreen->caps.caps.v1.max_render_targets;
  84    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  85       return vscreen->caps.caps.v1.max_dual_source_render_targets;
  86    case PIPE_CAP_OCCLUSION_QUERY:
  87       return vscreen->caps.caps.v1.bset.occlusion_query;
  88    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  89    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  90       return vscreen->caps.caps.v1.bset.mirror_clamp;
  91    case PIPE_CAP_TEXTURE_SWIZZLE:
  92       return 1;
  93    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  94       if (vscreen->caps.caps.v2.max_texture_2d_size)
  95          return vscreen->caps.caps.v2.max_texture_2d_size;
  96       return 16384;
  97    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  98       if (vscreen->caps.caps.v2.max_texture_3d_size)
  99          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
 100       return 9; /* 256 x 256 x 256 */
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       if (vscreen->caps.caps.v2.max_texture_cube_size)
 103          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
 104       return 13; /* 4K x 4K */
 105    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106       return 1;
 107    case PIPE_CAP_INDEP_BLEND_ENABLE:
 108       return vscreen->caps.caps.v1.bset.indep_blend_enable;
 109    case PIPE_CAP_INDEP_BLEND_FUNC:
 110       return vscreen->caps.caps.v1.bset.indep_blend_func;
 111    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 112    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 113    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114       return 1;
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 116       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118       if (vscreen->caps.caps.v1.bset.depth_clip_disable)
 119          return 1;
 120       if (vscreen->caps.caps.v2.host_feature_check_version >= 3)
 121          return 2;
 122       return 0;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return vscreen->caps.caps.v1.max_streamout_buffers;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 16*4;
 128    case PIPE_CAP_PRIMITIVE_RESTART:
 129    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 130       return vscreen->caps.caps.v1.bset.primitive_restart;
 131    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 132       return vscreen->caps.caps.v1.bset.shader_stencil_export;
 133    case PIPE_CAP_TGSI_INSTANCEID:
 134    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 135       return 1;
 136    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 137       return vscreen->caps.caps.v1.bset.seamless_cube_map;
 138    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 139       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
 140    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 141       return vscreen->caps.caps.v1.max_texture_array_layers;
 142    case PIPE_CAP_MIN_TEXEL_OFFSET:
 143       return vscreen->caps.caps.v2.min_texel_offset;
 144    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 145       return vscreen->caps.caps.v2.min_texture_gather_offset;
 146    case PIPE_CAP_MAX_TEXEL_OFFSET:
 147       return vscreen->caps.caps.v2.max_texel_offset;
 148    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 149       return vscreen->caps.caps.v2.max_texture_gather_offset;
 150    case PIPE_CAP_CONDITIONAL_RENDER:
 151       return vscreen->caps.caps.v1.bset.conditional_render;
 152    case PIPE_CAP_TEXTURE_BARRIER:
 153       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
 154    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 155       return 1;
 156    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 157    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 158       return vscreen->caps.caps.v1.bset.color_clamping;
 159    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 160       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
 161             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 162    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 163       return vscreen->caps.caps.v1.glsl_level;
 164    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 165       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
 166    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 167    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 168       return 0;
 169    case PIPE_CAP_COMPUTE:
 170       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
 171    case PIPE_CAP_USER_VERTEX_BUFFERS:
 172       return 0;
 173    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 174       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
 175    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 176    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 177       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
 178    case PIPE_CAP_START_INSTANCE:
 179       return vscreen->caps.caps.v1.bset.start_instance;
 180    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 181    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 185       return 0;
 186    case PIPE_CAP_QUERY_TIMESTAMP:
 187       return 1;
 188    case PIPE_CAP_QUERY_TIME_ELAPSED:
 189       return 1;
 190    case PIPE_CAP_TGSI_TEXCOORD:
 191       return 0;
 192    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 193       return VIRGL_MAP_BUFFER_ALIGNMENT;
 194    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 195       return vscreen->caps.caps.v1.max_tbo_size > 0;
 196    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 197       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
 198    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 199       return 0;
 200    case PIPE_CAP_CUBE_MAP_ARRAY:
 201       return vscreen->caps.caps.v1.bset.cube_map_array;
 202    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 203       return vscreen->caps.caps.v1.bset.texture_multisample;
 204    case PIPE_CAP_MAX_VIEWPORTS:
 205       return vscreen->caps.caps.v1.max_viewports;
 206    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 207       return vscreen->caps.caps.v1.max_tbo_size;
 208    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 209    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 210    case PIPE_CAP_ENDIANNESS:
 211       return 0;
 212    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 213    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 214       return 1;
 215    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 216       return 0;
 217    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 218       return vscreen->caps.caps.v2.max_geom_output_vertices;
 219    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 220       return vscreen->caps.caps.v2.max_geom_total_output_components;
 221    case PIPE_CAP_TEXTURE_QUERY_LOD:
 222       return vscreen->caps.caps.v1.bset.texture_query_lod;
 223    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 224       return vscreen->caps.caps.v1.max_texture_gather_components;
 225    case PIPE_CAP_DRAW_INDIRECT:
 226       return vscreen->caps.caps.v1.bset.has_indirect_draw;
 227    case PIPE_CAP_SAMPLE_SHADING:
 228    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 229       return vscreen->caps.caps.v1.bset.has_sample_shading;
 230    case PIPE_CAP_CULL_DISTANCE:
 231       return vscreen->caps.caps.v1.bset.has_cull;
 232    case PIPE_CAP_MAX_VERTEX_STREAMS:
 233       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
 234               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
 235    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 236       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
 237    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 238       return vscreen->caps.caps.v1.bset.derivative_control;
 239    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 240       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
 241    case PIPE_CAP_QUERY_SO_OVERFLOW:
 242       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
 245    case PIPE_CAP_DOUBLES:
 246       return vscreen->caps.caps.v1.bset.has_fp64 ||
 247             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
 248    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 249       return vscreen->caps.caps.v2.max_shader_patch_varyings;
 250    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 251       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
 252    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 253       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
 254    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 255       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
 256    case PIPE_CAP_TGSI_TXQS:
 257       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
 258    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 259       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
 260    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 261       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
 262    case PIPE_CAP_FBFETCH:
 263       return (vscreen->caps.caps.v2.capability_bits &
 264               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
 265    case PIPE_CAP_TGSI_CLOCK:
 266       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
 267    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 268       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
 269    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 270       return vscreen->caps.caps.v2.max_combined_shader_buffers;
 271    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 272       return vscreen->caps.caps.v2.max_combined_atomic_counters;
 273    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 274       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
 275    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 276    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 277       return 1; /* TODO: need to introduce a hw-cap for this */
 278    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 279       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
 280    case PIPE_CAP_MAX_VARYINGS:
 281       if (vscreen->caps.caps.v1.glsl_level < 150)
 282          return vscreen->caps.caps.v2.max_vertex_attribs;
 283       return 32;
 284    case PIPE_CAP_FAKE_SW_MSAA:
 285       /* If the host supports only one sample (e.g., if it is using softpipe),
 286        * fake multisampling to able to advertise higher GL versions. */
 287       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
 288    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 289       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
 290    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 291       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
 292    case PIPE_CAP_TEXTURE_GATHER_SM5:
 293    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 294    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 295    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 296    case PIPE_CAP_VERTEXID_NOBASE:
 297    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 298    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 299    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 300    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 301    case PIPE_CAP_SHAREABLE_SHADERS:
 302    case PIPE_CAP_DRAW_PARAMETERS:
 303    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 304    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 306    case PIPE_CAP_INVALIDATE_BUFFER:
 307    case PIPE_CAP_GENERATE_MIPMAP:
 308    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 309    case PIPE_CAP_STRING_MARKER:
 310    case PIPE_CAP_QUERY_MEMORY_INFO:
 311    case PIPE_CAP_PCI_GROUP:
 312    case PIPE_CAP_PCI_BUS:
 313    case PIPE_CAP_PCI_DEVICE:
 314    case PIPE_CAP_PCI_FUNCTION:
 315    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 316    case PIPE_CAP_TGSI_VOTE:
 317    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 318    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 319    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 320    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 321    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 322    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 323    case PIPE_CAP_INT64:
 324    case PIPE_CAP_INT64_DIVMOD:
 325    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 326    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 327    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 328    case PIPE_CAP_TGSI_BALLOT:
 329    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 330    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 331    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 332    case PIPE_CAP_POST_DEPTH_COVERAGE:
 333    case PIPE_CAP_BINDLESS_TEXTURE:
 334    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 335    case PIPE_CAP_MEMOBJ:
 336    case PIPE_CAP_LOAD_CONSTBUF:
 337    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 338    case PIPE_CAP_TILE_RASTER_ORDER:
 339    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 340    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 341    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 342    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 343    case PIPE_CAP_FENCE_SIGNAL:
 344    case PIPE_CAP_CONSTBUF0_FLAGS:
 345    case PIPE_CAP_PACKED_UNIFORMS:
 346    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 347    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 348    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 349    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 350    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 351    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 352    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 353    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 354       return 0;
 355    case PIPE_CAP_CLEAR_TEXTURE:
 356       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
 357    case PIPE_CAP_CLIP_HALFZ:
 358       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
 359    case PIPE_CAP_MAX_GS_INVOCATIONS:
 360       return 32;
 361    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 362       return 1 << 27;
 363    case PIPE_CAP_VENDOR_ID:
 364       return 0x1af4;
 365    case PIPE_CAP_DEVICE_ID:
 366       return 0x1010;
 367    case PIPE_CAP_ACCELERATED:
 368       return 1;
 369    case PIPE_CAP_UMA:
 370    case PIPE_CAP_VIDEO_MEMORY:
 371       return 0;
 372    case PIPE_CAP_NATIVE_FENCE_FD:
 373       return vscreen->vws->supports_fences;
 374    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 375       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
 376             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 377    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 378       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 379    default:
 380       return u_pipe_screen_get_param_defaults(screen, param);
 381    }
 382 }
 383
 384 static int
 385 virgl_get_shader_param(struct pipe_screen *screen,
 386                        enum pipe_shader_type shader,
 387                        enum pipe_shader_cap param)
 388 {
 389    struct virgl_screen *vscreen = virgl_screen(screen);
 390
 391    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
 392        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
 393       return 0;
 394
 395    if (shader == PIPE_SHADER_COMPUTE &&
 396        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 397      return 0;
 398
 399    switch(shader)
 400    {
 401    case PIPE_SHADER_FRAGMENT:
 402    case PIPE_SHADER_VERTEX:
 403    case PIPE_SHADER_GEOMETRY:
 404    case PIPE_SHADER_TESS_CTRL:
 405    case PIPE_SHADER_TESS_EVAL:
 406    case PIPE_SHADER_COMPUTE:
 407       switch (param) {
 408       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 409       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 410       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 411       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 412          return INT_MAX;
 413       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 414       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 415       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 416          return 1;
 417       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 418       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 419          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 420       case PIPE_SHADER_CAP_MAX_INPUTS:
 421          if (vscreen->caps.caps.v1.glsl_level < 150)
 422             return vscreen->caps.caps.v2.max_vertex_attribs;
 423          return (shader == PIPE_SHADER_VERTEX ||
 424                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
 425       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 426          if (shader == PIPE_SHADER_FRAGMENT)
 427             return vscreen->caps.caps.v1.max_render_targets;
 428          return vscreen->caps.caps.v2.max_vertex_outputs;
 429      // case PIPE_SHADER_CAP_MAX_CONSTS:
 430      //    return 4096;
 431       case PIPE_SHADER_CAP_MAX_TEMPS:
 432          return 256;
 433       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 434          return vscreen->caps.caps.v1.max_uniform_blocks;
 435     //  case PIPE_SHADER_CAP_MAX_ADDRS:
 436      //    return 1;
 437       case PIPE_SHADER_CAP_SUBROUTINES:
 438          return 1;
 439       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 440             return 16;
 441       case PIPE_SHADER_CAP_INTEGERS:
 442          return vscreen->caps.caps.v1.glsl_level >= 130;
 443       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 444          return 32;
 445       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 446          return 4096 * sizeof(float[4]);
 447       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 448          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 449             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
 450          else
 451             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
 452       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 453          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 454             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
 455          else
 456             return vscreen->caps.caps.v2.max_shader_image_other_stages;
 457       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 458          return (1 << PIPE_SHADER_IR_TGSI);
 459       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 460          return vscreen->caps.caps.v2.max_atomic_counters[shader];
 461       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 462          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
 463       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 464       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 465       case PIPE_SHADER_CAP_INT64_ATOMICS:
 466       case PIPE_SHADER_CAP_FP16:
 467       case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 468       case PIPE_SHADER_CAP_INT16:
 469       case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
 470          return 0;
 471       default:
 472          return 0;
 473       }
 474    default:
 475       return 0;
 476    }
 477 }
 478
 479 static float
 480 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 481 {
 482    struct virgl_screen *vscreen = virgl_screen(screen);
 483    switch (param) {
 484    case PIPE_CAPF_MAX_LINE_WIDTH:
 485       return vscreen->caps.caps.v2.max_aliased_line_width;
 486    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 487       return vscreen->caps.caps.v2.max_smooth_line_width;
 488    case PIPE_CAPF_MAX_POINT_WIDTH:
 489       return vscreen->caps.caps.v2.max_aliased_point_size;
 490    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 491       return vscreen->caps.caps.v2.max_smooth_point_size;
 492    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 493       return 16.0;
 494    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 495       return vscreen->caps.caps.v2.max_texture_lod_bias;
 496    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 497    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 498    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 499       return 0.0f;
 500    }
 501    /* should only get here on unhandled cases */
 502    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 503    return 0.0;
 504 }
 505
 506 static int
 507 virgl_get_compute_param(struct pipe_screen *screen,
 508                         enum pipe_shader_ir ir_type,
 509                         enum pipe_compute_cap param,
 510                         void *ret)
 511 {
 512    struct virgl_screen *vscreen = virgl_screen(screen);
 513    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 514       return 0;
 515    switch (param) {
 516    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 517       if (ret) {
 518          uint64_t *grid_size = ret;
 519          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
 520          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
 521          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
 522       }
 523       return 3 * sizeof(uint64_t) ;
 524    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 525       if (ret) {
 526          uint64_t *block_size = ret;
 527          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
 528          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
 529          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
 530       }
 531       return 3 * sizeof(uint64_t);
 532    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 533       if (ret) {
 534          uint64_t *max_threads_per_block = ret;
 535          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
 536       }
 537       return sizeof(uint64_t);
 538    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 539       if (ret) {
 540          uint64_t *max_local_size = ret;
 541          /* Value reported by the closed source driver. */
 542          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
 543       }
 544       return sizeof(uint64_t);
 545    default:
 546       break;
 547    }
 548    return 0;
 549 }
 550
 551 static bool
 552 has_format_bit(struct virgl_supported_format_mask *mask,
 553                enum virgl_formats fmt)
 554 {
 555    assert(fmt < VIRGL_FORMAT_MAX);
 556    unsigned val = (unsigned)fmt;
 557    unsigned idx = val / 32;
 558    unsigned bit = val % 32;
 559    assert(idx < ARRAY_SIZE(mask->bitmask));
 560    return (mask->bitmask[idx] & (1u << bit)) != 0;
 561 }
 562
 563 bool
 564 virgl_has_readback_format(struct pipe_screen *screen,
 565                           enum virgl_formats fmt)
 566 {
 567    struct virgl_screen *vscreen = virgl_screen(screen);
 568    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
 569                          fmt);
 570 }
 571
 572 static bool
 573 virgl_is_vertex_format_supported(struct pipe_screen *screen,
 574                                  enum pipe_format format)
 575 {
 576    struct virgl_screen *vscreen = virgl_screen(screen);
 577    const struct util_format_description *format_desc;
 578    int i;
 579
 580    format_desc = util_format_description(format);
 581    if (!format_desc)
 582       return false;
 583
 584    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 585       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
 586       int big = vformat / 32;
 587       int small = vformat % 32;
 588       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
 589          return false;
 590       return true;
 591    }
 592
 593    /* Find the first non-VOID channel. */
 594    for (i = 0; i < 4; i++) {
 595       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 596          break;
 597       }
 598    }
 599
 600    if (i == 4)
 601       return false;
 602
 603    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 604       return false;
 605
 606    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
 607       return false;
 608    return true;
 609 }
 610
 611 static bool
 612 virgl_format_check_bitmask(enum pipe_format format,
 613                            uint32_t bitmask[16],
 614                            bool may_emulate_bgra)
 615 {
 616    enum virgl_formats vformat = pipe_to_virgl_format(format);
 617    int big = vformat / 32;
 618    int small = vformat % 32;
 619    if ((bitmask[big] & (1 << small)))
 620       return true;
 621
 622    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
 623     * emulate it by using a swizzled RGBx */
 624    if (may_emulate_bgra) {
 625       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
 626          format = PIPE_FORMAT_R8G8B8A8_SRGB;
 627       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
 628          format = PIPE_FORMAT_R8G8B8X8_SRGB;
 629       else {
 630          return false;
 631       }
 632
 633       vformat = pipe_to_virgl_format(format);
 634       big = vformat / 32;
 635       small = vformat % 32;
 636       if (bitmask[big] & (1 << small))
 637          return true;
 638    }
 639    return false;
 640 }
 641
 642 /**
 643  * Query format support for creating a texture, drawing surface, etc.
 644  * \param format  the format to test
 645  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 646  */
 647 static bool
 648 virgl_is_format_supported( struct pipe_screen *screen,
 649                                  enum pipe_format format,
 650                                  enum pipe_texture_target target,
 651                                  unsigned sample_count,
 652                                  unsigned storage_sample_count,
 653                                  unsigned bind)
 654 {
 655    struct virgl_screen *vscreen = virgl_screen(screen);
 656    const struct util_format_description *format_desc;
 657    int i;
 658
 659    union virgl_caps *caps = &vscreen->caps.caps;
 660    boolean may_emulate_bgra = (caps->v2.capability_bits &
 661                                VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 662                                vscreen->tweak_gles_emulate_bgra;
 663
 664    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 665       return false;
 666
 667    if (!util_is_power_of_two_or_zero(sample_count))
 668       return false;
 669
 670    assert(target == PIPE_BUFFER ||
 671           target == PIPE_TEXTURE_1D ||
 672           target == PIPE_TEXTURE_1D_ARRAY ||
 673           target == PIPE_TEXTURE_2D ||
 674           target == PIPE_TEXTURE_2D_ARRAY ||
 675           target == PIPE_TEXTURE_RECT ||
 676           target == PIPE_TEXTURE_3D ||
 677           target == PIPE_TEXTURE_CUBE ||
 678           target == PIPE_TEXTURE_CUBE_ARRAY);
 679
 680    format_desc = util_format_description(format);
 681    if (!format_desc)
 682       return false;
 683
 684    if (util_format_is_intensity(format))
 685       return false;
 686
 687    if (sample_count > 1) {
 688       if (!caps->v1.bset.texture_multisample)
 689          return false;
 690
 691       if (bind & PIPE_BIND_SHADER_IMAGE) {
 692          if (sample_count > caps->v2.max_image_samples)
 693             return false;
 694       }
 695
 696       if (sample_count > caps->v1.max_samples)
 697          return false;
 698    }
 699
 700    if (bind & PIPE_BIND_VERTEX_BUFFER) {
 701       return virgl_is_vertex_format_supported(screen, format);
 702    }
 703
 704    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
 705       return false;
 706
 707    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
 708    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
 709        format == PIPE_FORMAT_R32G32B32_SINT ||
 710        format == PIPE_FORMAT_R32G32B32_UINT) &&
 711        target != PIPE_BUFFER)
 712       return false;
 713
 714    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
 715         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
 716         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
 717        target == PIPE_TEXTURE_3D)
 718       return false;
 719
 720
 721    if (bind & PIPE_BIND_RENDER_TARGET) {
 722       /* For ARB_framebuffer_no_attachments. */
 723       if (format == PIPE_FORMAT_NONE)
 724          return TRUE;
 725
 726       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 727          return false;
 728
 729       /*
 730        * Although possible, it is unnatural to render into compressed or YUV
 731        * surfaces. So disable these here to avoid going into weird paths
 732        * inside gallium frontends.
 733        */
 734       if (format_desc->block.width != 1 ||
 735           format_desc->block.height != 1)
 736          return false;
 737
 738       if (!virgl_format_check_bitmask(format,
 739                                       caps->v1.render.bitmask,
 740                                       may_emulate_bgra))
 741          return false;
 742    }
 743
 744    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 745       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 746          return false;
 747    }
 748
 749    if (bind & PIPE_BIND_SCANOUT) {
 750       if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
 751          return false;
 752    }
 753
 754    /*
 755     * All other operations (sampling, transfer, etc).
 756     */
 757
 758    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 759       goto out_lookup;
 760    }
 761    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 762       goto out_lookup;
 763    }
 764    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
 765       goto out_lookup;
 766    }
 767    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
 768       goto out_lookup;
 769    }
 770
 771    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 772       goto out_lookup;
 773    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 774       goto out_lookup;
 775    }
 776
 777    /* Find the first non-VOID channel. */
 778    for (i = 0; i < 4; i++) {
 779       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 780          break;
 781       }
 782    }
 783
 784    if (i == 4)
 785       return false;
 786
 787    /* no L4A4 */
 788    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
 789       return false;
 790
 791  out_lookup:
 792    return virgl_format_check_bitmask(format,
 793                                      caps->v1.sampler.bitmask,
 794                                      may_emulate_bgra);
 795 }
 796
 797 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
 798                                       struct pipe_resource *res,
 799                                       unsigned level, unsigned layer,
 800                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
 801 {
 802    struct virgl_screen *vscreen = virgl_screen(screen);
 803    struct virgl_winsys *vws = vscreen->vws;
 804    struct virgl_resource *vres = virgl_resource(res);
 805
 806    if (vws->flush_frontbuffer)
 807       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
 808                              sub_box);
 809 }
 810
 811 static void virgl_fence_reference(struct pipe_screen *screen,
 812                                   struct pipe_fence_handle **ptr,
 813                                   struct pipe_fence_handle *fence)
 814 {
 815    struct virgl_screen *vscreen = virgl_screen(screen);
 816    struct virgl_winsys *vws = vscreen->vws;
 817
 818    vws->fence_reference(vws, ptr, fence);
 819 }
 820
 821 static bool virgl_fence_finish(struct pipe_screen *screen,
 822                                struct pipe_context *ctx,
 823                                struct pipe_fence_handle *fence,
 824                                uint64_t timeout)
 825 {
 826    struct virgl_screen *vscreen = virgl_screen(screen);
 827    struct virgl_winsys *vws = vscreen->vws;
 828
 829    return vws->fence_wait(vws, fence, timeout);
 830 }
 831
 832 static int virgl_fence_get_fd(struct pipe_screen *screen,
 833             struct pipe_fence_handle *fence)
 834 {
 835    struct virgl_screen *vscreen = virgl_screen(screen);
 836    struct virgl_winsys *vws = vscreen->vws;
 837
 838    return vws->fence_get_fd(vws, fence);
 839 }
 840
 841 static uint64_t
 842 virgl_get_timestamp(struct pipe_screen *_screen)
 843 {
 844    return os_time_get_nano();
 845 }
 846
 847 static void
 848 virgl_destroy_screen(struct pipe_screen *screen)
 849 {
 850    struct virgl_screen *vscreen = virgl_screen(screen);
 851    struct virgl_winsys *vws = vscreen->vws;
 852
 853    slab_destroy_parent(&vscreen->transfer_pool);
 854
 855    if (vws)
 856       vws->destroy(vws);
 857    FREE(vscreen);
 858 }
 859
 860 static void
 861 fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
 862 {
 863    const size_t size = ARRAY_SIZE(mask->bitmask);
 864    for (int i = 0; i < size; ++i) {
 865       if (mask->bitmask[i] != 0)
 866          return; /* we got some formats, we definately have a new protocol */
 867    }
 868
 869    /* old protocol used; fall back to considering all sampleable formats valid
 870     * readback-formats
 871     */
 872    for (int i = 0; i < size; ++i)
 873       mask->bitmask[i] = caps->v1.sampler.bitmask[i];
 874 }
 875
 876 struct pipe_screen *
 877 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
 878 {
 879    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
 880
 881    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
 882    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
 883    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
 884
 885    if (!screen)
 886       return NULL;
 887
 888    virgl_debug = debug_get_option_virgl_debug();
 889
 890    if (config && config->options) {
 891       screen->tweak_gles_emulate_bgra =
 892             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
 893       screen->tweak_gles_apply_bgra_dest_swizzle =
 894             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
 895       screen->tweak_gles_tf3_value =
 896             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
 897    }
 898
 899    screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
 900    screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
 901
 902    screen->vws = vws;
 903    screen->base.get_name = virgl_get_name;
 904    screen->base.get_vendor = virgl_get_vendor;
 905    screen->base.get_param = virgl_get_param;
 906    screen->base.get_shader_param = virgl_get_shader_param;
 907    screen->base.get_compute_param = virgl_get_compute_param;
 908    screen->base.get_paramf = virgl_get_paramf;
 909    screen->base.is_format_supported = virgl_is_format_supported;
 910    screen->base.destroy = virgl_destroy_screen;
 911    screen->base.context_create = virgl_context_create;
 912    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
 913    screen->base.get_timestamp = virgl_get_timestamp;
 914    screen->base.fence_reference = virgl_fence_reference;
 915    //screen->base.fence_signalled = virgl_fence_signalled;
 916    screen->base.fence_finish = virgl_fence_finish;
 917    screen->base.fence_get_fd = virgl_fence_get_fd;
 918
 919    virgl_init_screen_resource_functions(&screen->base);
 920
 921    vws->get_caps(vws, &screen->caps);
 922    fixup_formats(&screen->caps.caps,
 923                  &screen->caps.caps.v2.supported_readback_formats);
 924    fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
 925
 926    screen->refcnt = 1;
 927
 928    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 929
 930    return &screen->base;
 931 }