src/gallium/drivers/virgl/virgl_screen.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "util/u_memory.h"
  24 #include "util/u_format.h"
  25 #include "util/u_format_s3tc.h"
  26 #include "util/u_screen.h"
  27 #include "util/u_video.h"
  28 #include "util/u_math.h"
  29 #include "util/os_time.h"
  30 #include "util/xmlconfig.h"
  31 #include "pipe/p_defines.h"
  32 #include "pipe/p_screen.h"
  33
  34 #include "tgsi/tgsi_exec.h"
  35
  36 #include "virgl_screen.h"
  37 #include "virgl_resource.h"
  38 #include "virgl_public.h"
  39 #include "virgl_context.h"
  40 #include "virgl_protocol.h"
  41
  42 int virgl_debug = 0;
  43 static const struct debug_named_value debug_options[] = {
  44    { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
  45    { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
  46    { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
  47    { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
  48    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
  49    { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
  50    DEBUG_NAMED_VALUE_END
  51 };
  52 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
  53
  54 static const char *
  55 virgl_get_vendor(struct pipe_screen *screen)
  56 {
  57    return "Red Hat";
  58 }
  59
  60
  61 static const char *
  62 virgl_get_name(struct pipe_screen *screen)
  63 {
  64    return "virgl";
  65 }
  66
  67 static int
  68 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
  69 {
  70    struct virgl_screen *vscreen = virgl_screen(screen);
  71    switch (param) {
  72    case PIPE_CAP_NPOT_TEXTURES:
  73       return 1;
  74    case PIPE_CAP_SM3:
  75       return 1;
  76    case PIPE_CAP_ANISOTROPIC_FILTER:
  77       return 1;
  78    case PIPE_CAP_POINT_SPRITE:
  79       return 1;
  80    case PIPE_CAP_MAX_RENDER_TARGETS:
  81       return vscreen->caps.caps.v1.max_render_targets;
  82    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  83       return vscreen->caps.caps.v1.max_dual_source_render_targets;
  84    case PIPE_CAP_OCCLUSION_QUERY:
  85       return vscreen->caps.caps.v1.bset.occlusion_query;
  86    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  87    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  88       return vscreen->caps.caps.v1.bset.mirror_clamp;
  89    case PIPE_CAP_TEXTURE_SWIZZLE:
  90       return 1;
  91    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  92       if (vscreen->caps.caps.v2.max_texture_2d_size)
  93          return vscreen->caps.caps.v2.max_texture_2d_size;
  94       return 16384;
  95    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  96       if (vscreen->caps.caps.v2.max_texture_3d_size)
  97          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
  98       return 9; /* 256 x 256 x 256 */
  99    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 100       if (vscreen->caps.caps.v2.max_texture_cube_size)
 101          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
 102       return 13; /* 4K x 4K */
 103    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 104       return 1;
 105    case PIPE_CAP_INDEP_BLEND_ENABLE:
 106       return vscreen->caps.caps.v1.bset.indep_blend_enable;
 107    case PIPE_CAP_INDEP_BLEND_FUNC:
 108       return vscreen->caps.caps.v1.bset.indep_blend_func;
 109    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 110    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 111    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 112       return 1;
 113    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 114       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
 115    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 116       return vscreen->caps.caps.v1.bset.depth_clip_disable;
 117    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 118       return vscreen->caps.caps.v1.max_streamout_buffers;
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 121       return 16*4;
 122    case PIPE_CAP_PRIMITIVE_RESTART:
 123       return vscreen->caps.caps.v1.bset.primitive_restart;
 124    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 125       return vscreen->caps.caps.v1.bset.shader_stencil_export;
 126    case PIPE_CAP_TGSI_INSTANCEID:
 127    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 128       return 1;
 129    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 130       return vscreen->caps.caps.v1.bset.seamless_cube_map;
 131    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 132       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
 133    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 134       return vscreen->caps.caps.v1.max_texture_array_layers;
 135    case PIPE_CAP_MIN_TEXEL_OFFSET:
 136       return vscreen->caps.caps.v2.min_texel_offset;
 137    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 138       return vscreen->caps.caps.v2.min_texture_gather_offset;
 139    case PIPE_CAP_MAX_TEXEL_OFFSET:
 140       return vscreen->caps.caps.v2.max_texel_offset;
 141    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 142       return vscreen->caps.caps.v2.max_texture_gather_offset;
 143    case PIPE_CAP_CONDITIONAL_RENDER:
 144       return vscreen->caps.caps.v1.bset.conditional_render;
 145    case PIPE_CAP_TEXTURE_BARRIER:
 146       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
 147    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 148       return 1;
 149    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 150    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 151       return vscreen->caps.caps.v1.bset.color_clamping;
 152    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 153       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
 154             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 155    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 156       return vscreen->caps.caps.v1.glsl_level;
 157    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 158       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
 159    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 160    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 161       return 0;
 162    case PIPE_CAP_COMPUTE:
 163       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
 164    case PIPE_CAP_USER_VERTEX_BUFFERS:
 165       return 0;
 166    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 167       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
 168    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 169    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 170       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
 171    case PIPE_CAP_START_INSTANCE:
 172       return vscreen->caps.caps.v1.bset.start_instance;
 173    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 174    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 175    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 176    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 177    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 178       return 0;
 179    case PIPE_CAP_QUERY_TIMESTAMP:
 180       return 1;
 181    case PIPE_CAP_QUERY_TIME_ELAPSED:
 182       return 1;
 183    case PIPE_CAP_TGSI_TEXCOORD:
 184       return 0;
 185    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 186       return VIRGL_MAP_BUFFER_ALIGNMENT;
 187    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 188       return vscreen->caps.caps.v1.max_tbo_size > 0;
 189    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
 191    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 192       return 0;
 193    case PIPE_CAP_CUBE_MAP_ARRAY:
 194       return vscreen->caps.caps.v1.bset.cube_map_array;
 195    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 196       return vscreen->caps.caps.v1.bset.texture_multisample;
 197    case PIPE_CAP_MAX_VIEWPORTS:
 198       return vscreen->caps.caps.v1.max_viewports;
 199    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 200       return vscreen->caps.caps.v1.max_tbo_size;
 201    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 202    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 203    case PIPE_CAP_ENDIANNESS:
 204       return 0;
 205    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 206    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 207       return 1;
 208    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 209       return 0;
 210    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 211       return vscreen->caps.caps.v2.max_geom_output_vertices;
 212    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 213       return vscreen->caps.caps.v2.max_geom_total_output_components;
 214    case PIPE_CAP_TEXTURE_QUERY_LOD:
 215       return vscreen->caps.caps.v1.bset.texture_query_lod;
 216    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 217       return vscreen->caps.caps.v1.max_texture_gather_components;
 218    case PIPE_CAP_DRAW_INDIRECT:
 219       return vscreen->caps.caps.v1.bset.has_indirect_draw;
 220    case PIPE_CAP_SAMPLE_SHADING:
 221    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 222       return vscreen->caps.caps.v1.bset.has_sample_shading;
 223    case PIPE_CAP_CULL_DISTANCE:
 224       return vscreen->caps.caps.v1.bset.has_cull;
 225    case PIPE_CAP_MAX_VERTEX_STREAMS:
 226       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
 227               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
 228    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 229       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
 230    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 231       return vscreen->caps.caps.v1.bset.derivative_control;
 232    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 233       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
 234    case PIPE_CAP_QUERY_SO_OVERFLOW:
 235       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
 236    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 237       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
 238    case PIPE_CAP_DOUBLES:
 239       return vscreen->caps.caps.v1.bset.has_fp64 ||
 240             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
 241    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 242       return vscreen->caps.caps.v2.max_shader_patch_varyings;
 243    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 244       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
 245    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 246       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
 247    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 248       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
 249    case PIPE_CAP_TGSI_TXQS:
 250       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
 251    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 252       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
 253    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 254       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
 255    case PIPE_CAP_FBFETCH:
 256       return (vscreen->caps.caps.v2.capability_bits &
 257               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
 258    case PIPE_CAP_TGSI_CLOCK:
 259       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
 260    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 261       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
 262    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 263       return vscreen->caps.caps.v2.max_combined_shader_buffers;
 264    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 265       return vscreen->caps.caps.v2.max_combined_atomic_counters;
 266    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 267       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
 268    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 269    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 270       return 1; /* TODO: need to introduce a hw-cap for this */
 271    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 272       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
 273    case PIPE_CAP_MAX_VARYINGS:
 274       if (vscreen->caps.caps.v1.glsl_level < 150)
 275          return vscreen->caps.caps.v2.max_vertex_attribs;
 276       return 32;
 277    case PIPE_CAP_FAKE_SW_MSAA:
 278       /* If the host supports only one sample (e.g., if it is using softpipe),
 279        * fake multisampling to able to advertise higher GL versions. */
 280       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
 281    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 282       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
 283    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 284       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
 285    case PIPE_CAP_TEXTURE_GATHER_SM5:
 286    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 287    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 288    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 289    case PIPE_CAP_VERTEXID_NOBASE:
 290    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 291    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 292    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 293    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 294    case PIPE_CAP_SHAREABLE_SHADERS:
 295    case PIPE_CAP_CLEAR_TEXTURE:
 296    case PIPE_CAP_DRAW_PARAMETERS:
 297    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 298    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 299    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 300    case PIPE_CAP_INVALIDATE_BUFFER:
 301    case PIPE_CAP_GENERATE_MIPMAP:
 302    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 303    case PIPE_CAP_STRING_MARKER:
 304    case PIPE_CAP_QUERY_MEMORY_INFO:
 305    case PIPE_CAP_PCI_GROUP:
 306    case PIPE_CAP_PCI_BUS:
 307    case PIPE_CAP_PCI_DEVICE:
 308    case PIPE_CAP_PCI_FUNCTION:
 309    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 310    case PIPE_CAP_TGSI_VOTE:
 311    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 312    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 313    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 314    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 315    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 316    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 317    case PIPE_CAP_INT64:
 318    case PIPE_CAP_INT64_DIVMOD:
 319    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 320    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 321    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 322    case PIPE_CAP_TGSI_BALLOT:
 323    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 324    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 325    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 326    case PIPE_CAP_POST_DEPTH_COVERAGE:
 327    case PIPE_CAP_BINDLESS_TEXTURE:
 328    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 329    case PIPE_CAP_MEMOBJ:
 330    case PIPE_CAP_LOAD_CONSTBUF:
 331    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 332    case PIPE_CAP_TILE_RASTER_ORDER:
 333    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 334    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 335    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 336    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 337    case PIPE_CAP_FENCE_SIGNAL:
 338    case PIPE_CAP_CONSTBUF0_FLAGS:
 339    case PIPE_CAP_PACKED_UNIFORMS:
 340    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 341    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 342    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 343    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 344    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 345    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 346    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 347    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 348       return 0;
 349    case PIPE_CAP_CLIP_HALFZ:
 350       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
 351    case PIPE_CAP_MAX_GS_INVOCATIONS:
 352       return 32;
 353    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 354       return 1 << 27;
 355    case PIPE_CAP_VENDOR_ID:
 356       return 0x1af4;
 357    case PIPE_CAP_DEVICE_ID:
 358       return 0x1010;
 359    case PIPE_CAP_ACCELERATED:
 360       return 1;
 361    case PIPE_CAP_UMA:
 362    case PIPE_CAP_VIDEO_MEMORY:
 363       return 0;
 364    case PIPE_CAP_NATIVE_FENCE_FD:
 365       return vscreen->vws->supports_fences;
 366    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 367       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
 368             (vscreen->caps.caps.v2.host_feature_check_version < 1);
 369    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 370       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 371    default:
 372       return u_pipe_screen_get_param_defaults(screen, param);
 373    }
 374 }
 375
 376 static int
 377 virgl_get_shader_param(struct pipe_screen *screen,
 378                        enum pipe_shader_type shader,
 379                        enum pipe_shader_cap param)
 380 {
 381    struct virgl_screen *vscreen = virgl_screen(screen);
 382
 383    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
 384        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
 385       return 0;
 386
 387    if (shader == PIPE_SHADER_COMPUTE &&
 388        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 389      return 0;
 390
 391    switch(shader)
 392    {
 393    case PIPE_SHADER_FRAGMENT:
 394    case PIPE_SHADER_VERTEX:
 395    case PIPE_SHADER_GEOMETRY:
 396    case PIPE_SHADER_TESS_CTRL:
 397    case PIPE_SHADER_TESS_EVAL:
 398    case PIPE_SHADER_COMPUTE:
 399       switch (param) {
 400       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 401       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 402       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 403       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 404          return INT_MAX;
 405       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 406       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 407       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 408          return 1;
 409       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 410       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 411          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
 412       case PIPE_SHADER_CAP_MAX_INPUTS:
 413          if (vscreen->caps.caps.v1.glsl_level < 150)
 414             return vscreen->caps.caps.v2.max_vertex_attribs;
 415          return (shader == PIPE_SHADER_VERTEX ||
 416                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
 417       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 418          if (shader == PIPE_SHADER_FRAGMENT)
 419             return vscreen->caps.caps.v1.max_render_targets;
 420          return vscreen->caps.caps.v2.max_vertex_outputs;
 421      // case PIPE_SHADER_CAP_MAX_CONSTS:
 422      //    return 4096;
 423       case PIPE_SHADER_CAP_MAX_TEMPS:
 424          return 256;
 425       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 426          return vscreen->caps.caps.v1.max_uniform_blocks;
 427     //  case PIPE_SHADER_CAP_MAX_ADDRS:
 428      //    return 1;
 429       case PIPE_SHADER_CAP_SUBROUTINES:
 430          return 1;
 431       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 432             return 16;
 433       case PIPE_SHADER_CAP_INTEGERS:
 434          return vscreen->caps.caps.v1.glsl_level >= 130;
 435       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 436          return 32;
 437       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 438          return 4096 * sizeof(float[4]);
 439       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 440          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 441             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
 442          else
 443             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
 444       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 445          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 446             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
 447          else
 448             return vscreen->caps.caps.v2.max_shader_image_other_stages;
 449       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 450          return (1 << PIPE_SHADER_IR_TGSI);
 451       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 452          return vscreen->caps.caps.v2.max_atomic_counters[shader];
 453       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 454          return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
 455       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 456       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 457       case PIPE_SHADER_CAP_INT64_ATOMICS:
 458       case PIPE_SHADER_CAP_FP16:
 459          return 0;
 460       case PIPE_SHADER_CAP_SCALAR_ISA:
 461          return 1;
 462       default:
 463          return 0;
 464       }
 465    default:
 466       return 0;
 467    }
 468 }
 469
 470 static float
 471 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 472 {
 473    struct virgl_screen *vscreen = virgl_screen(screen);
 474    switch (param) {
 475    case PIPE_CAPF_MAX_LINE_WIDTH:
 476       return vscreen->caps.caps.v2.max_aliased_line_width;
 477    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 478       return vscreen->caps.caps.v2.max_smooth_line_width;
 479    case PIPE_CAPF_MAX_POINT_WIDTH:
 480       return vscreen->caps.caps.v2.max_aliased_point_size;
 481    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 482       return vscreen->caps.caps.v2.max_smooth_point_size;
 483    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 484       return 16.0;
 485    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 486       return vscreen->caps.caps.v2.max_texture_lod_bias;
 487    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 488    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 489    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 490       return 0.0f;
 491    }
 492    /* should only get here on unhandled cases */
 493    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 494    return 0.0;
 495 }
 496
 497 static int
 498 virgl_get_compute_param(struct pipe_screen *screen,
 499                         enum pipe_shader_ir ir_type,
 500                         enum pipe_compute_cap param,
 501                         void *ret)
 502 {
 503    struct virgl_screen *vscreen = virgl_screen(screen);
 504    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
 505       return 0;
 506    switch (param) {
 507    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 508       if (ret) {
 509          uint64_t *grid_size = ret;
 510          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
 511          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
 512          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
 513       }
 514       return 3 * sizeof(uint64_t) ;
 515    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 516       if (ret) {
 517          uint64_t *block_size = ret;
 518          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
 519          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
 520          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
 521       }
 522       return 3 * sizeof(uint64_t);
 523    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 524       if (ret) {
 525          uint64_t *max_threads_per_block = ret;
 526          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
 527       }
 528       return sizeof(uint64_t);
 529    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 530       if (ret) {
 531          uint64_t *max_local_size = ret;
 532          /* Value reported by the closed source driver. */
 533          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
 534       }
 535       return sizeof(uint64_t);
 536    default:
 537       break;
 538    }
 539    return 0;
 540 }
 541
 542 static boolean
 543 has_format_bit(struct virgl_supported_format_mask *mask,
 544                enum virgl_formats fmt)
 545 {
 546    assert(fmt < VIRGL_FORMAT_MAX);
 547    unsigned val = (unsigned)fmt;
 548    unsigned idx = val / 32;
 549    unsigned bit = val % 32;
 550    assert(idx < ARRAY_SIZE(mask->bitmask));
 551    return (mask->bitmask[val / 32] & (1u << bit)) != 0;
 552 }
 553
 554 boolean
 555 virgl_has_readback_format(struct pipe_screen *screen,
 556                           enum virgl_formats fmt)
 557 {
 558    struct virgl_screen *vscreen = virgl_screen(screen);
 559    return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
 560                          fmt);
 561 }
 562
 563 static boolean
 564 virgl_is_vertex_format_supported(struct pipe_screen *screen,
 565                                  enum pipe_format format)
 566 {
 567    struct virgl_screen *vscreen = virgl_screen(screen);
 568    const struct util_format_description *format_desc;
 569    int i;
 570
 571    format_desc = util_format_description(format);
 572    if (!format_desc)
 573       return FALSE;
 574
 575    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 576       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
 577       int big = vformat / 32;
 578       int small = vformat % 32;
 579       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
 580          return FALSE;
 581       return TRUE;
 582    }
 583
 584    /* Find the first non-VOID channel. */
 585    for (i = 0; i < 4; i++) {
 586       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 587          break;
 588       }
 589    }
 590
 591    if (i == 4)
 592       return FALSE;
 593
 594    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
 595       return FALSE;
 596
 597    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
 598       return FALSE;
 599    return TRUE;
 600 }
 601
 602 static boolean
 603 virgl_format_check_bitmask(enum pipe_format format,
 604                            uint32_t bitmask[16],
 605                            boolean may_emulate_bgra)
 606 {
 607    int big = format / 32;
 608    int small = format % 32;
 609    if ((bitmask[big] & (1 << small)))
 610       return TRUE;
 611
 612    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
 613     * emulate it by using a swizzled RGBx */
 614    if (may_emulate_bgra) {
 615       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
 616          format = PIPE_FORMAT_R8G8B8A8_SRGB;
 617       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
 618          format = PIPE_FORMAT_R8G8B8X8_SRGB;
 619       else {
 620          return FALSE;
 621       }
 622
 623       big = format / 32;
 624       small = format % 32;
 625       if (bitmask[big] & (1 << small))
 626          return TRUE;
 627    }
 628    return FALSE;
 629 }
 630
 631 /**
 632  * Query format support for creating a texture, drawing surface, etc.
 633  * \param format  the format to test
 634  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 635  */
 636 static boolean
 637 virgl_is_format_supported( struct pipe_screen *screen,
 638                                  enum pipe_format format,
 639                                  enum pipe_texture_target target,
 640                                  unsigned sample_count,
 641                                  unsigned storage_sample_count,
 642                                  unsigned bind)
 643 {
 644    struct virgl_screen *vscreen = virgl_screen(screen);
 645    const struct util_format_description *format_desc;
 646    int i;
 647
 648    boolean may_emulate_bgra = false;
 649
 650    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 651       return false;
 652
 653    assert(target == PIPE_BUFFER ||
 654           target == PIPE_TEXTURE_1D ||
 655           target == PIPE_TEXTURE_1D_ARRAY ||
 656           target == PIPE_TEXTURE_2D ||
 657           target == PIPE_TEXTURE_2D_ARRAY ||
 658           target == PIPE_TEXTURE_RECT ||
 659           target == PIPE_TEXTURE_3D ||
 660           target == PIPE_TEXTURE_CUBE ||
 661           target == PIPE_TEXTURE_CUBE_ARRAY);
 662
 663    format_desc = util_format_description(format);
 664    if (!format_desc)
 665       return FALSE;
 666
 667    if (util_format_is_intensity(format))
 668       return FALSE;
 669
 670    if (sample_count > 1) {
 671       if (!vscreen->caps.caps.v1.bset.texture_multisample)
 672          return FALSE;
 673
 674       if (bind & PIPE_BIND_SHADER_IMAGE) {
 675          if (sample_count > vscreen->caps.caps.v2.max_image_samples)
 676             return FALSE;
 677       }
 678
 679       if (sample_count > vscreen->caps.caps.v1.max_samples)
 680          return FALSE;
 681    }
 682
 683    if (bind & PIPE_BIND_VERTEX_BUFFER) {
 684       return virgl_is_vertex_format_supported(screen, format);
 685    }
 686
 687    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
 688       return FALSE;
 689
 690    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
 691    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
 692        format == PIPE_FORMAT_R32G32B32_SINT ||
 693        format == PIPE_FORMAT_R32G32B32_UINT) &&
 694        target != PIPE_BUFFER)
 695       return FALSE;
 696
 697    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
 698         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
 699         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
 700        target == PIPE_TEXTURE_3D)
 701       return FALSE;
 702
 703    may_emulate_bgra = (vscreen->caps.caps.v2.capability_bits &
 704                        VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 705                       vscreen->tweak_gles_emulate_bgra;
 706
 707    if (bind & PIPE_BIND_RENDER_TARGET) {
 708       /* For ARB_framebuffer_no_attachments. */
 709       if (format == PIPE_FORMAT_NONE)
 710          return TRUE;
 711
 712       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 713          return FALSE;
 714
 715       /*
 716        * Although possible, it is unnatural to render into compressed or YUV
 717        * surfaces. So disable these here to avoid going into weird paths
 718        * inside the state trackers.
 719        */
 720       if (format_desc->block.width != 1 ||
 721           format_desc->block.height != 1)
 722          return FALSE;
 723
 724       if (!virgl_format_check_bitmask(format,
 725                                       vscreen->caps.caps.v1.render.bitmask,
 726                                       may_emulate_bgra))
 727          return FALSE;
 728    }
 729
 730    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 731       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 732          return FALSE;
 733    }
 734
 735    /*
 736     * All other operations (sampling, transfer, etc).
 737     */
 738
 739    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 740       goto out_lookup;
 741    }
 742    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 743       goto out_lookup;
 744    }
 745    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
 746       goto out_lookup;
 747    }
 748
 749    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 750       goto out_lookup;
 751    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 752       goto out_lookup;
 753    }
 754
 755    /* Find the first non-VOID channel. */
 756    for (i = 0; i < 4; i++) {
 757       if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 758          break;
 759       }
 760    }
 761
 762    if (i == 4)
 763       return FALSE;
 764
 765    /* no L4A4 */
 766    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
 767       return FALSE;
 768
 769  out_lookup:
 770    return virgl_format_check_bitmask(format,
 771                                      vscreen->caps.caps.v1.sampler.bitmask,
 772                                      may_emulate_bgra);
 773 }
 774
 775 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
 776                                       struct pipe_resource *res,
 777                                       unsigned level, unsigned layer,
 778                                     void *winsys_drawable_handle, struct pipe_box *sub_box)
 779 {
 780    struct virgl_screen *vscreen = virgl_screen(screen);
 781    struct virgl_winsys *vws = vscreen->vws;
 782    struct virgl_resource *vres = virgl_resource(res);
 783
 784    if (vws->flush_frontbuffer)
 785       vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
 786                              sub_box);
 787 }
 788
 789 static void virgl_fence_reference(struct pipe_screen *screen,
 790                                   struct pipe_fence_handle **ptr,
 791                                   struct pipe_fence_handle *fence)
 792 {
 793    struct virgl_screen *vscreen = virgl_screen(screen);
 794    struct virgl_winsys *vws = vscreen->vws;
 795
 796    vws->fence_reference(vws, ptr, fence);
 797 }
 798
 799 static boolean virgl_fence_finish(struct pipe_screen *screen,
 800                                   struct pipe_context *ctx,
 801                                   struct pipe_fence_handle *fence,
 802                                   uint64_t timeout)
 803 {
 804    struct virgl_screen *vscreen = virgl_screen(screen);
 805    struct virgl_winsys *vws = vscreen->vws;
 806
 807    return vws->fence_wait(vws, fence, timeout);
 808 }
 809
 810 static int virgl_fence_get_fd(struct pipe_screen *screen,
 811             struct pipe_fence_handle *fence)
 812 {
 813    struct virgl_screen *vscreen = virgl_screen(screen);
 814    struct virgl_winsys *vws = vscreen->vws;
 815
 816    return vws->fence_get_fd(vws, fence);
 817 }
 818
 819 static uint64_t
 820 virgl_get_timestamp(struct pipe_screen *_screen)
 821 {
 822    return os_time_get_nano();
 823 }
 824
 825 static void
 826 virgl_destroy_screen(struct pipe_screen *screen)
 827 {
 828    struct virgl_screen *vscreen = virgl_screen(screen);
 829    struct virgl_winsys *vws = vscreen->vws;
 830
 831    slab_destroy_parent(&vscreen->transfer_pool);
 832
 833    if (vws)
 834       vws->destroy(vws);
 835    FREE(vscreen);
 836 }
 837
 838 static void
 839 fixup_readback_format(union virgl_caps *caps)
 840 {
 841    const size_t size = ARRAY_SIZE(caps->v2.supported_readback_formats.bitmask);
 842    for (int i = 0; i < size; ++i) {
 843       if (caps->v2.supported_readback_formats.bitmask[i] != 0)
 844          return; /* we got some formats, we definately have a new protocol */
 845    }
 846
 847    /* old protocol used; fall back to considering all sampleable formats valid
 848     * readback-formats
 849     */
 850    for (int i = 0; i < size; ++i) {
 851       caps->v2.supported_readback_formats.bitmask[i] =
 852          caps->v1.sampler.bitmask[i];
 853    }
 854 }
 855
 856 struct pipe_screen *
 857 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
 858 {
 859    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
 860
 861    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
 862    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
 863    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
 864
 865    if (!screen)
 866       return NULL;
 867
 868    virgl_debug = debug_get_option_virgl_debug();
 869
 870    if (config && config->options) {
 871       screen->tweak_gles_emulate_bgra =
 872             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
 873       screen->tweak_gles_apply_bgra_dest_swizzle =
 874             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
 875       screen->tweak_gles_tf3_value =
 876             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
 877    }
 878
 879    screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
 880    screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
 881
 882    screen->vws = vws;
 883    screen->base.get_name = virgl_get_name;
 884    screen->base.get_vendor = virgl_get_vendor;
 885    screen->base.get_param = virgl_get_param;
 886    screen->base.get_shader_param = virgl_get_shader_param;
 887    screen->base.get_compute_param = virgl_get_compute_param;
 888    screen->base.get_paramf = virgl_get_paramf;
 889    screen->base.is_format_supported = virgl_is_format_supported;
 890    screen->base.destroy = virgl_destroy_screen;
 891    screen->base.context_create = virgl_context_create;
 892    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
 893    screen->base.get_timestamp = virgl_get_timestamp;
 894    screen->base.fence_reference = virgl_fence_reference;
 895    //screen->base.fence_signalled = virgl_fence_signalled;
 896    screen->base.fence_finish = virgl_fence_finish;
 897    screen->base.fence_get_fd = virgl_fence_get_fd;
 898
 899    virgl_init_screen_resource_functions(&screen->base);
 900
 901    vws->get_caps(vws, &screen->caps);
 902    fixup_readback_format(&screen->caps.caps);
 903
 904    screen->refcnt = 1;
 905
 906    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 907
 908    return &screen->base;
 909 }