src/gallium/drivers/zink/zink_context.c

   1 /*
   2  * Copyright 2018 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "zink_context.h"
  25
  26 #include "zink_batch.h"
  27 #include "zink_compiler.h"
  28 #include "zink_fence.h"
  29 #include "zink_framebuffer.h"
  30 #include "zink_pipeline.h"
  31 #include "zink_program.h"
  32 #include "zink_render_pass.h"
  33 #include "zink_resource.h"
  34 #include "zink_screen.h"
  35 #include "zink_state.h"
  36 #include "zink_surface.h"
  37
  38 #include "indices/u_primconvert.h"
  39 #include "util/u_blitter.h"
  40 #include "util/u_debug.h"
  41 #include "util/u_format.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45
  46 #include "nir.h"
  47
  48 #include "util/u_memory.h"
  49 #include "util/u_prim.h"
  50 #include "util/u_upload_mgr.h"
  51
  52 static void
  53 zink_context_destroy(struct pipe_context *pctx)
  54 {
  55    struct zink_context *ctx = zink_context(pctx);
  56    struct zink_screen *screen = zink_screen(pctx->screen);
  57
  58    if (vkQueueWaitIdle(ctx->queue) != VK_SUCCESS)
  59       debug_printf("vkQueueWaitIdle failed\n");
  60
  61    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i)
  62       vkFreeCommandBuffers(screen->dev, ctx->cmdpool, 1, &ctx->batches[i].cmdbuf);
  63    vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
  64
  65    util_primconvert_destroy(ctx->primconvert);
  66    u_upload_destroy(pctx->stream_uploader);
  67    slab_destroy_child(&ctx->transfer_pool);
  68    util_blitter_destroy(ctx->blitter);
  69    FREE(ctx);
  70 }
  71
  72 static VkFilter
  73 filter(enum pipe_tex_filter filter)
  74 {
  75    switch (filter) {
  76    case PIPE_TEX_FILTER_NEAREST: return VK_FILTER_NEAREST;
  77    case PIPE_TEX_FILTER_LINEAR: return VK_FILTER_LINEAR;
  78    }
  79    unreachable("unexpected filter");
  80 }
  81
  82 static VkSamplerMipmapMode
  83 sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
  84 {
  85    switch (filter) {
  86    case PIPE_TEX_MIPFILTER_NEAREST: return VK_SAMPLER_MIPMAP_MODE_NEAREST;
  87    case PIPE_TEX_MIPFILTER_LINEAR: return VK_SAMPLER_MIPMAP_MODE_LINEAR;
  88    case PIPE_TEX_MIPFILTER_NONE:
  89       unreachable("PIPE_TEX_MIPFILTER_NONE should be dealt with earlier");
  90    }
  91    unreachable("unexpected filter");
  92 }
  93
  94 static VkSamplerAddressMode
  95 sampler_address_mode(enum pipe_tex_wrap filter)
  96 {
  97    switch (filter) {
  98    case PIPE_TEX_WRAP_REPEAT: return VK_SAMPLER_ADDRESS_MODE_REPEAT;
  99    case PIPE_TEX_WRAP_CLAMP: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 100    case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE;
 101    case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
 102    case PIPE_TEX_WRAP_MIRROR_REPEAT: return VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT;
 103    case PIPE_TEX_WRAP_MIRROR_CLAMP: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 104    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE;
 105    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE; /* not technically correct, but kinda works */
 106    }
 107    unreachable("unexpected wrap");
 108 }
 109
 110 static VkCompareOp
 111 compare_op(enum pipe_compare_func op)
 112 {
 113    switch (op) {
 114       case PIPE_FUNC_NEVER: return VK_COMPARE_OP_NEVER;
 115       case PIPE_FUNC_LESS: return VK_COMPARE_OP_LESS;
 116       case PIPE_FUNC_EQUAL: return VK_COMPARE_OP_EQUAL;
 117       case PIPE_FUNC_LEQUAL: return VK_COMPARE_OP_LESS_OR_EQUAL;
 118       case PIPE_FUNC_GREATER: return VK_COMPARE_OP_GREATER;
 119       case PIPE_FUNC_NOTEQUAL: return VK_COMPARE_OP_NOT_EQUAL;
 120       case PIPE_FUNC_GEQUAL: return VK_COMPARE_OP_GREATER_OR_EQUAL;
 121       case PIPE_FUNC_ALWAYS: return VK_COMPARE_OP_ALWAYS;
 122    }
 123    unreachable("unexpected compare");
 124 }
 125
 126 static void *
 127 zink_create_sampler_state(struct pipe_context *pctx,
 128                           const struct pipe_sampler_state *state)
 129 {
 130    struct zink_screen *screen = zink_screen(pctx->screen);
 131
 132    VkSamplerCreateInfo sci = {};
 133    sci.sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO;
 134    sci.magFilter = filter(state->mag_img_filter);
 135    sci.minFilter = filter(state->min_img_filter);
 136
 137    if (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 138       sci.mipmapMode = sampler_mipmap_mode(state->min_mip_filter);
 139       sci.minLod = state->min_lod;
 140       sci.maxLod = state->max_lod;
 141    } else {
 142       sci.mipmapMode = VK_SAMPLER_MIPMAP_MODE_NEAREST;
 143       sci.minLod = 0;
 144       sci.maxLod = 0;
 145    }
 146
 147    sci.addressModeU = sampler_address_mode(state->wrap_s);
 148    sci.addressModeV = sampler_address_mode(state->wrap_t);
 149    sci.addressModeW = sampler_address_mode(state->wrap_r);
 150    sci.mipLodBias = state->lod_bias;
 151
 152    if (state->compare_mode == PIPE_TEX_COMPARE_NONE)
 153       sci.compareOp = VK_COMPARE_OP_NEVER;
 154    else
 155       sci.compareOp = compare_op(state->compare_func);
 156
 157    sci.borderColor = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK; // TODO
 158    sci.unnormalizedCoordinates = !state->normalized_coords;
 159
 160    if (state->max_anisotropy > 1) {
 161       sci.maxAnisotropy = state->max_anisotropy;
 162       sci.anisotropyEnable = VK_TRUE;
 163    }
 164
 165    VkSampler *sampler = CALLOC(1, sizeof(VkSampler));
 166    if (!sampler)
 167       return NULL;
 168
 169    if (vkCreateSampler(screen->dev, &sci, NULL, sampler) != VK_SUCCESS) {
 170       FREE(sampler);
 171       return NULL;
 172    }
 173
 174    return sampler;
 175 }
 176
 177 static void
 178 zink_bind_sampler_states(struct pipe_context *pctx,
 179                          enum pipe_shader_type shader,
 180                          unsigned start_slot,
 181                          unsigned num_samplers,
 182                          void **samplers)
 183 {
 184    struct zink_context *ctx = zink_context(pctx);
 185    for (unsigned i = 0; i < num_samplers; ++i) {
 186       VkSampler *sampler = samplers[i];
 187       ctx->samplers[shader][start_slot + i] = sampler ? *sampler : VK_NULL_HANDLE;
 188    }
 189    ctx->num_samplers[shader] = start_slot + num_samplers;
 190 }
 191
 192 static void
 193 zink_delete_sampler_state(struct pipe_context *pctx,
 194                           void *sampler_state)
 195 {
 196    struct zink_batch *batch = zink_curr_batch(zink_context(pctx));
 197    util_dynarray_append(&batch->zombie_samplers, VkSampler,
 198                         *(VkSampler *)sampler_state);
 199    FREE(sampler_state);
 200 }
 201
 202
 203 static VkImageViewType
 204 image_view_type(enum pipe_texture_target target)
 205 {
 206    switch (target) {
 207    case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
 208    case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
 209    case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
 210    case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
 211    case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
 212    case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
 213    case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
 214    case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D; /* not sure */
 215    default:
 216       unreachable("unexpected target");
 217    }
 218 }
 219
 220 static VkComponentSwizzle
 221 component_mapping(enum pipe_swizzle swizzle)
 222 {
 223    switch (swizzle) {
 224    case PIPE_SWIZZLE_X: return VK_COMPONENT_SWIZZLE_R;
 225    case PIPE_SWIZZLE_Y: return VK_COMPONENT_SWIZZLE_G;
 226    case PIPE_SWIZZLE_Z: return VK_COMPONENT_SWIZZLE_B;
 227    case PIPE_SWIZZLE_W: return VK_COMPONENT_SWIZZLE_A;
 228    case PIPE_SWIZZLE_0: return VK_COMPONENT_SWIZZLE_ZERO;
 229    case PIPE_SWIZZLE_1: return VK_COMPONENT_SWIZZLE_ONE;
 230    case PIPE_SWIZZLE_NONE: return VK_COMPONENT_SWIZZLE_IDENTITY; // ???
 231    default:
 232       unreachable("unexpected swizzle");
 233    }
 234 }
 235
 236 static VkImageAspectFlags
 237 sampler_aspect_from_format(enum pipe_format fmt)
 238 {
 239    if (util_format_is_depth_or_stencil(fmt)) {
 240       const struct util_format_description *desc = util_format_description(fmt);
 241       if (util_format_has_depth(desc))
 242          return VK_IMAGE_ASPECT_DEPTH_BIT;
 243       assert(util_format_has_stencil(desc));
 244       return VK_IMAGE_ASPECT_STENCIL_BIT;
 245    } else
 246      return VK_IMAGE_ASPECT_COLOR_BIT;
 247 }
 248
 249 static struct pipe_sampler_view *
 250 zink_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *pres,
 251                          const struct pipe_sampler_view *state)
 252 {
 253    struct zink_screen *screen = zink_screen(pctx->screen);
 254    struct zink_resource *res = zink_resource(pres);
 255    struct zink_sampler_view *sampler_view = CALLOC_STRUCT(zink_sampler_view);
 256
 257    sampler_view->base = *state;
 258    sampler_view->base.texture = NULL;
 259    pipe_resource_reference(&sampler_view->base.texture, pres);
 260    sampler_view->base.reference.count = 1;
 261    sampler_view->base.context = pctx;
 262
 263    VkImageViewCreateInfo ivci = {};
 264    ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
 265    ivci.image = res->image;
 266    ivci.viewType = image_view_type(state->target);
 267    ivci.format = zink_get_format(screen, state->format);
 268    ivci.components.r = component_mapping(state->swizzle_r);
 269    ivci.components.g = component_mapping(state->swizzle_g);
 270    ivci.components.b = component_mapping(state->swizzle_b);
 271    ivci.components.a = component_mapping(state->swizzle_a);
 272
 273    ivci.subresourceRange.aspectMask = sampler_aspect_from_format(state->format);
 274    ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
 275    ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
 276    ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
 277    ivci.subresourceRange.layerCount = state->u.tex.last_layer - state->u.tex.first_layer + 1;
 278
 279    VkResult err = vkCreateImageView(screen->dev, &ivci, NULL, &sampler_view->image_view);
 280    if (err != VK_SUCCESS) {
 281       FREE(sampler_view);
 282       return NULL;
 283    }
 284
 285    return &sampler_view->base;
 286 }
 287
 288 static void
 289 zink_sampler_view_destroy(struct pipe_context *pctx,
 290                           struct pipe_sampler_view *pview)
 291 {
 292    struct zink_sampler_view *view = zink_sampler_view(pview);
 293    vkDestroyImageView(zink_screen(pctx->screen)->dev, view->image_view, NULL);
 294    FREE(view);
 295 }
 296
 297 static void *
 298 zink_create_vs_state(struct pipe_context *pctx,
 299                      const struct pipe_shader_state *shader)
 300 {
 301    struct nir_shader *nir;
 302    if (shader->type != PIPE_SHADER_IR_NIR)
 303       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 304    else
 305       nir = (struct nir_shader *)shader->ir.nir;
 306
 307    return zink_compile_nir(zink_screen(pctx->screen), nir);
 308 }
 309
 310 static void
 311 bind_stage(struct zink_context *ctx, enum pipe_shader_type stage,
 312            struct zink_shader *shader)
 313 {
 314    assert(stage < PIPE_SHADER_COMPUTE);
 315    ctx->gfx_stages[stage] = shader;
 316    ctx->dirty_program = true;
 317 }
 318
 319 static void
 320 zink_bind_vs_state(struct pipe_context *pctx,
 321                    void *cso)
 322 {
 323    bind_stage(zink_context(pctx), PIPE_SHADER_VERTEX, cso);
 324 }
 325
 326 static void
 327 zink_delete_vs_state(struct pipe_context *pctx,
 328                      void *cso)
 329 {
 330    zink_shader_free(zink_screen(pctx->screen), cso);
 331 }
 332
 333 static void *
 334 zink_create_fs_state(struct pipe_context *pctx,
 335                      const struct pipe_shader_state *shader)
 336 {
 337    struct nir_shader *nir;
 338    if (shader->type != PIPE_SHADER_IR_NIR)
 339       nir = zink_tgsi_to_nir(pctx->screen, shader->tokens);
 340    else
 341       nir = (struct nir_shader *)shader->ir.nir;
 342
 343    return zink_compile_nir(zink_screen(pctx->screen), nir);
 344 }
 345
 346 static void
 347 zink_bind_fs_state(struct pipe_context *pctx,
 348                    void *cso)
 349 {
 350    bind_stage(zink_context(pctx), PIPE_SHADER_FRAGMENT, cso);
 351 }
 352
 353 static void
 354 zink_delete_fs_state(struct pipe_context *pctx,
 355                      void *cso)
 356 {
 357    zink_shader_free(zink_screen(pctx->screen), cso);
 358 }
 359
 360 static void
 361 zink_set_polygon_stipple(struct pipe_context *pctx,
 362                          const struct pipe_poly_stipple *ps)
 363 {
 364 }
 365
 366 static void
 367 zink_set_vertex_buffers(struct pipe_context *pctx,
 368                         unsigned start_slot,
 369                         unsigned num_buffers,
 370                         const struct pipe_vertex_buffer *buffers)
 371 {
 372    struct zink_context *ctx = zink_context(pctx);
 373
 374    if (buffers) {
 375       for (int i = 0; i < num_buffers; ++i) {
 376          const struct pipe_vertex_buffer *vb = buffers + i;
 377          ctx->gfx_pipeline_state.bindings[start_slot + i].stride = vb->stride;
 378       }
 379    }
 380
 381    util_set_vertex_buffers_mask(ctx->buffers, &ctx->buffers_enabled_mask,
 382                                 buffers, start_slot, num_buffers);
 383 }
 384
 385 static void
 386 zink_set_viewport_states(struct pipe_context *pctx,
 387                          unsigned start_slot,
 388                          unsigned num_viewports,
 389                          const struct pipe_viewport_state *state)
 390 {
 391    struct zink_context *ctx = zink_context(pctx);
 392
 393    for (unsigned i = 0; i < num_viewports; ++i) {
 394       VkViewport viewport = {
 395          state[i].translate[0] - state[i].scale[0],
 396          state[i].translate[1] - state[i].scale[1],
 397          state[i].scale[0] * 2,
 398          state[i].scale[1] * 2,
 399          state[i].translate[2] - state[i].scale[2],
 400          state[i].translate[2] + state[i].scale[2]
 401       };
 402       ctx->viewport_states[start_slot + i] = state[i];
 403       ctx->viewports[start_slot + i] = viewport;
 404    }
 405    ctx->num_viewports = start_slot + num_viewports;
 406 }
 407
 408 static void
 409 zink_set_scissor_states(struct pipe_context *pctx,
 410                         unsigned start_slot, unsigned num_scissors,
 411                         const struct pipe_scissor_state *states)
 412 {
 413    struct zink_context *ctx = zink_context(pctx);
 414
 415    for (unsigned i = 0; i < num_scissors; i++) {
 416       VkRect2D scissor;
 417
 418       scissor.offset.x = states[i].minx;
 419       scissor.offset.y = states[i].miny;
 420       scissor.extent.width = states[i].maxx - states[i].minx;
 421       scissor.extent.height = states[i].maxy - states[i].miny;
 422       ctx->scissor_states[start_slot + i] = states[i];
 423       ctx->scissors[start_slot + i] = scissor;
 424    }
 425 }
 426
 427 static void
 428 zink_set_constant_buffer(struct pipe_context *pctx,
 429                          enum pipe_shader_type shader, uint index,
 430                          const struct pipe_constant_buffer *cb)
 431 {
 432    struct zink_context *ctx = zink_context(pctx);
 433
 434    if (cb) {
 435       struct pipe_resource *buffer = cb->buffer;
 436       unsigned offset = cb->buffer_offset;
 437       if (cb->user_buffer) {
 438          struct zink_screen *screen = zink_screen(pctx->screen);
 439          u_upload_data(ctx->base.const_uploader, 0, cb->buffer_size,
 440                        screen->props.limits.minUniformBufferOffsetAlignment,
 441                        cb->user_buffer, &offset, &buffer);
 442       }
 443
 444       pipe_resource_reference(&ctx->ubos[shader][index].buffer, buffer);
 445       ctx->ubos[shader][index].buffer_offset = offset;
 446       ctx->ubos[shader][index].buffer_size = cb->buffer_size;
 447       ctx->ubos[shader][index].user_buffer = NULL;
 448
 449       if (cb->user_buffer)
 450          pipe_resource_reference(&buffer, NULL);
 451    } else {
 452       pipe_resource_reference(&ctx->ubos[shader][index].buffer, NULL);
 453       ctx->ubos[shader][index].buffer_offset = 0;
 454       ctx->ubos[shader][index].buffer_size = 0;
 455       ctx->ubos[shader][index].user_buffer = NULL;
 456    }
 457 }
 458
 459 static void
 460 zink_set_sampler_views(struct pipe_context *pctx,
 461                        enum pipe_shader_type shader_type,
 462                        unsigned start_slot,
 463                        unsigned num_views,
 464                        struct pipe_sampler_view **views)
 465 {
 466    struct zink_context *ctx = zink_context(pctx);
 467    assert(views);
 468    for (unsigned i = 0; i < num_views; ++i) {
 469       pipe_sampler_view_reference(
 470          &ctx->image_views[shader_type][start_slot + i],
 471          views[i]);
 472    }
 473    ctx->num_image_views[shader_type] = start_slot + num_views;
 474 }
 475
 476 static void
 477 zink_set_stencil_ref(struct pipe_context *pctx,
 478                      const struct pipe_stencil_ref *ref)
 479 {
 480    struct zink_context *ctx = zink_context(pctx);
 481    ctx->stencil_ref = *ref;
 482 }
 483
 484 static void
 485 zink_set_clip_state(struct pipe_context *pctx,
 486                     const struct pipe_clip_state *pcs)
 487 {
 488 }
 489
 490 static struct zink_render_pass *
 491 get_render_pass(struct zink_context *ctx)
 492 {
 493    struct zink_screen *screen = zink_screen(ctx->base.screen);
 494    const struct pipe_framebuffer_state *fb = &ctx->fb_state;
 495    struct zink_render_pass_state state;
 496
 497    for (int i = 0; i < fb->nr_cbufs; i++) {
 498       struct zink_resource *cbuf = zink_resource(fb->cbufs[i]->texture);
 499       state.rts[i].format = cbuf->format;
 500       state.rts[i].samples = cbuf->base.nr_samples > 0 ? cbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 501    }
 502    state.num_cbufs = fb->nr_cbufs;
 503
 504    if (fb->zsbuf) {
 505       struct zink_resource *zsbuf = zink_resource(fb->zsbuf->texture);
 506       state.rts[fb->nr_cbufs].format = zsbuf->format;
 507       state.rts[fb->nr_cbufs].samples = zsbuf->base.nr_samples > 0 ? zsbuf->base.nr_samples : VK_SAMPLE_COUNT_1_BIT;
 508    }
 509    state.have_zsbuf = fb->zsbuf != NULL;
 510
 511    struct hash_entry *entry = _mesa_hash_table_search(ctx->render_pass_cache,
 512                                                       &state);
 513    if (!entry) {
 514       struct zink_render_pass *rp;
 515       rp = zink_create_render_pass(screen, &state);
 516       entry = _mesa_hash_table_insert(ctx->render_pass_cache, &state, rp);
 517       if (!entry)
 518          return NULL;
 519    }
 520
 521    return entry->data;
 522 }
 523
 524 static struct zink_framebuffer *
 525 get_framebuffer(struct zink_context *ctx)
 526 {
 527    struct zink_screen *screen = zink_screen(ctx->base.screen);
 528
 529    struct zink_framebuffer_state state = {};
 530    state.rp = get_render_pass(ctx);
 531    for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
 532       struct pipe_surface *psurf = ctx->fb_state.cbufs[i];
 533       state.attachments[i] = zink_surface(psurf);
 534    }
 535
 536    state.num_attachments = ctx->fb_state.nr_cbufs;
 537    if (ctx->fb_state.zsbuf) {
 538       struct pipe_surface *psurf = ctx->fb_state.zsbuf;
 539       state.attachments[state.num_attachments++] = zink_surface(psurf);
 540    }
 541
 542    state.width = ctx->fb_state.width;
 543    state.height = ctx->fb_state.height;
 544    state.layers = MAX2(ctx->fb_state.layers, 1);
 545
 546    struct hash_entry *entry = _mesa_hash_table_search(ctx->framebuffer_cache,
 547                                                       &state);
 548    if (!entry) {
 549       struct zink_framebuffer *fb = zink_create_framebuffer(screen, &state);
 550       entry = _mesa_hash_table_insert(ctx->framebuffer_cache, &state, fb);
 551       if (!entry)
 552          return NULL;
 553    }
 554
 555    return entry->data;
 556 }
 557
 558 void
 559 zink_begin_render_pass(struct zink_context *ctx, struct zink_batch *batch)
 560 {
 561    struct zink_screen *screen = zink_screen(ctx->base.screen);
 562    assert(batch == zink_curr_batch(ctx));
 563    assert(ctx->gfx_pipeline_state.render_pass);
 564
 565    struct pipe_framebuffer_state *fb_state = &ctx->fb_state;
 566
 567    VkRenderPassBeginInfo rpbi = {};
 568    rpbi.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO;
 569    rpbi.renderPass = ctx->gfx_pipeline_state.render_pass->render_pass;
 570    rpbi.renderArea.offset.x = 0;
 571    rpbi.renderArea.offset.y = 0;
 572    rpbi.renderArea.extent.width = fb_state->width;
 573    rpbi.renderArea.extent.height = fb_state->height;
 574    rpbi.clearValueCount = 0;
 575    rpbi.pClearValues = NULL;
 576    rpbi.framebuffer = ctx->framebuffer->fb;
 577
 578    assert(ctx->gfx_pipeline_state.render_pass && ctx->framebuffer);
 579    assert(!batch->rp || batch->rp == ctx->gfx_pipeline_state.render_pass);
 580    assert(!batch->fb || batch->fb == ctx->framebuffer);
 581
 582    for (int i = 0; i < fb_state->nr_cbufs; i++) {
 583       struct zink_resource *res = zink_resource(fb_state->cbufs[i]->texture);
 584       if (res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
 585          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 586                                VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
 587    }
 588
 589    if (fb_state->zsbuf) {
 590       struct zink_resource *res = zink_resource(fb_state->zsbuf->texture);
 591       if (res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
 592          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 593                                VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL);
 594    }
 595
 596    zink_render_pass_reference(screen, &batch->rp, ctx->gfx_pipeline_state.render_pass);
 597    zink_framebuffer_reference(screen, &batch->fb, ctx->framebuffer);
 598
 599    vkCmdBeginRenderPass(batch->cmdbuf, &rpbi, VK_SUBPASS_CONTENTS_INLINE);
 600 }
 601
 602 static void
 603 flush_batch(struct zink_context *ctx)
 604 {
 605    struct zink_batch *batch = zink_curr_batch(ctx);
 606    if (batch->rp)
 607       vkCmdEndRenderPass(batch->cmdbuf);
 608
 609    zink_end_batch(ctx, batch);
 610
 611    ctx->curr_batch++;
 612    if (ctx->curr_batch == ARRAY_SIZE(ctx->batches))
 613       ctx->curr_batch = 0;
 614
 615    zink_start_batch(ctx, zink_curr_batch(ctx));
 616 }
 617
 618 struct zink_batch *
 619 zink_batch_rp(struct zink_context *ctx)
 620 {
 621    struct zink_batch *batch = zink_curr_batch(ctx);
 622    if (!batch->rp) {
 623       zink_begin_render_pass(ctx, batch);
 624       assert(batch->rp);
 625    }
 626    return batch;
 627 }
 628
 629 struct zink_batch *
 630 zink_batch_no_rp(struct zink_context *ctx)
 631 {
 632    struct zink_batch *batch = zink_curr_batch(ctx);
 633    if (batch->rp) {
 634       /* flush batch and get a new one */
 635       flush_batch(ctx);
 636       batch = zink_curr_batch(ctx);
 637       assert(!batch->rp);
 638    }
 639    return batch;
 640 }
 641
 642 static void
 643 zink_set_framebuffer_state(struct pipe_context *pctx,
 644                            const struct pipe_framebuffer_state *state)
 645 {
 646    struct zink_context *ctx = zink_context(pctx);
 647    struct zink_screen *screen = zink_screen(pctx->screen);
 648
 649    VkSampleCountFlagBits rast_samples = VK_SAMPLE_COUNT_1_BIT;
 650    for (int i = 0; i < state->nr_cbufs; i++)
 651       rast_samples = MAX2(rast_samples, state->cbufs[i]->texture->nr_samples);
 652    if (state->zsbuf && state->zsbuf->texture->nr_samples)
 653       rast_samples = MAX2(rast_samples, state->zsbuf->texture->nr_samples);
 654
 655    util_copy_framebuffer_state(&ctx->fb_state, state);
 656
 657    struct zink_framebuffer *fb = get_framebuffer(ctx);
 658    zink_framebuffer_reference(screen, &ctx->framebuffer, fb);
 659    zink_render_pass_reference(screen, &ctx->gfx_pipeline_state.render_pass, fb->rp);
 660
 661    ctx->gfx_pipeline_state.rast_samples = rast_samples;
 662    ctx->gfx_pipeline_state.num_attachments = state->nr_cbufs;
 663
 664    struct zink_batch *batch = zink_batch_no_rp(ctx);
 665
 666    for (int i = 0; i < state->nr_cbufs; i++) {
 667       struct zink_resource *res = zink_resource(state->cbufs[i]->texture);
 668       if (res->layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL)
 669          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 670                                VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
 671    }
 672
 673    if (state->zsbuf) {
 674       struct zink_resource *res = zink_resource(state->zsbuf->texture);
 675       if (res->layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL)
 676          zink_resource_barrier(batch->cmdbuf, res, res->aspect,
 677                                VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL);
 678    }
 679 }
 680
 681 static void
 682 zink_set_blend_color(struct pipe_context *pctx,
 683                      const struct pipe_blend_color *color)
 684 {
 685    struct zink_context *ctx = zink_context(pctx);
 686    memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
 687 }
 688
 689 static void
 690 zink_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
 691 {
 692    struct zink_context *ctx = zink_context(pctx);
 693    ctx->gfx_pipeline_state.sample_mask = sample_mask;
 694 }
 695
 696 static VkAccessFlags
 697 access_src_flags(VkImageLayout layout)
 698 {
 699    switch (layout) {
 700    case VK_IMAGE_LAYOUT_UNDEFINED:
 701    case VK_IMAGE_LAYOUT_GENERAL:
 702       return 0;
 703
 704    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 705       return VK_ACCESS_COLOR_ATTACHMENT_READ_BIT;
 706    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 707       return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT;
 708
 709    case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
 710       return VK_ACCESS_SHADER_READ_BIT;
 711
 712    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 713       return VK_ACCESS_TRANSFER_READ_BIT;
 714
 715    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 716       return VK_ACCESS_TRANSFER_WRITE_BIT;
 717
 718    case VK_IMAGE_LAYOUT_PREINITIALIZED:
 719       return VK_ACCESS_HOST_WRITE_BIT;
 720
 721    default:
 722       unreachable("unexpected layout");
 723    }
 724 }
 725
 726 static VkAccessFlags
 727 access_dst_flags(VkImageLayout layout)
 728 {
 729    switch (layout) {
 730    case VK_IMAGE_LAYOUT_UNDEFINED:
 731    case VK_IMAGE_LAYOUT_GENERAL:
 732       return 0;
 733
 734    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 735       return VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
 736    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 737       return VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
 738
 739    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 740       return VK_ACCESS_TRANSFER_READ_BIT;
 741
 742    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 743       return VK_ACCESS_TRANSFER_WRITE_BIT;
 744
 745    default:
 746       unreachable("unexpected layout");
 747    }
 748 }
 749
 750 static VkPipelineStageFlags
 751 pipeline_dst_stage(VkImageLayout layout)
 752 {
 753    switch (layout) {
 754    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 755       return VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
 756    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 757       return VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
 758
 759    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 760       return VK_PIPELINE_STAGE_TRANSFER_BIT;
 761    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 762       return VK_PIPELINE_STAGE_TRANSFER_BIT;
 763
 764    default:
 765       return VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT;
 766    }
 767 }
 768
 769 static VkPipelineStageFlags
 770 pipeline_src_stage(VkImageLayout layout)
 771 {
 772    switch (layout) {
 773    case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
 774       return VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
 775    case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
 776       return VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT;
 777
 778    case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
 779       return VK_PIPELINE_STAGE_TRANSFER_BIT;
 780    case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
 781       return VK_PIPELINE_STAGE_TRANSFER_BIT;
 782
 783    default:
 784       return VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
 785    }
 786 }
 787
 788
 789 void
 790 zink_resource_barrier(VkCommandBuffer cmdbuf, struct zink_resource *res,
 791                       VkImageAspectFlags aspect, VkImageLayout new_layout)
 792 {
 793    VkImageSubresourceRange isr = {
 794       aspect,
 795       0, VK_REMAINING_MIP_LEVELS,
 796       0, VK_REMAINING_ARRAY_LAYERS
 797    };
 798
 799    VkImageMemoryBarrier imb = {
 800       VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
 801       NULL,
 802       access_src_flags(res->layout),
 803       access_dst_flags(new_layout),
 804       res->layout,
 805       new_layout,
 806       VK_QUEUE_FAMILY_IGNORED,
 807       VK_QUEUE_FAMILY_IGNORED,
 808       res->image,
 809       isr
 810    };
 811    vkCmdPipelineBarrier(
 812       cmdbuf,
 813       pipeline_src_stage(res->layout),
 814       pipeline_dst_stage(new_layout),
 815       0,
 816       0, NULL,
 817       0, NULL,
 818       1, &imb
 819    );
 820
 821    res->layout = new_layout;
 822 }
 823
 824 static void
 825 zink_clear(struct pipe_context *pctx,
 826            unsigned buffers,
 827            const union pipe_color_union *pcolor,
 828            double depth, unsigned stencil)
 829 {
 830    struct zink_context *ctx = zink_context(pctx);
 831    struct pipe_framebuffer_state *fb = &ctx->fb_state;
 832
 833    /* FIXME: this is very inefficient; if no renderpass has been started yet,
 834     * we should record the clear if it's full-screen, and apply it as we
 835     * start the render-pass. Otherwise we can do a partial out-of-renderpass
 836     * clear.
 837     */
 838    struct zink_batch *batch = zink_batch_rp(ctx);
 839
 840    VkClearAttachment attachments[1 + PIPE_MAX_COLOR_BUFS];
 841    int num_attachments = 0;
 842
 843    if (buffers & PIPE_CLEAR_COLOR) {
 844       VkClearColorValue color;
 845       color.float32[0] = pcolor->f[0];
 846       color.float32[1] = pcolor->f[1];
 847       color.float32[2] = pcolor->f[2];
 848       color.float32[3] = pcolor->f[3];
 849
 850       for (unsigned i = 0; i < fb->nr_cbufs; i++) {
 851          if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
 852             continue;
 853
 854          attachments[num_attachments].aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
 855          attachments[num_attachments].colorAttachment = i;
 856          attachments[num_attachments].clearValue.color = color;
 857          ++num_attachments;
 858       }
 859    }
 860
 861    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && fb->zsbuf) {
 862       VkImageAspectFlags aspect = 0;
 863       if (buffers & PIPE_CLEAR_DEPTH)
 864          aspect |= VK_IMAGE_ASPECT_DEPTH_BIT;
 865       if (buffers & PIPE_CLEAR_STENCIL)
 866          aspect |= VK_IMAGE_ASPECT_STENCIL_BIT;
 867
 868       attachments[num_attachments].aspectMask = aspect;
 869       attachments[num_attachments].clearValue.depthStencil.depth = depth;
 870       attachments[num_attachments].clearValue.depthStencil.stencil = stencil;
 871       ++num_attachments;
 872    }
 873
 874    VkClearRect cr;
 875    cr.rect.offset.x = 0;
 876    cr.rect.offset.y = 0;
 877    cr.rect.extent.width = fb->width;
 878    cr.rect.extent.height = fb->height;
 879    cr.baseArrayLayer = 0;
 880    cr.layerCount = util_framebuffer_get_num_layers(fb);
 881    vkCmdClearAttachments(batch->cmdbuf, num_attachments, attachments, 1, &cr);
 882 }
 883
 884 VkShaderStageFlagBits
 885 zink_shader_stage(enum pipe_shader_type type)
 886 {
 887    VkShaderStageFlagBits stages[] = {
 888       [PIPE_SHADER_VERTEX] = VK_SHADER_STAGE_VERTEX_BIT,
 889       [PIPE_SHADER_FRAGMENT] = VK_SHADER_STAGE_FRAGMENT_BIT,
 890       [PIPE_SHADER_GEOMETRY] = VK_SHADER_STAGE_GEOMETRY_BIT,
 891       [PIPE_SHADER_TESS_CTRL] = VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT,
 892       [PIPE_SHADER_TESS_EVAL] = VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
 893       [PIPE_SHADER_COMPUTE] = VK_SHADER_STAGE_COMPUTE_BIT,
 894    };
 895    return stages[type];
 896 }
 897
 898 static VkDescriptorSet
 899 allocate_descriptor_set(struct zink_screen *screen,
 900                         struct zink_batch *batch,
 901                         struct zink_gfx_program *prog)
 902 {
 903    assert(batch->descs_left >= prog->num_descriptors);
 904    VkDescriptorSetAllocateInfo dsai;
 905    memset((void *)&dsai, 0, sizeof(dsai));
 906    dsai.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO;
 907    dsai.pNext = NULL;
 908    dsai.descriptorPool = batch->descpool;
 909    dsai.descriptorSetCount = 1;
 910    dsai.pSetLayouts = &prog->dsl;
 911
 912    VkDescriptorSet desc_set;
 913    if (vkAllocateDescriptorSets(screen->dev, &dsai, &desc_set) != VK_SUCCESS) {
 914       debug_printf("ZINK: failed to allocate descriptor set :/");
 915       return VK_NULL_HANDLE;
 916    }
 917
 918    batch->descs_left -= prog->num_descriptors;
 919    return desc_set;
 920 }
 921
 922 static void
 923 zink_bind_vertex_buffers(struct zink_batch *batch, struct zink_context *ctx)
 924 {
 925    VkBuffer buffers[PIPE_MAX_ATTRIBS];
 926    VkDeviceSize buffer_offsets[PIPE_MAX_ATTRIBS];
 927    const struct zink_vertex_elements_state *elems = ctx->element_state;
 928    for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) {
 929       struct pipe_vertex_buffer *vb = ctx->buffers + ctx->element_state->binding_map[i];
 930       assert(vb && vb->buffer.resource);
 931       struct zink_resource *res = zink_resource(vb->buffer.resource);
 932       buffers[i] = res->buffer;
 933       buffer_offsets[i] = vb->buffer_offset;
 934       zink_batch_reference_resoure(batch, res);
 935    }
 936
 937    if (elems->hw_state.num_bindings > 0)
 938       vkCmdBindVertexBuffers(batch->cmdbuf, 0,
 939                              elems->hw_state.num_bindings,
 940                              buffers, buffer_offsets);
 941 }
 942
 943 static uint32_t
 944 hash_gfx_program(const void *key)
 945 {
 946    return _mesa_hash_data(key, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1));
 947 }
 948
 949 static bool
 950 equals_gfx_program(const void *a, const void *b)
 951 {
 952    return memcmp(a, b, sizeof(struct zink_shader *) * (PIPE_SHADER_TYPES - 1)) == 0;
 953 }
 954
 955 static uint32_t
 956 hash_render_pass_state(const void *key)
 957 {
 958    return _mesa_hash_data(key, sizeof(struct zink_render_pass_state));
 959 }
 960
 961 static bool
 962 equals_render_pass_state(const void *a, const void *b)
 963 {
 964    return memcmp(a, b, sizeof(struct zink_render_pass_state)) == 0;
 965 }
 966
 967 static uint32_t
 968 hash_framebuffer_state(const void *key)
 969 {
 970    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)key;
 971    return _mesa_hash_data(key, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments);
 972 }
 973
 974 static bool
 975 equals_framebuffer_state(const void *a, const void *b)
 976 {
 977    struct zink_framebuffer_state *s = (struct zink_framebuffer_state*)a;
 978    return memcmp(a, b, sizeof(struct zink_framebuffer_state) + sizeof(s->attachments) * s->num_attachments) == 0;
 979 }
 980
 981 static struct zink_gfx_program *
 982 get_gfx_program(struct zink_context *ctx)
 983 {
 984    if (ctx->dirty_program) {
 985       struct hash_entry *entry = _mesa_hash_table_search(ctx->program_cache,
 986                                                          ctx->gfx_stages);
 987       if (!entry) {
 988          struct zink_gfx_program *prog;
 989          prog = zink_create_gfx_program(zink_screen(ctx->base.screen),
 990                                                      ctx->gfx_stages);
 991          entry = _mesa_hash_table_insert(ctx->program_cache, prog->stages, prog);
 992          if (!entry)
 993             return NULL;
 994       }
 995       ctx->curr_program = entry->data;
 996       ctx->dirty_program = false;
 997    }
 998
 999    assert(ctx->curr_program);
1000    return ctx->curr_program;
1001 }
1002
1003 static void
1004 zink_draw_vbo(struct pipe_context *pctx,
1005               const struct pipe_draw_info *dinfo)
1006 {
1007    struct zink_context *ctx = zink_context(pctx);
1008    struct zink_screen *screen = zink_screen(pctx->screen);
1009    struct zink_rasterizer_state *rast_state = ctx->rast_state;
1010
1011    if (dinfo->mode >= PIPE_PRIM_QUADS ||
1012        dinfo->mode == PIPE_PRIM_LINE_LOOP ||
1013        dinfo->index_size == 1) {
1014       if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&dinfo->count))
1015          return;
1016
1017       util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
1018       util_primconvert_draw_vbo(ctx->primconvert, dinfo);
1019       return;
1020    }
1021
1022    struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
1023    if (!gfx_program)
1024       return;
1025
1026    VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
1027                                                &ctx->gfx_pipeline_state,
1028                                                dinfo->mode);
1029
1030    enum pipe_prim_type reduced_prim = u_reduced_prim(dinfo->mode);
1031
1032    bool depth_bias = false;
1033    switch (reduced_prim) {
1034    case PIPE_PRIM_POINTS:
1035       depth_bias = rast_state->offset_point;
1036       break;
1037
1038    case PIPE_PRIM_LINES:
1039       depth_bias = rast_state->offset_line;
1040       break;
1041
1042    case PIPE_PRIM_TRIANGLES:
1043       depth_bias = rast_state->offset_tri;
1044       break;
1045
1046    default:
1047       unreachable("unexpected reduced prim");
1048    }
1049
1050    unsigned index_offset = 0;
1051    struct pipe_resource *index_buffer = NULL;
1052    if (dinfo->index_size > 0) {
1053       if (dinfo->has_user_indices) {
1054          if (!util_upload_index_buffer(pctx, dinfo, &index_buffer, &index_offset)) {
1055             debug_printf("util_upload_index_buffer() failed\n");
1056             return;
1057          }
1058       } else
1059          index_buffer = dinfo->index.resource;
1060    }
1061
1062    VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS + PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
1063    VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * PIPE_MAX_CONSTANT_BUFFERS];
1064    VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
1065    int num_wds = 0, num_buffer_info = 0, num_image_info = 0;
1066
1067    struct zink_resource *transitions[PIPE_SHADER_TYPES * PIPE_MAX_SHADER_SAMPLER_VIEWS];
1068    int num_transitions = 0;
1069
1070    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1071       struct zink_shader *shader = ctx->gfx_stages[i];
1072       if (!shader)
1073          continue;
1074
1075       for (int j = 0; j < shader->num_bindings; j++) {
1076          int index = shader->bindings[j].index;
1077          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1078             assert(ctx->ubos[i][index].buffer_size > 0);
1079             assert(ctx->ubos[i][index].buffer_size <= screen->props.limits.maxUniformBufferRange);
1080             assert(ctx->ubos[i][index].buffer);
1081             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1082             buffer_infos[num_buffer_info].buffer = res->buffer;
1083             buffer_infos[num_buffer_info].offset = ctx->ubos[i][index].buffer_offset;
1084             buffer_infos[num_buffer_info].range  = ctx->ubos[i][index].buffer_size;
1085             wds[num_wds].pBufferInfo = buffer_infos + num_buffer_info;
1086             ++num_buffer_info;
1087          } else {
1088             struct pipe_sampler_view *psampler_view = ctx->image_views[i][index];
1089             assert(psampler_view);
1090             struct zink_sampler_view *sampler_view = zink_sampler_view(psampler_view);
1091
1092             struct zink_resource *res = zink_resource(psampler_view->texture);
1093             VkImageLayout layout = res->layout;
1094             if (layout != VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL &&
1095                 layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL &&
1096                 layout != VK_IMAGE_LAYOUT_GENERAL) {
1097                transitions[num_transitions++] = res;
1098                layout = VK_IMAGE_LAYOUT_GENERAL;
1099             }
1100             image_infos[num_image_info].imageLayout = layout;
1101             image_infos[num_image_info].imageView = sampler_view->image_view;
1102             image_infos[num_image_info].sampler = ctx->samplers[i][index];
1103             wds[num_wds].pImageInfo = image_infos + num_image_info;
1104             ++num_image_info;
1105          }
1106
1107          wds[num_wds].sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET;
1108          wds[num_wds].pNext = NULL;
1109          wds[num_wds].dstBinding = shader->bindings[j].binding;
1110          wds[num_wds].dstArrayElement = 0;
1111          wds[num_wds].descriptorCount = 1;
1112          wds[num_wds].descriptorType = shader->bindings[j].type;
1113          ++num_wds;
1114       }
1115    }
1116
1117    struct zink_batch *batch;
1118    if (num_transitions > 0) {
1119       batch = zink_batch_no_rp(ctx);
1120
1121       for (int i = 0; i < num_transitions; ++i)
1122          zink_resource_barrier(batch->cmdbuf, transitions[i],
1123                                transitions[i]->aspect,
1124                                VK_IMAGE_LAYOUT_GENERAL);
1125    }
1126
1127    batch = zink_batch_rp(ctx);
1128
1129    if (batch->descs_left < gfx_program->num_descriptors) {
1130       flush_batch(ctx);
1131       batch = zink_batch_rp(ctx);
1132       assert(batch->descs_left >= gfx_program->num_descriptors);
1133    }
1134
1135    VkDescriptorSet desc_set = allocate_descriptor_set(screen, batch,
1136                                                       gfx_program);
1137    assert(desc_set != VK_NULL_HANDLE);
1138
1139    for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
1140       struct zink_shader *shader = ctx->gfx_stages[i];
1141       if (!shader)
1142          continue;
1143
1144       for (int j = 0; j < shader->num_bindings; j++) {
1145          int index = shader->bindings[j].index;
1146          if (shader->bindings[j].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
1147             struct zink_resource *res = zink_resource(ctx->ubos[i][index].buffer);
1148             zink_batch_reference_resoure(batch, res);
1149          } else {
1150             struct zink_sampler_view *sampler_view = zink_sampler_view(ctx->image_views[i][index]);
1151             zink_batch_reference_sampler_view(batch, sampler_view);
1152          }
1153       }
1154    }
1155
1156    vkCmdSetViewport(batch->cmdbuf, 0, ctx->num_viewports, ctx->viewports);
1157    if (ctx->rast_state->base.scissor)
1158       vkCmdSetScissor(batch->cmdbuf, 0, ctx->num_viewports, ctx->scissors);
1159    else if (ctx->fb_state.width && ctx->fb_state.height) {
1160       VkRect2D fb_scissor = {};
1161       fb_scissor.extent.width = ctx->fb_state.width;
1162       fb_scissor.extent.height = ctx->fb_state.height;
1163       vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
1164    }
1165
1166    if (reduced_prim == PIPE_PRIM_LINES) {
1167       if (screen->feats.wideLines || ctx->line_width == 1.0f)
1168          vkCmdSetLineWidth(batch->cmdbuf, ctx->line_width);
1169       else
1170          debug_printf("BUG: wide lines not supported, needs fallback!");
1171    }
1172
1173    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref.ref_value[0]);
1174    vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref.ref_value[1]);
1175
1176    if (depth_bias)
1177       vkCmdSetDepthBias(batch->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
1178    else
1179       vkCmdSetDepthBias(batch->cmdbuf, 0.0f, 0.0f, 0.0f);
1180
1181    if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
1182       vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
1183
1184    if (num_wds > 0) {
1185       for (int i = 0; i < num_wds; ++i)
1186          wds[i].dstSet = desc_set;
1187       vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
1188    }
1189
1190    vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
1191    vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
1192                            gfx_program->layout, 0, 1, &desc_set, 0, NULL);
1193    zink_bind_vertex_buffers(batch, ctx);
1194
1195    if (dinfo->index_size > 0) {
1196       assert(dinfo->index_size != 1);
1197       VkIndexType index_type = dinfo->index_size == 2 ? VK_INDEX_TYPE_UINT16 : VK_INDEX_TYPE_UINT32;
1198       struct zink_resource *res = zink_resource(index_buffer);
1199       vkCmdBindIndexBuffer(batch->cmdbuf, res->buffer, index_offset, index_type);
1200       zink_batch_reference_resoure(batch, res);
1201       vkCmdDrawIndexed(batch->cmdbuf,
1202          dinfo->count, dinfo->instance_count,
1203          dinfo->start, dinfo->index_bias, dinfo->start_instance);
1204    } else
1205       vkCmdDraw(batch->cmdbuf, dinfo->count, dinfo->instance_count, dinfo->start, dinfo->start_instance);
1206
1207    if (dinfo->index_size > 0 && dinfo->has_user_indices)
1208       pipe_resource_reference(&index_buffer, NULL);
1209 }
1210
1211 static void
1212 zink_flush(struct pipe_context *pctx,
1213            struct pipe_fence_handle **pfence,
1214            enum pipe_flush_flags flags)
1215 {
1216    struct zink_context *ctx = zink_context(pctx);
1217
1218    struct zink_batch *batch = zink_curr_batch(ctx);
1219    flush_batch(ctx);
1220
1221    if (pfence)
1222       zink_fence_reference(zink_screen(pctx->screen),
1223                            (struct zink_fence **)pfence,
1224                            batch->fence);
1225
1226    /* HACK:
1227     * For some strange reason, we need to finish before presenting, or else
1228     * we start rendering on top of the back-buffer for the next frame. This
1229     * seems like a bug in the DRI-driver to me, because we really should
1230     * be properly protected by fences here, and the back-buffer should
1231     * either be swapped with the front-buffer, or blitted from. But for
1232     * some strange reason, neither of these things happen.
1233     */
1234    if (flags & PIPE_FLUSH_END_OF_FRAME)
1235       pctx->screen->fence_finish(pctx->screen, pctx,
1236                                  (struct pipe_fence_handle *)batch->fence,
1237                                  PIPE_TIMEOUT_INFINITE);
1238 }
1239
1240 static bool
1241 blit_resolve(struct zink_context *ctx, const struct pipe_blit_info *info)
1242 {
1243    if (info->mask != PIPE_MASK_RGBA ||
1244        info->scissor_enable ||
1245        info->alpha_blend)
1246       return false;
1247
1248    struct zink_resource *src = zink_resource(info->src.resource);
1249    struct zink_resource *dst = zink_resource(info->dst.resource);
1250
1251    struct zink_batch *batch = zink_batch_no_rp(ctx);
1252
1253    zink_batch_reference_resoure(batch, src);
1254    zink_batch_reference_resoure(batch, dst);
1255
1256    VkImageResolve region = {};
1257
1258    region.srcSubresource.aspectMask = src->aspect;
1259    region.srcSubresource.mipLevel = info->src.level;
1260    region.srcSubresource.baseArrayLayer = 0; // no clue
1261    region.srcSubresource.layerCount = 1; // no clue
1262    region.srcOffset.x = info->src.box.x;
1263    region.srcOffset.y = info->src.box.y;
1264    region.srcOffset.z = info->src.box.z;
1265
1266    region.dstSubresource.aspectMask = dst->aspect;
1267    region.dstSubresource.mipLevel = info->dst.level;
1268    region.dstSubresource.baseArrayLayer = 0; // no clue
1269    region.dstSubresource.layerCount = 1; // no clue
1270    region.dstOffset.x = info->dst.box.x;
1271    region.dstOffset.y = info->dst.box.y;
1272    region.dstOffset.z = info->dst.box.z;
1273
1274    region.extent.width = info->dst.box.width;
1275    region.extent.height = info->dst.box.height;
1276    region.extent.depth = info->dst.box.depth;
1277    vkCmdResolveImage(batch->cmdbuf, src->image, src->layout,
1278                      dst->image, dst->layout,
1279                      1, &region);
1280
1281    /* HACK: I have no idea why this is needed, but without it ioquake3
1282     * randomly keeps fading to black.
1283     */
1284    flush_batch(ctx);
1285
1286    return true;
1287 }
1288
1289 static bool
1290 blit_native(struct zink_context *ctx, const struct pipe_blit_info *info)
1291 {
1292    if (info->mask != PIPE_MASK_RGBA ||
1293        info->scissor_enable ||
1294        info->alpha_blend)
1295       return false;
1296
1297    struct zink_resource *src = zink_resource(info->src.resource);
1298    struct zink_resource *dst = zink_resource(info->dst.resource);
1299
1300    struct zink_batch *batch = zink_batch_no_rp(ctx);
1301    zink_batch_reference_resoure(batch, src);
1302    zink_batch_reference_resoure(batch, dst);
1303
1304    if (dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL)
1305       zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1306                             VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
1307
1308    VkImageBlit region = {};
1309    region.srcSubresource.aspectMask = src->aspect;
1310    region.srcSubresource.mipLevel = info->src.level;
1311    region.srcOffsets[0].x = info->src.box.x;
1312    region.srcOffsets[0].y = info->src.box.y;
1313    region.srcOffsets[1].x = info->src.box.x + info->src.box.width;
1314    region.srcOffsets[1].y = info->src.box.y + info->src.box.height;
1315
1316    if (src->base.array_size > 1) {
1317       region.srcOffsets[0].z = 0;
1318       region.srcOffsets[1].z = 1;
1319       region.srcSubresource.baseArrayLayer = info->src.box.z;
1320       region.srcSubresource.layerCount = info->src.box.depth;
1321    } else {
1322       region.srcOffsets[0].z = info->src.box.z;
1323       region.srcOffsets[1].z = info->src.box.z + info->src.box.depth;
1324       region.srcSubresource.baseArrayLayer = 0;
1325       region.srcSubresource.layerCount = 1;
1326    }
1327
1328    region.dstSubresource.aspectMask = dst->aspect;
1329    region.dstSubresource.mipLevel = info->dst.level;
1330    region.dstOffsets[0].x = info->dst.box.x;
1331    region.dstOffsets[0].y = info->dst.box.y;
1332    region.dstOffsets[1].x = info->dst.box.x + info->dst.box.width;
1333    region.dstOffsets[1].y = info->dst.box.y + info->dst.box.height;
1334
1335    if (dst->base.array_size > 1) {
1336       region.dstOffsets[0].z = 0;
1337       region.dstOffsets[1].z = 1;
1338       region.dstSubresource.baseArrayLayer = info->dst.box.z;
1339       region.dstSubresource.layerCount = info->dst.box.depth;
1340    } else {
1341       region.dstOffsets[0].z = info->dst.box.z;
1342       region.dstOffsets[1].z = info->dst.box.z + info->dst.box.depth;
1343       region.dstSubresource.baseArrayLayer = 0;
1344       region.dstSubresource.layerCount = 1;
1345    }
1346
1347    vkCmdBlitImage(batch->cmdbuf, src->image, src->layout,
1348                   dst->image, dst->layout,
1349                   1, &region,
1350                   filter(info->filter));
1351
1352    /* HACK: I have no idea why this is needed, but without it ioquake3
1353     * randomly keeps fading to black.
1354     */
1355    flush_batch(ctx);
1356
1357    return true;
1358 }
1359
1360 static void
1361 zink_blit(struct pipe_context *pctx,
1362           const struct pipe_blit_info *info)
1363 {
1364    struct zink_context *ctx = zink_context(pctx);
1365    if (info->src.resource->nr_samples > 1 &&
1366        info->dst.resource->nr_samples <= 1) {
1367       if (blit_resolve(ctx, info))
1368          return;
1369    } else {
1370       if (blit_native(ctx, info))
1371          return;
1372    }
1373
1374    if (!util_blitter_is_blit_supported(ctx->blitter, info)) {
1375       debug_printf("blit unsupported %s -> %s\n",
1376               util_format_short_name(info->src.resource->format),
1377               util_format_short_name(info->dst.resource->format));
1378       return;
1379    }
1380
1381    util_blitter_save_blend(ctx->blitter, ctx->gfx_pipeline_state.blend_state);
1382    util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->gfx_pipeline_state.depth_stencil_alpha_state);
1383    util_blitter_save_vertex_elements(ctx->blitter, ctx->element_state);
1384    util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
1385    util_blitter_save_rasterizer(ctx->blitter, ctx->rast_state);
1386    util_blitter_save_fragment_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_FRAGMENT]);
1387    util_blitter_save_vertex_shader(ctx->blitter, ctx->gfx_stages[PIPE_SHADER_VERTEX]);
1388    util_blitter_save_framebuffer(ctx->blitter, &ctx->fb_state);
1389    util_blitter_save_viewport(ctx->blitter, ctx->viewport_states);
1390    util_blitter_save_scissor(ctx->blitter, ctx->scissor_states);
1391    util_blitter_save_fragment_sampler_states(ctx->blitter,
1392                                              ctx->num_samplers[PIPE_SHADER_FRAGMENT],
1393                                              (void **)ctx->samplers[PIPE_SHADER_FRAGMENT]);
1394    util_blitter_save_fragment_sampler_views(ctx->blitter,
1395                                             ctx->num_image_views[PIPE_SHADER_FRAGMENT],
1396                                             ctx->image_views[PIPE_SHADER_FRAGMENT]);
1397    util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[PIPE_SHADER_FRAGMENT]);
1398    util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->buffers);
1399    util_blitter_save_sample_mask(ctx->blitter, ctx->gfx_pipeline_state.sample_mask);
1400
1401    util_blitter_blit(ctx->blitter, info);
1402 }
1403
1404 static void
1405 zink_flush_resource(struct pipe_context *pipe,
1406                     struct pipe_resource *resource)
1407 {
1408 }
1409
1410 static void
1411 zink_resource_copy_region(struct pipe_context *pctx,
1412                           struct pipe_resource *pdst,
1413                           unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1414                           struct pipe_resource *psrc,
1415                           unsigned src_level, const struct pipe_box *src_box)
1416 {
1417    struct zink_resource *dst = zink_resource(pdst);
1418    struct zink_resource *src = zink_resource(psrc);
1419    struct zink_context *ctx = zink_context(pctx);
1420    if (dst->base.target != PIPE_BUFFER && src->base.target != PIPE_BUFFER) {
1421       VkImageCopy region = {};
1422
1423       region.srcSubresource.aspectMask = src->aspect;
1424       region.srcSubresource.mipLevel = src_level;
1425       region.srcSubresource.layerCount = 1;
1426       if (src->base.array_size > 1) {
1427          region.srcSubresource.baseArrayLayer = src_box->z;
1428          region.srcSubresource.layerCount = src_box->depth;
1429          region.extent.depth = 1;
1430       } else {
1431          region.srcOffset.z = src_box->z;
1432          region.srcSubresource.layerCount = 1;
1433          region.extent.depth = src_box->depth;
1434       }
1435
1436       region.srcOffset.x = src_box->x;
1437       region.srcOffset.y = src_box->y;
1438
1439       region.dstSubresource.aspectMask = dst->aspect;
1440       region.dstSubresource.mipLevel = dst_level;
1441       if (dst->base.array_size > 1) {
1442          region.dstSubresource.baseArrayLayer = dstz;
1443          region.dstSubresource.layerCount = src_box->depth;
1444       } else {
1445          region.dstOffset.z = dstz;
1446          region.dstSubresource.layerCount = 1;
1447       }
1448
1449       region.dstOffset.x = dstx;
1450       region.dstOffset.y = dsty;
1451       region.extent.width = src_box->width;
1452       region.extent.height = src_box->height;
1453
1454       struct zink_batch *batch = zink_batch_no_rp(ctx);
1455       zink_batch_reference_resoure(batch, src);
1456       zink_batch_reference_resoure(batch, dst);
1457
1458       if (src->layout != VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL) {
1459          zink_resource_barrier(batch->cmdbuf, src, src->aspect,
1460                                VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL);
1461       }
1462
1463       if (dst->layout != VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) {
1464          zink_resource_barrier(batch->cmdbuf, dst, dst->aspect,
1465                                VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
1466       }
1467
1468       vkCmdCopyImage(batch->cmdbuf, src->image, src->layout,
1469                      dst->image, dst->layout,
1470                      1, &region);
1471    } else
1472       debug_printf("zink: TODO resource copy\n");
1473 }
1474
1475 struct pipe_context *
1476 zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
1477 {
1478    struct zink_screen *screen = zink_screen(pscreen);
1479    struct zink_context *ctx = CALLOC_STRUCT(zink_context);
1480
1481    ctx->base.screen = pscreen;
1482    ctx->base.priv = priv;
1483
1484    ctx->base.destroy = zink_context_destroy;
1485
1486    zink_context_state_init(&ctx->base);
1487
1488    ctx->base.create_sampler_state = zink_create_sampler_state;
1489    ctx->base.bind_sampler_states = zink_bind_sampler_states;
1490    ctx->base.delete_sampler_state = zink_delete_sampler_state;
1491
1492    ctx->base.create_sampler_view = zink_create_sampler_view;
1493    ctx->base.set_sampler_views = zink_set_sampler_views;
1494    ctx->base.sampler_view_destroy = zink_sampler_view_destroy;
1495
1496    ctx->base.create_vs_state = zink_create_vs_state;
1497    ctx->base.bind_vs_state = zink_bind_vs_state;
1498    ctx->base.delete_vs_state = zink_delete_vs_state;
1499
1500    ctx->base.create_fs_state = zink_create_fs_state;
1501    ctx->base.bind_fs_state = zink_bind_fs_state;
1502    ctx->base.delete_fs_state = zink_delete_fs_state;
1503
1504    ctx->base.set_polygon_stipple = zink_set_polygon_stipple;
1505    ctx->base.set_vertex_buffers = zink_set_vertex_buffers;
1506    ctx->base.set_viewport_states = zink_set_viewport_states;
1507    ctx->base.set_scissor_states = zink_set_scissor_states;
1508    ctx->base.set_constant_buffer = zink_set_constant_buffer;
1509    ctx->base.set_framebuffer_state = zink_set_framebuffer_state;
1510    ctx->base.set_stencil_ref = zink_set_stencil_ref;
1511    ctx->base.set_clip_state = zink_set_clip_state;
1512    ctx->base.set_blend_color = zink_set_blend_color;
1513
1514    ctx->base.set_sample_mask = zink_set_sample_mask;
1515
1516    ctx->base.clear = zink_clear;
1517    ctx->base.draw_vbo = zink_draw_vbo;
1518    ctx->base.flush = zink_flush;
1519
1520    ctx->base.resource_copy_region = zink_resource_copy_region;
1521    ctx->base.blit = zink_blit;
1522
1523    ctx->base.flush_resource = zink_flush_resource;
1524    zink_context_surface_init(&ctx->base);
1525    zink_context_resource_init(&ctx->base);
1526    zink_context_query_init(&ctx->base);
1527
1528    slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
1529
1530    ctx->base.stream_uploader = u_upload_create_default(&ctx->base);
1531    ctx->base.const_uploader = ctx->base.stream_uploader;
1532
1533    int prim_hwsupport = 1 << PIPE_PRIM_POINTS |
1534                         1 << PIPE_PRIM_LINES |
1535                         1 << PIPE_PRIM_LINE_STRIP |
1536                         1 << PIPE_PRIM_TRIANGLES |
1537                         1 << PIPE_PRIM_TRIANGLE_STRIP |
1538                         1 << PIPE_PRIM_TRIANGLE_FAN;
1539
1540    ctx->primconvert = util_primconvert_create(&ctx->base, prim_hwsupport);
1541    if (!ctx->primconvert)
1542       goto fail;
1543
1544    ctx->blitter = util_blitter_create(&ctx->base);
1545    if (!ctx->blitter)
1546       goto fail;
1547
1548    VkCommandPoolCreateInfo cpci = {};
1549    cpci.sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO;
1550    cpci.queueFamilyIndex = screen->gfx_queue;
1551    cpci.flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT;
1552    if (vkCreateCommandPool(screen->dev, &cpci, NULL, &ctx->cmdpool) != VK_SUCCESS)
1553       goto fail;
1554
1555    VkCommandBufferAllocateInfo cbai = {};
1556    cbai.sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO;
1557    cbai.commandPool = ctx->cmdpool;
1558    cbai.level = VK_COMMAND_BUFFER_LEVEL_PRIMARY;
1559    cbai.commandBufferCount = 1;
1560
1561    VkDescriptorPoolSize sizes[] = {
1562       {VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER, ZINK_BATCH_DESC_SIZE}
1563    };
1564    VkDescriptorPoolCreateInfo dpci = {};
1565    dpci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO;
1566    dpci.pPoolSizes = sizes;
1567    dpci.poolSizeCount = ARRAY_SIZE(sizes);
1568    dpci.flags = VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT;
1569    dpci.maxSets = ZINK_BATCH_DESC_SIZE;
1570
1571    for (int i = 0; i < ARRAY_SIZE(ctx->batches); ++i) {
1572       if (vkAllocateCommandBuffers(screen->dev, &cbai, &ctx->batches[i].cmdbuf) != VK_SUCCESS)
1573          goto fail;
1574
1575       ctx->batches[i].resources = _mesa_set_create(NULL, _mesa_hash_pointer,
1576                                                    _mesa_key_pointer_equal);
1577       ctx->batches[i].sampler_views = _mesa_set_create(NULL,
1578                                                        _mesa_hash_pointer,
1579                                                        _mesa_key_pointer_equal);
1580
1581       if (!ctx->batches[i].resources || !ctx->batches[i].sampler_views)
1582          goto fail;
1583
1584       util_dynarray_init(&ctx->batches[i].zombie_samplers, NULL);
1585
1586       if (vkCreateDescriptorPool(screen->dev, &dpci, 0,
1587                                  &ctx->batches[i].descpool) != VK_SUCCESS)
1588          goto fail;
1589    }
1590
1591    vkGetDeviceQueue(screen->dev, screen->gfx_queue, 0, &ctx->queue);
1592
1593    ctx->program_cache = _mesa_hash_table_create(NULL,
1594                                                 hash_gfx_program,
1595                                                 equals_gfx_program);
1596    ctx->render_pass_cache = _mesa_hash_table_create(NULL,
1597                                                     hash_render_pass_state,
1598                                                     equals_render_pass_state);
1599    ctx->framebuffer_cache = _mesa_hash_table_create(NULL,
1600                                                     hash_framebuffer_state,
1601                                                     equals_framebuffer_state);
1602
1603    if (!ctx->program_cache || !ctx->render_pass_cache ||
1604        !ctx->framebuffer_cache)
1605       goto fail;
1606
1607    ctx->dirty_program = true;
1608
1609    /* start the first batch */
1610    zink_start_batch(ctx, zink_curr_batch(ctx));
1611
1612    return &ctx->base;
1613
1614 fail:
1615    if (ctx) {
1616       vkDestroyCommandPool(screen->dev, ctx->cmdpool, NULL);
1617       FREE(ctx);
1618    }
1619    return NULL;
1620 }