2 * Copyright 2018 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "zink_screen.h"
26 #include "zink_compiler.h"
27 #include "zink_context.h"
28 #include "zink_fence.h"
29 #include "zink_public.h"
30 #include "zink_resource.h"
32 #include "os/os_process.h"
33 #include "util/u_debug.h"
34 #include "util/u_format.h"
35 #include "util/u_math.h"
36 #include "util/u_memory.h"
37 #include "util/u_screen.h"
38 #include "util/u_string.h"
40 #include "state_tracker/sw_winsys.h"
42 static const struct debug_named_value
44 { "nir", ZINK_DEBUG_NIR
, "Dump NIR during program compile" },
45 { "spirv", ZINK_DEBUG_SPIRV
, "Dump SPIR-V during program compile" },
46 { "tgsi", ZINK_DEBUG_TGSI
, "Dump TGSI during program compile" },
50 DEBUG_GET_ONCE_FLAGS_OPTION(zink_debug
, "ZINK_DEBUG", debug_options
, 0)
56 zink_get_vendor(struct pipe_screen
*pscreen
)
58 return "Collabora Ltd";
62 zink_get_device_vendor(struct pipe_screen
*pscreen
)
64 struct zink_screen
*screen
= zink_screen(pscreen
);
65 static char buf
[1000];
66 snprintf(buf
, sizeof(buf
), "Unknown (vendor-id: 0x%04x)", screen
->props
.vendorID
);
71 zink_get_name(struct pipe_screen
*pscreen
)
73 struct zink_screen
*screen
= zink_screen(pscreen
);
74 static char buf
[1000];
75 snprintf(buf
, sizeof(buf
), "zink (%s)", screen
->props
.deviceName
);
80 get_video_mem(struct zink_screen
*screen
)
82 VkDeviceSize size
= 0;
83 for (uint32_t i
= 0; i
< screen
->mem_props
.memoryHeapCount
; ++i
)
84 size
+= screen
->mem_props
.memoryHeaps
[i
].size
;
85 return (int)(size
>> 20);
89 zink_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
91 struct zink_screen
*screen
= zink_screen(pscreen
);
94 case PIPE_CAP_NPOT_TEXTURES
:
97 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
98 return screen
->props
.limits
.maxFragmentDualSrcAttachments
;
100 case PIPE_CAP_POINT_SPRITE
:
103 case PIPE_CAP_MAX_RENDER_TARGETS
:
104 return screen
->props
.limits
.maxColorAttachments
;
106 case PIPE_CAP_OCCLUSION_QUERY
:
107 case PIPE_CAP_QUERY_TIME_ELAPSED
:
110 case PIPE_CAP_TEXTURE_SWIZZLE
:
113 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
114 return screen
->props
.limits
.maxImageDimension2D
;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
116 return 1 + util_logbase2(screen
->props
.limits
.maxImageDimension3D
);
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
118 return 1 + util_logbase2(screen
->props
.limits
.maxImageDimensionCube
);
120 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
123 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
124 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
125 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
128 case PIPE_CAP_INDEP_BLEND_ENABLE
:
129 case PIPE_CAP_INDEP_BLEND_FUNC
:
132 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
133 return screen
->props
.limits
.maxImageArrayLayers
;
135 #if 0 /* TODO: Enable me */
136 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
140 #if 0 /* TODO: Enable me */
141 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
145 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
148 case PIPE_CAP_MIN_TEXEL_OFFSET
:
149 return screen
->props
.limits
.minTexelOffset
;
150 case PIPE_CAP_MAX_TEXEL_OFFSET
:
151 return screen
->props
.limits
.maxTexelOffset
;
153 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
156 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
157 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
158 return 450; /* unsure (probably wrong) */
160 #if 0 /* TODO: Enable me */
161 case PIPE_CAP_COMPUTE
:
165 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
166 return screen
->props
.limits
.minUniformBufferOffsetAlignment
;
168 case PIPE_CAP_QUERY_TIMESTAMP
:
171 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
172 return screen
->props
.limits
.minMemoryMapAlignment
;
174 case PIPE_CAP_CUBE_MAP_ARRAY
:
175 return screen
->feats
.imageCubeArray
;
177 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
178 return 0; /* unsure */
180 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
181 return screen
->props
.limits
.maxTexelBufferElements
;
183 case PIPE_CAP_ENDIANNESS
:
184 return PIPE_ENDIAN_NATIVE
; /* unsure */
186 case PIPE_CAP_MAX_VIEWPORTS
:
187 return screen
->props
.limits
.maxViewports
;
189 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
192 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
193 return screen
->props
.limits
.maxGeometryOutputVertices
;
194 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
195 return screen
->props
.limits
.maxGeometryOutputComponents
;
197 #if 0 /* TODO: Enable me. Enables ARB_texture_gather */
198 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
202 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
203 return screen
->props
.limits
.minTexelGatherOffset
;
204 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
205 return screen
->props
.limits
.maxTexelGatherOffset
;
207 case PIPE_CAP_VENDOR_ID
:
208 return screen
->props
.vendorID
;
209 case PIPE_CAP_DEVICE_ID
:
210 return screen
->props
.deviceID
;
212 case PIPE_CAP_ACCELERATED
:
214 case PIPE_CAP_VIDEO_MEMORY
:
215 return get_video_mem(screen
);
218 return screen
->props
.deviceType
== VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
;
220 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
221 return screen
->props
.limits
.maxVertexInputBindingStride
;
223 #if 0 /* TODO: Enable me */
224 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
228 #if 0 /* TODO: Enable me */
229 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
230 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
234 case PIPE_CAP_SHAREABLE_SHADERS
:
237 #if 0 /* TODO: Enable me. Enables GL_ARB_shader_storage_buffer_object */
238 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
239 return screen
->props
.limits
.minStorageBufferOffsetAlignment
;
242 case PIPE_CAP_PCI_GROUP
:
243 case PIPE_CAP_PCI_BUS
:
244 case PIPE_CAP_PCI_DEVICE
:
245 case PIPE_CAP_PCI_FUNCTION
:
246 return 0; /* TODO: figure these out */
248 #if 0 /* TODO: Enable me */
249 case PIPE_CAP_CULL_DISTANCE
:
250 return screen
->feats
.shaderCullDistance
;
253 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
254 return screen
->props
.limits
.viewportSubPixelBits
;
256 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
257 return 0; /* not sure */
259 case PIPE_CAP_MAX_GS_INVOCATIONS
:
260 return 0; /* not implemented */
262 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
263 return screen
->props
.limits
.maxDescriptorSetStorageBuffers
;
265 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
266 return screen
->props
.limits
.maxStorageBufferRange
; /* unsure */
268 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
269 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
272 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
273 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
276 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
279 case PIPE_CAP_NIR_COMPACT_ARRAYS
:
282 case PIPE_CAP_FLATSHADE
:
283 case PIPE_CAP_ALPHA_TEST
:
284 case PIPE_CAP_CLIP_PLANES
:
288 return u_pipe_screen_get_param_defaults(pscreen
, param
);
293 zink_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
295 struct zink_screen
*screen
= zink_screen(pscreen
);
298 case PIPE_CAPF_MAX_LINE_WIDTH
:
299 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
300 return screen
->props
.limits
.lineWidthRange
[1];
302 case PIPE_CAPF_MAX_POINT_WIDTH
:
303 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
304 return screen
->props
.limits
.pointSizeRange
[1];
306 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
307 return screen
->props
.limits
.maxSamplerAnisotropy
;
309 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
310 return screen
->props
.limits
.maxSamplerLodBias
;
312 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
313 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
314 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
315 return 0.0f
; /* not implemented */
318 /* should only get here on unhandled cases */
323 zink_get_shader_param(struct pipe_screen
*pscreen
,
324 enum pipe_shader_type shader
,
325 enum pipe_shader_cap param
)
327 struct zink_screen
*screen
= zink_screen(pscreen
);
330 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
331 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
332 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
333 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
334 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
335 if (shader
== PIPE_SHADER_VERTEX
||
336 shader
== PIPE_SHADER_FRAGMENT
)
340 case PIPE_SHADER_CAP_MAX_INPUTS
:
342 case PIPE_SHADER_VERTEX
:
343 return MIN2(screen
->props
.limits
.maxVertexInputAttributes
,
344 PIPE_MAX_SHADER_INPUTS
);
345 case PIPE_SHADER_FRAGMENT
:
346 return MIN2(screen
->props
.limits
.maxFragmentInputComponents
/ 4,
347 PIPE_MAX_SHADER_INPUTS
);
349 return 0; /* unsupported stage */
352 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
354 case PIPE_SHADER_VERTEX
:
355 return MIN2(screen
->props
.limits
.maxVertexOutputComponents
/ 4,
356 PIPE_MAX_SHADER_OUTPUTS
);
357 case PIPE_SHADER_FRAGMENT
:
358 return MIN2(screen
->props
.limits
.maxColorAttachments
,
359 PIPE_MAX_SHADER_OUTPUTS
);
361 return 0; /* unsupported stage */
364 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
365 /* this might be a bit simplistic... */
366 return MIN2(screen
->props
.limits
.maxPerStageDescriptorSamplers
,
369 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
370 return MIN2(screen
->props
.limits
.maxUniformBufferRange
, INT_MAX
);
372 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
373 return screen
->props
.limits
.maxPerStageDescriptorUniformBuffers
;
375 case PIPE_SHADER_CAP_MAX_TEMPS
:
378 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
379 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
380 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
381 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
382 case PIPE_SHADER_CAP_SUBROUTINES
:
383 case PIPE_SHADER_CAP_INTEGERS
:
384 case PIPE_SHADER_CAP_INT64_ATOMICS
:
385 case PIPE_SHADER_CAP_FP16
:
386 return 0; /* not implemented */
388 case PIPE_SHADER_CAP_PREFERRED_IR
:
389 return PIPE_SHADER_IR_NIR
;
391 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
392 return 0; /* not implemented */
394 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
395 return MIN2(screen
->props
.limits
.maxPerStageDescriptorSampledImages
,
396 PIPE_MAX_SHADER_SAMPLER_VIEWS
);
398 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
399 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
400 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
401 return 0; /* not implemented */
403 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
404 return 0; /* no idea */
406 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
407 return 32; /* arbitrary */
409 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
410 /* TODO: this limitation is dumb, and will need some fixes in mesa */
411 return MIN2(screen
->props
.limits
.maxPerStageDescriptorStorageBuffers
, 8);
413 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
414 return (1 << PIPE_SHADER_IR_NIR
) | (1 << PIPE_SHADER_IR_TGSI
);
416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
417 return MIN2(screen
->props
.limits
.maxPerStageDescriptorStorageImages
,
418 PIPE_MAX_SHADER_IMAGES
);
420 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
421 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
422 return 0; /* unsure */
424 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
425 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
426 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
427 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
428 return 0; /* not implemented */
431 /* should only get here on unhandled cases */
435 static const VkFormat formats
[PIPE_FORMAT_COUNT
] = {
436 #define MAP_FORMAT_NORM(FMT) \
437 [PIPE_FORMAT_ ## FMT ## _UNORM] = VK_FORMAT_ ## FMT ## _UNORM, \
438 [PIPE_FORMAT_ ## FMT ## _SNORM] = VK_FORMAT_ ## FMT ## _SNORM,
440 #define MAP_FORMAT_SCALED(FMT) \
441 [PIPE_FORMAT_ ## FMT ## _USCALED] = VK_FORMAT_ ## FMT ## _USCALED, \
442 [PIPE_FORMAT_ ## FMT ## _SSCALED] = VK_FORMAT_ ## FMT ## _SSCALED,
444 #define MAP_FORMAT_INT(FMT) \
445 [PIPE_FORMAT_ ## FMT ## _UINT] = VK_FORMAT_ ## FMT ## _UINT, \
446 [PIPE_FORMAT_ ## FMT ## _SINT] = VK_FORMAT_ ## FMT ## _SINT,
448 #define MAP_FORMAT_SRGB(FMT) \
449 [PIPE_FORMAT_ ## FMT ## _SRGB] = VK_FORMAT_ ## FMT ## _SRGB,
451 #define MAP_FORMAT_FLOAT(FMT) \
452 [PIPE_FORMAT_ ## FMT ## _FLOAT] = VK_FORMAT_ ## FMT ## _SFLOAT,
458 MAP_FORMAT_SCALED(R8
)
462 MAP_FORMAT_SCALED(R16
)
464 MAP_FORMAT_FLOAT(R16
)
467 MAP_FORMAT_FLOAT(R32
)
472 MAP_FORMAT_NORM(R8G8
)
473 MAP_FORMAT_SCALED(R8G8
)
476 MAP_FORMAT_NORM(R16G16
)
477 MAP_FORMAT_SCALED(R16G16
)
478 MAP_FORMAT_INT(R16G16
)
479 MAP_FORMAT_FLOAT(R16G16
)
481 MAP_FORMAT_INT(R32G32
)
482 MAP_FORMAT_FLOAT(R32G32
)
487 MAP_FORMAT_NORM(R8G8B8
)
488 MAP_FORMAT_SCALED(R8G8B8
)
489 MAP_FORMAT_INT(R8G8B8
)
490 MAP_FORMAT_SRGB(R8G8B8
)
492 MAP_FORMAT_NORM(R16G16B16
)
493 MAP_FORMAT_SCALED(R16G16B16
)
494 MAP_FORMAT_INT(R16G16B16
)
495 MAP_FORMAT_FLOAT(R16G16B16
)
497 MAP_FORMAT_INT(R32G32B32
)
498 MAP_FORMAT_FLOAT(R32G32B32
)
503 MAP_FORMAT_NORM(R8G8B8A8
)
504 MAP_FORMAT_SCALED(R8G8B8A8
)
505 MAP_FORMAT_INT(R8G8B8A8
)
506 MAP_FORMAT_SRGB(R8G8B8A8
)
507 [PIPE_FORMAT_B8G8R8A8_UNORM
] = VK_FORMAT_B8G8R8A8_UNORM
,
508 MAP_FORMAT_SRGB(B8G8R8A8
)
509 [PIPE_FORMAT_A8B8G8R8_SRGB
] = VK_FORMAT_A8B8G8R8_SRGB_PACK32
,
511 MAP_FORMAT_NORM(R16G16B16A16
)
512 MAP_FORMAT_SCALED(R16G16B16A16
)
513 MAP_FORMAT_INT(R16G16B16A16
)
514 MAP_FORMAT_FLOAT(R16G16B16A16
)
516 MAP_FORMAT_INT(R32G32B32A32
)
517 MAP_FORMAT_FLOAT(R32G32B32A32
)
519 // other color formats
520 [PIPE_FORMAT_B5G6R5_UNORM
] = VK_FORMAT_R5G6B5_UNORM_PACK16
,
521 [PIPE_FORMAT_B5G5R5A1_UNORM
] = VK_FORMAT_B5G5R5A1_UNORM_PACK16
,
522 [PIPE_FORMAT_R11G11B10_FLOAT
] = VK_FORMAT_B10G11R11_UFLOAT_PACK32
,
523 [PIPE_FORMAT_R9G9B9E5_FLOAT
] = VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
,
524 [PIPE_FORMAT_R10G10B10A2_UNORM
] = VK_FORMAT_A2B10G10R10_UNORM_PACK32
,
525 [PIPE_FORMAT_B10G10R10A2_UNORM
] = VK_FORMAT_A2R10G10B10_UNORM_PACK32
,
526 [PIPE_FORMAT_R10G10B10A2_UINT
] = VK_FORMAT_A2B10G10R10_UINT_PACK32
,
527 [PIPE_FORMAT_B10G10R10A2_UINT
] = VK_FORMAT_A2R10G10B10_UINT_PACK32
,
529 // depth/stencil formats
530 [PIPE_FORMAT_Z32_FLOAT
] = VK_FORMAT_D32_SFLOAT
,
531 [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
] = VK_FORMAT_D32_SFLOAT_S8_UINT
,
532 [PIPE_FORMAT_Z16_UNORM
] = VK_FORMAT_D16_UNORM
,
533 [PIPE_FORMAT_X8Z24_UNORM
] = VK_FORMAT_X8_D24_UNORM_PACK32
,
534 [PIPE_FORMAT_Z24_UNORM_S8_UINT
] = VK_FORMAT_D24_UNORM_S8_UINT
,
536 // compressed formats
537 [PIPE_FORMAT_DXT1_RGB
] = VK_FORMAT_BC1_RGB_UNORM_BLOCK
,
538 [PIPE_FORMAT_DXT1_RGBA
] = VK_FORMAT_BC1_RGBA_UNORM_BLOCK
,
539 [PIPE_FORMAT_DXT3_RGBA
] = VK_FORMAT_BC2_UNORM_BLOCK
,
540 [PIPE_FORMAT_DXT5_RGBA
] = VK_FORMAT_BC3_UNORM_BLOCK
,
541 [PIPE_FORMAT_RGTC1_UNORM
] = VK_FORMAT_BC4_UNORM_BLOCK
,
542 [PIPE_FORMAT_RGTC1_SNORM
] = VK_FORMAT_BC4_SNORM_BLOCK
,
543 [PIPE_FORMAT_RGTC2_UNORM
] = VK_FORMAT_BC5_UNORM_BLOCK
,
544 [PIPE_FORMAT_RGTC2_SNORM
] = VK_FORMAT_BC5_SNORM_BLOCK
,
545 [PIPE_FORMAT_BPTC_RGBA_UNORM
] = VK_FORMAT_BC7_UNORM_BLOCK
,
546 [PIPE_FORMAT_BPTC_SRGBA
] = VK_FORMAT_BC7_SRGB_BLOCK
,
547 [PIPE_FORMAT_BPTC_RGB_FLOAT
] = VK_FORMAT_BC6H_SFLOAT_BLOCK
,
548 [PIPE_FORMAT_BPTC_RGB_UFLOAT
] = VK_FORMAT_BC6H_UFLOAT_BLOCK
,
552 zink_get_format(enum pipe_format format
)
554 return formats
[format
];
558 zink_is_format_supported(struct pipe_screen
*pscreen
,
559 enum pipe_format format
,
560 enum pipe_texture_target target
,
561 unsigned sample_count
,
562 unsigned storage_sample_count
,
565 struct zink_screen
*screen
= zink_screen(pscreen
);
567 if (sample_count
> 1)
570 VkFormat vkformat
= formats
[format
];
571 if (vkformat
== VK_FORMAT_UNDEFINED
)
574 VkFormatProperties props
;
575 vkGetPhysicalDeviceFormatProperties(screen
->pdev
, vkformat
, &props
);
577 if (target
== PIPE_BUFFER
) {
578 if (bind
& PIPE_BIND_VERTEX_BUFFER
&&
579 !(props
.bufferFeatures
& VK_FORMAT_FEATURE_VERTEX_BUFFER_BIT
))
582 /* all other targets are texture-targets */
583 if (bind
& PIPE_BIND_RENDER_TARGET
&&
584 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT
))
587 if (bind
& PIPE_BIND_BLENDABLE
&&
588 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT
))
591 if (bind
& PIPE_BIND_SAMPLER_VIEW
&&
592 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT
))
595 if (bind
& PIPE_BIND_DEPTH_STENCIL
&&
596 !(props
.optimalTilingFeatures
& VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT
))
600 const struct util_format_description
*desc
= util_format_description(format
);
601 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
&&
602 !screen
->feats
.textureCompressionBC
)
609 zink_destroy_screen(struct pipe_screen
*pscreen
)
611 struct zink_screen
*screen
= zink_screen(pscreen
);
612 slab_destroy_parent(&screen
->transfer_pool
);
619 VkApplicationInfo ai
= {};
620 ai
.sType
= VK_STRUCTURE_TYPE_APPLICATION_INFO
;
623 if (os_get_process_name(proc_name
, ARRAY_SIZE(proc_name
)))
624 ai
.pApplicationName
= proc_name
;
626 ai
.pApplicationName
= "unknown";
628 ai
.pEngineName
= "mesa zink";
629 ai
.apiVersion
= VK_API_VERSION_1_0
;
631 const char *extensions
[] = {
632 VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
633 VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
636 VkInstanceCreateInfo ici
= {};
637 ici
.sType
= VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
;
638 ici
.pApplicationInfo
= &ai
;
639 ici
.ppEnabledExtensionNames
= extensions
;
640 ici
.enabledExtensionCount
= ARRAY_SIZE(extensions
);
642 VkInstance instance
= VK_NULL_HANDLE
;
643 VkResult err
= vkCreateInstance(&ici
, NULL
, &instance
);
644 if (err
!= VK_SUCCESS
)
645 return VK_NULL_HANDLE
;
650 static VkPhysicalDevice
651 choose_pdev(const VkInstance instance
)
653 uint32_t i
, pdev_count
;
654 VkPhysicalDevice
*pdevs
, pdev
;
655 vkEnumeratePhysicalDevices(instance
, &pdev_count
, NULL
);
656 assert(pdev_count
> 0);
658 pdevs
= malloc(sizeof(*pdevs
) * pdev_count
);
659 vkEnumeratePhysicalDevices(instance
, &pdev_count
, pdevs
);
660 assert(pdev_count
> 0);
663 for (i
= 0; i
< pdev_count
; ++i
) {
664 VkPhysicalDeviceProperties props
;
665 vkGetPhysicalDeviceProperties(pdevs
[i
], &props
);
666 if (props
.deviceType
== VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
) {
676 find_gfx_queue(const VkPhysicalDevice pdev
)
679 vkGetPhysicalDeviceQueueFamilyProperties(pdev
, &num_queues
, NULL
);
680 assert(num_queues
> 0);
682 VkQueueFamilyProperties
*props
= malloc(sizeof(*props
) * num_queues
);
683 vkGetPhysicalDeviceQueueFamilyProperties(pdev
, &num_queues
, props
);
685 for (uint32_t i
= 0; i
< num_queues
; i
++) {
686 if (props
[i
].queueFlags
& VK_QUEUE_GRAPHICS_BIT
) {
696 zink_flush_frontbuffer(struct pipe_screen
*pscreen
,
697 struct pipe_resource
*pres
,
698 unsigned level
, unsigned layer
,
699 void *winsys_drawable_handle
,
700 struct pipe_box
*sub_box
)
702 struct zink_screen
*screen
= zink_screen(pscreen
);
703 struct sw_winsys
*winsys
= screen
->winsys
;
704 struct zink_resource
*res
= zink_resource(pres
);
708 void *map
= winsys
->displaytarget_map(winsys
, res
->dt
, 0);
711 VkImageSubresource isr
= {};
712 isr
.aspectMask
= res
->aspect
;
713 isr
.mipLevel
= level
;
714 isr
.arrayLayer
= layer
;
715 VkSubresourceLayout layout
;
716 vkGetImageSubresourceLayout(screen
->dev
, res
->image
, &isr
, &layout
);
719 VkResult result
= vkMapMemory(screen
->dev
, res
->mem
, res
->offset
, res
->size
, 0, &ptr
);
720 if (result
!= VK_SUCCESS
) {
721 debug_printf("failed to map memory for display\n");
724 for (int i
= 0; i
< pres
->height0
; ++i
) {
725 uint8_t *src
= (uint8_t *)ptr
+ i
* layout
.rowPitch
;
726 uint8_t *dst
= (uint8_t *)map
+ i
* res
->dt_stride
;
727 memcpy(dst
, src
, res
->dt_stride
);
729 vkUnmapMemory(screen
->dev
, res
->mem
);
732 winsys
->displaytarget_unmap(winsys
, res
->dt
);
736 winsys
->displaytarget_display(winsys
, res
->dt
, winsys_drawable_handle
, sub_box
);
739 static struct pipe_screen
*
740 zink_internal_create_screen(struct sw_winsys
*winsys
, int fd
)
742 struct zink_screen
*screen
= CALLOC_STRUCT(zink_screen
);
746 zink_debug
= debug_get_option_zink_debug();
748 screen
->instance
= create_instance();
749 screen
->pdev
= choose_pdev(screen
->instance
);
750 screen
->gfx_queue
= find_gfx_queue(screen
->pdev
);
752 vkGetPhysicalDeviceProperties(screen
->pdev
, &screen
->props
);
753 vkGetPhysicalDeviceFeatures(screen
->pdev
, &screen
->feats
);
754 vkGetPhysicalDeviceMemoryProperties(screen
->pdev
, &screen
->mem_props
);
756 uint32_t num_extensions
= 0;
757 if (vkEnumerateDeviceExtensionProperties(screen
->pdev
, NULL
,
758 &num_extensions
, NULL
) == VK_SUCCESS
&& num_extensions
> 0) {
759 VkExtensionProperties
*extensions
= MALLOC(sizeof(VkExtensionProperties
) *
762 vkEnumerateDeviceExtensionProperties(screen
->pdev
, NULL
,
763 &num_extensions
, extensions
);
765 for (uint32_t i
= 0; i
< num_extensions
; ++i
) {
766 if (!strcmp(extensions
[i
].extensionName
,
767 VK_KHR_MAINTENANCE1_EXTENSION_NAME
))
768 screen
->have_VK_KHR_maintenance1
= true;
774 VkDeviceQueueCreateInfo qci
= {};
776 qci
.sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO
;
777 qci
.queueFamilyIndex
= screen
->gfx_queue
;
779 qci
.pQueuePriorities
= &dummy
;
781 VkDeviceCreateInfo dci
= {};
782 dci
.sType
= VK_STRUCTURE_TYPE_DEVICE_CREATE_INFO
;
783 dci
.queueCreateInfoCount
= 1;
784 dci
.pQueueCreateInfos
= &qci
;
785 dci
.pEnabledFeatures
= &screen
->feats
;
786 const char *extensions
[] = {
787 VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
788 VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME
,
789 VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
791 dci
.ppEnabledExtensionNames
= extensions
;
792 dci
.enabledExtensionCount
= ARRAY_SIZE(extensions
);
793 if (vkCreateDevice(screen
->pdev
, &dci
, NULL
, &screen
->dev
) != VK_SUCCESS
)
796 screen
->winsys
= winsys
;
798 screen
->base
.get_name
= zink_get_name
;
799 screen
->base
.get_vendor
= zink_get_vendor
;
800 screen
->base
.get_device_vendor
= zink_get_device_vendor
;
801 screen
->base
.get_param
= zink_get_param
;
802 screen
->base
.get_paramf
= zink_get_paramf
;
803 screen
->base
.get_shader_param
= zink_get_shader_param
;
804 screen
->base
.get_compiler_options
= zink_get_compiler_options
;
805 screen
->base
.is_format_supported
= zink_is_format_supported
;
806 screen
->base
.context_create
= zink_context_create
;
807 screen
->base
.flush_frontbuffer
= zink_flush_frontbuffer
;
808 screen
->base
.destroy
= zink_destroy_screen
;
810 zink_screen_resource_init(&screen
->base
);
811 zink_screen_fence_init(&screen
->base
);
813 slab_create_parent(&screen
->transfer_pool
, sizeof(struct zink_transfer
), 16);
815 return &screen
->base
;
823 zink_create_screen(struct sw_winsys
*winsys
)
825 return zink_internal_create_screen(winsys
, -1);
829 zink_drm_create_screen(int fd
)
831 return zink_internal_create_screen(NULL
, fd
);