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[mesa.git] / src / gallium / include / pipe / p_defines.h
1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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26 **************************************************************************/
27
28 #ifndef PIPE_DEFINES_H
29 #define PIPE_DEFINES_H
30
31 #include "p_compiler.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /**
38 * Gallium error codes.
39 *
40 * - A zero value always means success.
41 * - A negative value always means failure.
42 * - The meaning of a positive value is function dependent.
43 */
44 enum pipe_error
45 {
46 PIPE_OK = 0,
47 PIPE_ERROR = -1, /**< Generic error */
48 PIPE_ERROR_BAD_INPUT = -2,
49 PIPE_ERROR_OUT_OF_MEMORY = -3,
50 PIPE_ERROR_RETRY = -4
51 /* TODO */
52 };
53
54 enum pipe_blendfactor {
55 PIPE_BLENDFACTOR_ONE = 1,
56 PIPE_BLENDFACTOR_SRC_COLOR,
57 PIPE_BLENDFACTOR_SRC_ALPHA,
58 PIPE_BLENDFACTOR_DST_ALPHA,
59 PIPE_BLENDFACTOR_DST_COLOR,
60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE,
61 PIPE_BLENDFACTOR_CONST_COLOR,
62 PIPE_BLENDFACTOR_CONST_ALPHA,
63 PIPE_BLENDFACTOR_SRC1_COLOR,
64 PIPE_BLENDFACTOR_SRC1_ALPHA,
65
66 PIPE_BLENDFACTOR_ZERO = 0x11,
67 PIPE_BLENDFACTOR_INV_SRC_COLOR,
68 PIPE_BLENDFACTOR_INV_SRC_ALPHA,
69 PIPE_BLENDFACTOR_INV_DST_ALPHA,
70 PIPE_BLENDFACTOR_INV_DST_COLOR,
71
72 PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17,
73 PIPE_BLENDFACTOR_INV_CONST_ALPHA,
74 PIPE_BLENDFACTOR_INV_SRC1_COLOR,
75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA,
76 };
77
78 enum pipe_blend_func {
79 PIPE_BLEND_ADD,
80 PIPE_BLEND_SUBTRACT,
81 PIPE_BLEND_REVERSE_SUBTRACT,
82 PIPE_BLEND_MIN,
83 PIPE_BLEND_MAX,
84 };
85
86 enum pipe_logicop {
87 PIPE_LOGICOP_CLEAR,
88 PIPE_LOGICOP_NOR,
89 PIPE_LOGICOP_AND_INVERTED,
90 PIPE_LOGICOP_COPY_INVERTED,
91 PIPE_LOGICOP_AND_REVERSE,
92 PIPE_LOGICOP_INVERT,
93 PIPE_LOGICOP_XOR,
94 PIPE_LOGICOP_NAND,
95 PIPE_LOGICOP_AND,
96 PIPE_LOGICOP_EQUIV,
97 PIPE_LOGICOP_NOOP,
98 PIPE_LOGICOP_OR_INVERTED,
99 PIPE_LOGICOP_COPY,
100 PIPE_LOGICOP_OR_REVERSE,
101 PIPE_LOGICOP_OR,
102 PIPE_LOGICOP_SET,
103 };
104
105 #define PIPE_MASK_R 0x1
106 #define PIPE_MASK_G 0x2
107 #define PIPE_MASK_B 0x4
108 #define PIPE_MASK_A 0x8
109 #define PIPE_MASK_RGBA 0xf
110 #define PIPE_MASK_Z 0x10
111 #define PIPE_MASK_S 0x20
112 #define PIPE_MASK_ZS 0x30
113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
114
115
116 /**
117 * Inequality functions. Used for depth test, stencil compare, alpha
118 * test, shadow compare, etc.
119 */
120 enum pipe_compare_func {
121 PIPE_FUNC_NEVER,
122 PIPE_FUNC_LESS,
123 PIPE_FUNC_EQUAL,
124 PIPE_FUNC_LEQUAL,
125 PIPE_FUNC_GREATER,
126 PIPE_FUNC_NOTEQUAL,
127 PIPE_FUNC_GEQUAL,
128 PIPE_FUNC_ALWAYS,
129 };
130
131 /** Polygon fill mode */
132 enum {
133 PIPE_POLYGON_MODE_FILL,
134 PIPE_POLYGON_MODE_LINE,
135 PIPE_POLYGON_MODE_POINT,
136 PIPE_POLYGON_MODE_FILL_RECTANGLE,
137 };
138
139 /** Polygon face specification, eg for culling */
140 #define PIPE_FACE_NONE 0
141 #define PIPE_FACE_FRONT 1
142 #define PIPE_FACE_BACK 2
143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
144
145 /** Stencil ops */
146 enum pipe_stencil_op {
147 PIPE_STENCIL_OP_KEEP,
148 PIPE_STENCIL_OP_ZERO,
149 PIPE_STENCIL_OP_REPLACE,
150 PIPE_STENCIL_OP_INCR,
151 PIPE_STENCIL_OP_DECR,
152 PIPE_STENCIL_OP_INCR_WRAP,
153 PIPE_STENCIL_OP_DECR_WRAP,
154 PIPE_STENCIL_OP_INVERT,
155 };
156
157 /** Texture types.
158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
159 */
160 enum pipe_texture_target
161 {
162 PIPE_BUFFER,
163 PIPE_TEXTURE_1D,
164 PIPE_TEXTURE_2D,
165 PIPE_TEXTURE_3D,
166 PIPE_TEXTURE_CUBE,
167 PIPE_TEXTURE_RECT,
168 PIPE_TEXTURE_1D_ARRAY,
169 PIPE_TEXTURE_2D_ARRAY,
170 PIPE_TEXTURE_CUBE_ARRAY,
171 PIPE_MAX_TEXTURE_TYPES,
172 };
173
174 enum pipe_tex_face {
175 PIPE_TEX_FACE_POS_X,
176 PIPE_TEX_FACE_NEG_X,
177 PIPE_TEX_FACE_POS_Y,
178 PIPE_TEX_FACE_NEG_Y,
179 PIPE_TEX_FACE_POS_Z,
180 PIPE_TEX_FACE_NEG_Z,
181 PIPE_TEX_FACE_MAX,
182 };
183
184 enum pipe_tex_wrap {
185 PIPE_TEX_WRAP_REPEAT,
186 PIPE_TEX_WRAP_CLAMP,
187 PIPE_TEX_WRAP_CLAMP_TO_EDGE,
188 PIPE_TEX_WRAP_CLAMP_TO_BORDER,
189 PIPE_TEX_WRAP_MIRROR_REPEAT,
190 PIPE_TEX_WRAP_MIRROR_CLAMP,
191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE,
192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER,
193 };
194
195 /** Between mipmaps, ie mipfilter */
196 enum pipe_tex_mipfilter {
197 PIPE_TEX_MIPFILTER_NEAREST,
198 PIPE_TEX_MIPFILTER_LINEAR,
199 PIPE_TEX_MIPFILTER_NONE,
200 };
201
202 /** Within a mipmap, ie min/mag filter */
203 enum pipe_tex_filter {
204 PIPE_TEX_FILTER_NEAREST,
205 PIPE_TEX_FILTER_LINEAR,
206 };
207
208 enum pipe_tex_compare {
209 PIPE_TEX_COMPARE_NONE,
210 PIPE_TEX_COMPARE_R_TO_TEXTURE,
211 };
212
213 /**
214 * Clear buffer bits
215 */
216 #define PIPE_CLEAR_DEPTH (1 << 0)
217 #define PIPE_CLEAR_STENCIL (1 << 1)
218 #define PIPE_CLEAR_COLOR0 (1 << 2)
219 #define PIPE_CLEAR_COLOR1 (1 << 3)
220 #define PIPE_CLEAR_COLOR2 (1 << 4)
221 #define PIPE_CLEAR_COLOR3 (1 << 5)
222 #define PIPE_CLEAR_COLOR4 (1 << 6)
223 #define PIPE_CLEAR_COLOR5 (1 << 7)
224 #define PIPE_CLEAR_COLOR6 (1 << 8)
225 #define PIPE_CLEAR_COLOR7 (1 << 9)
226 /** Combined flags */
227 /** All color buffers currently bound */
228 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
229 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
230 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
231 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
232 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
233
234 /**
235 * Transfer object usage flags
236 */
237 enum pipe_transfer_usage
238 {
239 /**
240 * Resource contents read back (or accessed directly) at transfer
241 * create time.
242 */
243 PIPE_TRANSFER_READ = (1 << 0),
244
245 /**
246 * Resource contents will be written back at transfer_unmap
247 * time (or modified as a result of being accessed directly).
248 */
249 PIPE_TRANSFER_WRITE = (1 << 1),
250
251 /**
252 * Read/modify/write
253 */
254 PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE,
255
256 /**
257 * The transfer should map the texture storage directly. The driver may
258 * return NULL if that isn't possible, and the state tracker needs to cope
259 * with that and use an alternative path without this flag.
260 *
261 * E.g. the state tracker could have a simpler path which maps textures and
262 * does read/modify/write cycles on them directly, and a more complicated
263 * path which uses minimal read and write transfers.
264 */
265 PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
266
267 /**
268 * Discards the memory within the mapped region.
269 *
270 * It should not be used with PIPE_TRANSFER_READ.
271 *
272 * See also:
273 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
274 */
275 PIPE_TRANSFER_DISCARD_RANGE = (1 << 8),
276
277 /**
278 * Fail if the resource cannot be mapped immediately.
279 *
280 * See also:
281 * - Direct3D's D3DLOCK_DONOTWAIT flag.
282 * - Mesa's MESA_MAP_NOWAIT_BIT flag.
283 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
284 */
285 PIPE_TRANSFER_DONTBLOCK = (1 << 9),
286
287 /**
288 * Do not attempt to synchronize pending operations on the resource when mapping.
289 *
290 * It should not be used with PIPE_TRANSFER_READ.
291 *
292 * See also:
293 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
294 * - Direct3D's D3DLOCK_NOOVERWRITE flag.
295 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
296 */
297 PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
298
299 /**
300 * Written ranges will be notified later with
301 * pipe_context::transfer_flush_region.
302 *
303 * It should not be used with PIPE_TRANSFER_READ.
304 *
305 * See also:
306 * - pipe_context::transfer_flush_region
307 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
308 */
309 PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11),
310
311 /**
312 * Discards all memory backing the resource.
313 *
314 * It should not be used with PIPE_TRANSFER_READ.
315 *
316 * This is equivalent to:
317 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
318 * - BufferData(NULL) on a GL buffer
319 * - Direct3D's D3DLOCK_DISCARD flag.
320 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
321 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
322 * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
323 */
324 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12),
325
326 /**
327 * Allows the resource to be used for rendering while mapped.
328 *
329 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
330 * the resource.
331 *
332 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
333 * must be called to ensure the device can see what the CPU has written.
334 */
335 PIPE_TRANSFER_PERSISTENT = (1 << 13),
336
337 /**
338 * If PERSISTENT is set, this ensures any writes done by the device are
339 * immediately visible to the CPU and vice versa.
340 *
341 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
342 * the resource.
343 */
344 PIPE_TRANSFER_COHERENT = (1 << 14)
345 };
346
347 /**
348 * Flags for the flush function.
349 */
350 enum pipe_flush_flags
351 {
352 PIPE_FLUSH_END_OF_FRAME = (1 << 0),
353 PIPE_FLUSH_DEFERRED = (1 << 1),
354 PIPE_FLUSH_FENCE_FD = (1 << 2),
355 };
356
357 /**
358 * Flags for pipe_context::dump_debug_state.
359 */
360 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0)
361
362 /**
363 * Create a compute-only context. Use in pipe_screen::context_create.
364 * This disables draw, blit, and clear*, render_condition, and other graphics
365 * functions. Interop with other graphics contexts is still allowed.
366 * This allows scheduling jobs on a compute-only hardware command queue that
367 * can run in parallel with graphics without stalling it.
368 */
369 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0)
370
371 /**
372 * Gather debug information and expect that pipe_context::dump_debug_state
373 * will be called. Use in pipe_screen::context_create.
374 */
375 #define PIPE_CONTEXT_DEBUG (1 << 1)
376
377 /**
378 * Whether out-of-bounds shader loads must return zero and out-of-bounds
379 * shader stores must be dropped.
380 */
381 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
382
383 /**
384 * Prefer threaded pipe_context. It also implies that video codec functions
385 * will not be used. (they will be either no-ops or NULL when threading is
386 * enabled)
387 */
388 #define PIPE_CONTEXT_PREFER_THREADED (1 << 3)
389
390
391 /**
392 * Flags for pipe_context::memory_barrier.
393 */
394 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0)
395 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1)
396 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2)
397 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3)
398 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4)
399 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5)
400 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6)
401 #define PIPE_BARRIER_TEXTURE (1 << 7)
402 #define PIPE_BARRIER_IMAGE (1 << 8)
403 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9)
404 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10)
405 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
406 #define PIPE_BARRIER_ALL ((1 << 12) - 1)
407
408 /**
409 * Flags for pipe_context::texture_barrier.
410 */
411 #define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0)
412 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1)
413
414 /**
415 * Resource binding flags -- state tracker must specify in advance all
416 * the ways a resource might be used.
417 */
418 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */
419 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */
420 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */
421 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */
422 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */
423 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */
424 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */
425 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */
426 /* gap */
427 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */
428 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */
429 #define PIPE_BIND_CUSTOM (1 << 12) /* state-tracker/winsys usages */
430 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */
431 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */
432 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */
433 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */
434 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */
435 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */
436
437 /**
438 * The first two flags above were previously part of the amorphous
439 * TEXTURE_USAGE, most of which are now descriptions of the ways a
440 * particular texture can be bound to the gallium pipeline. The two flags
441 * below do not fit within that and probably need to be migrated to some
442 * other place.
443 *
444 * It seems like scanout is used by the Xorg state tracker to ask for
445 * a texture suitable for actual scanout (hence the name), which
446 * implies extra layout constraints on some hardware. It may also
447 * have some special meaning regarding mouse cursor images.
448 *
449 * The shared flag is quite underspecified, but certainly isn't a
450 * binding flag - it seems more like a message to the winsys to create
451 * a shareable allocation.
452 *
453 * The third flag has been added to be able to force textures to be created
454 * in linear mode (no tiling).
455 */
456 #define PIPE_BIND_SCANOUT (1 << 19) /* */
457 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */
458 #define PIPE_BIND_LINEAR (1 << 21)
459
460
461 /**
462 * Flags for the driver about resource behaviour:
463 */
464 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
465 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
466 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
467 #define PIPE_RESOURCE_FLAG_SPARSE (1 << 3)
468 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
469 #define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
470
471 /**
472 * Hint about the expected lifecycle of a resource.
473 * Sorted according to GPU vs CPU access.
474 */
475 enum pipe_resource_usage {
476 PIPE_USAGE_DEFAULT, /* fast GPU access */
477 PIPE_USAGE_IMMUTABLE, /* fast GPU access, immutable */
478 PIPE_USAGE_DYNAMIC, /* uploaded data is used multiple times */
479 PIPE_USAGE_STREAM, /* uploaded data is used once */
480 PIPE_USAGE_STAGING, /* fast CPU access */
481 };
482
483 /**
484 * Shaders
485 */
486 enum pipe_shader_type {
487 PIPE_SHADER_VERTEX,
488 PIPE_SHADER_FRAGMENT,
489 PIPE_SHADER_GEOMETRY,
490 PIPE_SHADER_TESS_CTRL,
491 PIPE_SHADER_TESS_EVAL,
492 PIPE_SHADER_COMPUTE,
493 PIPE_SHADER_TYPES,
494 };
495
496 /**
497 * Primitive types:
498 */
499 enum pipe_prim_type {
500 PIPE_PRIM_POINTS,
501 PIPE_PRIM_LINES,
502 PIPE_PRIM_LINE_LOOP,
503 PIPE_PRIM_LINE_STRIP,
504 PIPE_PRIM_TRIANGLES,
505 PIPE_PRIM_TRIANGLE_STRIP,
506 PIPE_PRIM_TRIANGLE_FAN,
507 PIPE_PRIM_QUADS,
508 PIPE_PRIM_QUAD_STRIP,
509 PIPE_PRIM_POLYGON,
510 PIPE_PRIM_LINES_ADJACENCY,
511 PIPE_PRIM_LINE_STRIP_ADJACENCY,
512 PIPE_PRIM_TRIANGLES_ADJACENCY,
513 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY,
514 PIPE_PRIM_PATCHES,
515 PIPE_PRIM_MAX,
516 };
517
518 /**
519 * Tessellator spacing types
520 */
521 enum pipe_tess_spacing {
522 PIPE_TESS_SPACING_FRACTIONAL_ODD,
523 PIPE_TESS_SPACING_FRACTIONAL_EVEN,
524 PIPE_TESS_SPACING_EQUAL,
525 };
526
527 /**
528 * Query object types
529 */
530 enum pipe_query_type {
531 PIPE_QUERY_OCCLUSION_COUNTER,
532 PIPE_QUERY_OCCLUSION_PREDICATE,
533 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE,
534 PIPE_QUERY_TIMESTAMP,
535 PIPE_QUERY_TIMESTAMP_DISJOINT,
536 PIPE_QUERY_TIME_ELAPSED,
537 PIPE_QUERY_PRIMITIVES_GENERATED,
538 PIPE_QUERY_PRIMITIVES_EMITTED,
539 PIPE_QUERY_SO_STATISTICS,
540 PIPE_QUERY_SO_OVERFLOW_PREDICATE,
541 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE,
542 PIPE_QUERY_GPU_FINISHED,
543 PIPE_QUERY_PIPELINE_STATISTICS,
544 PIPE_QUERY_TYPES,
545 /* start of driver queries, see pipe_screen::get_driver_query_info */
546 PIPE_QUERY_DRIVER_SPECIFIC = 256,
547 };
548
549 /**
550 * Conditional rendering modes
551 */
552 enum pipe_render_cond_flag {
553 PIPE_RENDER_COND_WAIT,
554 PIPE_RENDER_COND_NO_WAIT,
555 PIPE_RENDER_COND_BY_REGION_WAIT,
556 PIPE_RENDER_COND_BY_REGION_NO_WAIT,
557 };
558
559 /**
560 * Point sprite coord modes
561 */
562 enum pipe_sprite_coord_mode {
563 PIPE_SPRITE_COORD_UPPER_LEFT,
564 PIPE_SPRITE_COORD_LOWER_LEFT,
565 };
566
567 /**
568 * Texture & format swizzles
569 */
570 enum pipe_swizzle {
571 PIPE_SWIZZLE_X,
572 PIPE_SWIZZLE_Y,
573 PIPE_SWIZZLE_Z,
574 PIPE_SWIZZLE_W,
575 PIPE_SWIZZLE_0,
576 PIPE_SWIZZLE_1,
577 PIPE_SWIZZLE_NONE,
578 PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */
579 };
580
581 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
582
583
584 /**
585 * Device reset status.
586 */
587 enum pipe_reset_status
588 {
589 PIPE_NO_RESET,
590 PIPE_GUILTY_CONTEXT_RESET,
591 PIPE_INNOCENT_CONTEXT_RESET,
592 PIPE_UNKNOWN_CONTEXT_RESET,
593 };
594
595
596 /**
597 * resource_get_handle flags.
598 */
599 /* Requires pipe_context::flush_resource before external use. */
600 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
601 /* Expected external use of the resource: */
602 #define PIPE_HANDLE_USAGE_READ (1 << 1)
603 #define PIPE_HANDLE_USAGE_WRITE (1 << 2)
604 #define PIPE_HANDLE_USAGE_READ_WRITE (PIPE_HANDLE_USAGE_READ | \
605 PIPE_HANDLE_USAGE_WRITE)
606
607 /**
608 * pipe_image_view access flags.
609 */
610 #define PIPE_IMAGE_ACCESS_READ (1 << 0)
611 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1)
612 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
613 PIPE_IMAGE_ACCESS_WRITE)
614
615 /**
616 * Implementation capabilities/limits which are queried through
617 * pipe_screen::get_param()
618 */
619 enum pipe_cap
620 {
621 PIPE_CAP_NPOT_TEXTURES,
622 PIPE_CAP_TWO_SIDED_STENCIL,
623 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS,
624 PIPE_CAP_ANISOTROPIC_FILTER,
625 PIPE_CAP_POINT_SPRITE,
626 PIPE_CAP_MAX_RENDER_TARGETS,
627 PIPE_CAP_OCCLUSION_QUERY,
628 PIPE_CAP_QUERY_TIME_ELAPSED,
629 PIPE_CAP_TEXTURE_SHADOW_MAP,
630 PIPE_CAP_TEXTURE_SWIZZLE,
631 PIPE_CAP_MAX_TEXTURE_2D_LEVELS,
632 PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
633 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
634 PIPE_CAP_TEXTURE_MIRROR_CLAMP,
635 PIPE_CAP_BLEND_EQUATION_SEPARATE,
636 PIPE_CAP_SM3,
637 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
638 PIPE_CAP_PRIMITIVE_RESTART,
639 /** blend enables and write masks per rendertarget */
640 PIPE_CAP_INDEP_BLEND_ENABLE,
641 /** different blend funcs per rendertarget */
642 PIPE_CAP_INDEP_BLEND_FUNC,
643 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
644 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
645 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
646 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
647 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
648 PIPE_CAP_DEPTH_CLIP_DISABLE,
649 PIPE_CAP_SHADER_STENCIL_EXPORT,
650 PIPE_CAP_TGSI_INSTANCEID,
651 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
652 PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
653 PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
654 PIPE_CAP_SEAMLESS_CUBE_MAP,
655 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
656 PIPE_CAP_MIN_TEXEL_OFFSET,
657 PIPE_CAP_MAX_TEXEL_OFFSET,
658 PIPE_CAP_CONDITIONAL_RENDER,
659 PIPE_CAP_TEXTURE_BARRIER,
660 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS,
661 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS,
662 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
663 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
664 PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
665 PIPE_CAP_VERTEX_COLOR_CLAMPED,
666 PIPE_CAP_GLSL_FEATURE_LEVEL,
667 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
668 PIPE_CAP_USER_VERTEX_BUFFERS,
669 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
670 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
671 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
672 PIPE_CAP_COMPUTE,
673 PIPE_CAP_USER_CONSTANT_BUFFERS,
674 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
675 PIPE_CAP_START_INSTANCE,
676 PIPE_CAP_QUERY_TIMESTAMP,
677 PIPE_CAP_TEXTURE_MULTISAMPLE,
678 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
679 PIPE_CAP_CUBE_MAP_ARRAY,
680 PIPE_CAP_TEXTURE_BUFFER_OBJECTS,
681 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT,
682 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY,
683 PIPE_CAP_TGSI_TEXCOORD,
684 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
685 PIPE_CAP_QUERY_PIPELINE_STATISTICS,
686 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
687 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
688 PIPE_CAP_MAX_VIEWPORTS,
689 PIPE_CAP_ENDIANNESS,
690 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES,
691 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT,
692 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES,
693 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
694 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
695 PIPE_CAP_TEXTURE_GATHER_SM5,
696 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
697 PIPE_CAP_FAKE_SW_MSAA,
698 PIPE_CAP_TEXTURE_QUERY_LOD,
699 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
700 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET,
701 PIPE_CAP_SAMPLE_SHADING,
702 PIPE_CAP_TEXTURE_GATHER_OFFSETS,
703 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
704 PIPE_CAP_MAX_VERTEX_STREAMS,
705 PIPE_CAP_DRAW_INDIRECT,
706 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
707 PIPE_CAP_VENDOR_ID,
708 PIPE_CAP_DEVICE_ID,
709 PIPE_CAP_ACCELERATED,
710 PIPE_CAP_VIDEO_MEMORY,
711 PIPE_CAP_UMA,
712 PIPE_CAP_CONDITIONAL_RENDER_INVERTED,
713 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
714 PIPE_CAP_SAMPLER_VIEW_TARGET,
715 PIPE_CAP_CLIP_HALFZ,
716 PIPE_CAP_VERTEXID_NOBASE,
717 PIPE_CAP_POLYGON_OFFSET_CLAMP,
718 PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
719 PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
720 PIPE_CAP_DEVICE_RESET_STATUS_QUERY,
721 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS,
722 PIPE_CAP_TEXTURE_FLOAT_LINEAR,
723 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
724 PIPE_CAP_DEPTH_BOUNDS_TEST,
725 PIPE_CAP_TGSI_TXQS,
726 PIPE_CAP_FORCE_PERSAMPLE_INTERP,
727 PIPE_CAP_SHAREABLE_SHADERS,
728 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
729 PIPE_CAP_CLEAR_TEXTURE,
730 PIPE_CAP_DRAW_PARAMETERS,
731 PIPE_CAP_TGSI_PACK_HALF_FLOAT,
732 PIPE_CAP_MULTI_DRAW_INDIRECT,
733 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS,
734 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
735 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
736 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
737 PIPE_CAP_INVALIDATE_BUFFER,
738 PIPE_CAP_GENERATE_MIPMAP,
739 PIPE_CAP_STRING_MARKER,
740 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS,
741 PIPE_CAP_QUERY_BUFFER_OBJECT,
742 PIPE_CAP_QUERY_MEMORY_INFO,
743 PIPE_CAP_PCI_GROUP,
744 PIPE_CAP_PCI_BUS,
745 PIPE_CAP_PCI_DEVICE,
746 PIPE_CAP_PCI_FUNCTION,
747 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT,
748 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR,
749 PIPE_CAP_CULL_DISTANCE,
750 PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES,
751 PIPE_CAP_TGSI_VOTE,
752 PIPE_CAP_MAX_WINDOW_RECTANGLES,
753 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
754 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
755 PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
756 PIPE_CAP_TGSI_ARRAY_COMPONENTS,
757 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
758 PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
759 PIPE_CAP_NATIVE_FENCE_FD,
760 PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
761 PIPE_CAP_TGSI_FS_FBFETCH,
762 PIPE_CAP_TGSI_MUL_ZERO_WINS,
763 PIPE_CAP_DOUBLES,
764 PIPE_CAP_INT64,
765 PIPE_CAP_INT64_DIVMOD,
766 PIPE_CAP_TGSI_TEX_TXF_LZ,
767 PIPE_CAP_TGSI_CLOCK,
768 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
769 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE,
770 PIPE_CAP_TGSI_BALLOT,
771 PIPE_CAP_TGSI_TES_LAYER_VIEWPORT,
772 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX,
773 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION,
774 PIPE_CAP_POST_DEPTH_COVERAGE,
775 PIPE_CAP_BINDLESS_TEXTURE,
776 PIPE_CAP_NIR_SAMPLERS_AS_DEREF,
777 PIPE_CAP_QUERY_SO_OVERFLOW,
778 PIPE_CAP_MEMOBJ,
779 PIPE_CAP_LOAD_CONSTBUF,
780 };
781
782 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
783 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
784
785 enum pipe_endian
786 {
787 PIPE_ENDIAN_LITTLE = 0,
788 PIPE_ENDIAN_BIG = 1,
789 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
790 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE
791 #elif defined(PIPE_ARCH_BIG_ENDIAN)
792 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG
793 #endif
794 };
795
796 /**
797 * Implementation limits which are queried through
798 * pipe_screen::get_paramf()
799 */
800 enum pipe_capf
801 {
802 PIPE_CAPF_MAX_LINE_WIDTH,
803 PIPE_CAPF_MAX_LINE_WIDTH_AA,
804 PIPE_CAPF_MAX_POINT_WIDTH,
805 PIPE_CAPF_MAX_POINT_WIDTH_AA,
806 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
807 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
808 PIPE_CAPF_GUARD_BAND_LEFT,
809 PIPE_CAPF_GUARD_BAND_TOP,
810 PIPE_CAPF_GUARD_BAND_RIGHT,
811 PIPE_CAPF_GUARD_BAND_BOTTOM
812 };
813
814 /** Shader caps not specific to any single stage */
815 enum pipe_shader_cap
816 {
817 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
818 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
819 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
820 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
821 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
822 PIPE_SHADER_CAP_MAX_INPUTS,
823 PIPE_SHADER_CAP_MAX_OUTPUTS,
824 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
825 PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
826 PIPE_SHADER_CAP_MAX_TEMPS,
827 /* boolean caps */
828 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
829 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
830 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
831 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
832 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
833 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
834 PIPE_SHADER_CAP_INTEGERS,
835 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
836 PIPE_SHADER_CAP_PREFERRED_IR,
837 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
838 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
839 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
840 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
841 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
842 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
843 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
844 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
845 PIPE_SHADER_CAP_SUPPORTED_IRS,
846 PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
847 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
848 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
849 };
850
851 /**
852 * Shader intermediate representation.
853 *
854 * Note that if the driver requests something other than TGSI, it must
855 * always be prepared to receive TGSI in addition to its preferred IR.
856 * If the driver requests TGSI as its preferred IR, it will *always*
857 * get TGSI.
858 *
859 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
860 * state trackers that only understand TGSI.
861 */
862 enum pipe_shader_ir
863 {
864 PIPE_SHADER_IR_TGSI = 0,
865 PIPE_SHADER_IR_LLVM,
866 PIPE_SHADER_IR_NATIVE,
867 PIPE_SHADER_IR_NIR,
868 };
869
870 /**
871 * Compute-specific implementation capability. They can be queried
872 * using pipe_screen::get_compute_param.
873 */
874 enum pipe_compute_cap
875 {
876 PIPE_COMPUTE_CAP_ADDRESS_BITS,
877 PIPE_COMPUTE_CAP_IR_TARGET,
878 PIPE_COMPUTE_CAP_GRID_DIMENSION,
879 PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
880 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
881 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
882 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
883 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
884 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
885 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE,
886 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
887 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
888 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
889 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
890 PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
891 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
892 };
893
894 /**
895 * Composite query types
896 */
897
898 /**
899 * Query result for PIPE_QUERY_SO_STATISTICS.
900 */
901 struct pipe_query_data_so_statistics
902 {
903 uint64_t num_primitives_written;
904 uint64_t primitives_storage_needed;
905 };
906
907 /**
908 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
909 */
910 struct pipe_query_data_timestamp_disjoint
911 {
912 uint64_t frequency;
913 boolean disjoint;
914 };
915
916 /**
917 * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
918 */
919 struct pipe_query_data_pipeline_statistics
920 {
921 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */
922 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */
923 uint64_t vs_invocations; /**< Num vertex shader invocations. */
924 uint64_t gs_invocations; /**< Num geometry shader invocations. */
925 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */
926 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */
927 uint64_t c_primitives; /**< Num primitives that were rendered. */
928 uint64_t ps_invocations; /**< Num pixel shader invocations. */
929 uint64_t hs_invocations; /**< Num hull shader invocations. */
930 uint64_t ds_invocations; /**< Num domain shader invocations. */
931 uint64_t cs_invocations; /**< Num compute shader invocations. */
932 };
933
934 /**
935 * For batch queries.
936 */
937 union pipe_numeric_type_union
938 {
939 uint64_t u64;
940 uint32_t u32;
941 float f;
942 };
943
944 /**
945 * Query result (returned by pipe_context::get_query_result).
946 */
947 union pipe_query_result
948 {
949 /* PIPE_QUERY_OCCLUSION_PREDICATE */
950 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */
951 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
952 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */
953 /* PIPE_QUERY_GPU_FINISHED */
954 boolean b;
955
956 /* PIPE_QUERY_OCCLUSION_COUNTER */
957 /* PIPE_QUERY_TIMESTAMP */
958 /* PIPE_QUERY_TIME_ELAPSED */
959 /* PIPE_QUERY_PRIMITIVES_GENERATED */
960 /* PIPE_QUERY_PRIMITIVES_EMITTED */
961 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
962 /* PIPE_DRIVER_QUERY_TYPE_BYTES */
963 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
964 /* PIPE_DRIVER_QUERY_TYPE_HZ */
965 uint64_t u64;
966
967 /* PIPE_DRIVER_QUERY_TYPE_UINT */
968 uint32_t u32;
969
970 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
971 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
972 float f;
973
974 /* PIPE_QUERY_SO_STATISTICS */
975 struct pipe_query_data_so_statistics so_statistics;
976
977 /* PIPE_QUERY_TIMESTAMP_DISJOINT */
978 struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
979
980 /* PIPE_QUERY_PIPELINE_STATISTICS */
981 struct pipe_query_data_pipeline_statistics pipeline_statistics;
982
983 /* batch queries (variable length) */
984 union pipe_numeric_type_union batch[1];
985 };
986
987 enum pipe_query_value_type
988 {
989 PIPE_QUERY_TYPE_I32,
990 PIPE_QUERY_TYPE_U32,
991 PIPE_QUERY_TYPE_I64,
992 PIPE_QUERY_TYPE_U64,
993 };
994
995 union pipe_color_union
996 {
997 float f[4];
998 int i[4];
999 unsigned int ui[4];
1000 };
1001
1002 enum pipe_driver_query_type
1003 {
1004 PIPE_DRIVER_QUERY_TYPE_UINT64,
1005 PIPE_DRIVER_QUERY_TYPE_UINT,
1006 PIPE_DRIVER_QUERY_TYPE_FLOAT,
1007 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE,
1008 PIPE_DRIVER_QUERY_TYPE_BYTES,
1009 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS,
1010 PIPE_DRIVER_QUERY_TYPE_HZ,
1011 PIPE_DRIVER_QUERY_TYPE_DBM,
1012 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE,
1013 PIPE_DRIVER_QUERY_TYPE_VOLTS,
1014 PIPE_DRIVER_QUERY_TYPE_AMPS,
1015 PIPE_DRIVER_QUERY_TYPE_WATTS,
1016 };
1017
1018 /* Whether an average value per frame or a cumulative value should be
1019 * displayed.
1020 */
1021 enum pipe_driver_query_result_type
1022 {
1023 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE,
1024 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE,
1025 };
1026
1027 /**
1028 * Some hardware requires some hardware-specific queries to be submitted
1029 * as batched queries. The corresponding query objects are created using
1030 * create_batch_query, and at most one such query may be active at
1031 * any time.
1032 */
1033 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0)
1034
1035 /* Do not list this query in the HUD. */
1036 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
1037
1038 struct pipe_driver_query_info
1039 {
1040 const char *name;
1041 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
1042 union pipe_numeric_type_union max_value; /* max value that can be returned */
1043 enum pipe_driver_query_type type;
1044 enum pipe_driver_query_result_type result_type;
1045 unsigned group_id;
1046 unsigned flags;
1047 };
1048
1049 struct pipe_driver_query_group_info
1050 {
1051 const char *name;
1052 unsigned max_active_queries;
1053 unsigned num_queries;
1054 };
1055
1056 enum pipe_debug_type
1057 {
1058 PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1,
1059 PIPE_DEBUG_TYPE_ERROR,
1060 PIPE_DEBUG_TYPE_SHADER_INFO,
1061 PIPE_DEBUG_TYPE_PERF_INFO,
1062 PIPE_DEBUG_TYPE_INFO,
1063 PIPE_DEBUG_TYPE_FALLBACK,
1064 PIPE_DEBUG_TYPE_CONFORMANCE,
1065 };
1066
1067 #define PIPE_UUID_SIZE 16
1068
1069 #ifdef __cplusplus
1070 }
1071 #endif
1072
1073 #endif