1 /**************************************************************************
3 * Copyright 2007 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef PIPE_DEFINES_H
29 #define PIPE_DEFINES_H
31 #include "p_compiler.h"
38 * Gallium error codes.
40 * - A zero value always means success.
41 * - A negative value always means failure.
42 * - The meaning of a positive value is function dependent.
47 PIPE_ERROR
= -1, /**< Generic error */
48 PIPE_ERROR_BAD_INPUT
= -2,
49 PIPE_ERROR_OUT_OF_MEMORY
= -3,
54 enum pipe_blendfactor
{
55 PIPE_BLENDFACTOR_ONE
= 1,
56 PIPE_BLENDFACTOR_SRC_COLOR
,
57 PIPE_BLENDFACTOR_SRC_ALPHA
,
58 PIPE_BLENDFACTOR_DST_ALPHA
,
59 PIPE_BLENDFACTOR_DST_COLOR
,
60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
,
61 PIPE_BLENDFACTOR_CONST_COLOR
,
62 PIPE_BLENDFACTOR_CONST_ALPHA
,
63 PIPE_BLENDFACTOR_SRC1_COLOR
,
64 PIPE_BLENDFACTOR_SRC1_ALPHA
,
66 PIPE_BLENDFACTOR_ZERO
= 0x11,
67 PIPE_BLENDFACTOR_INV_SRC_COLOR
,
68 PIPE_BLENDFACTOR_INV_SRC_ALPHA
,
69 PIPE_BLENDFACTOR_INV_DST_ALPHA
,
70 PIPE_BLENDFACTOR_INV_DST_COLOR
,
72 PIPE_BLENDFACTOR_INV_CONST_COLOR
= 0x17,
73 PIPE_BLENDFACTOR_INV_CONST_ALPHA
,
74 PIPE_BLENDFACTOR_INV_SRC1_COLOR
,
75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA
,
78 enum pipe_blend_func
{
81 PIPE_BLEND_REVERSE_SUBTRACT
,
89 PIPE_LOGICOP_AND_INVERTED
,
90 PIPE_LOGICOP_COPY_INVERTED
,
91 PIPE_LOGICOP_AND_REVERSE
,
98 PIPE_LOGICOP_OR_INVERTED
,
100 PIPE_LOGICOP_OR_REVERSE
,
105 #define PIPE_MASK_R 0x1
106 #define PIPE_MASK_G 0x2
107 #define PIPE_MASK_B 0x4
108 #define PIPE_MASK_A 0x8
109 #define PIPE_MASK_RGBA 0xf
110 #define PIPE_MASK_Z 0x10
111 #define PIPE_MASK_S 0x20
112 #define PIPE_MASK_ZS 0x30
113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
117 * Inequality functions. Used for depth test, stencil compare, alpha
118 * test, shadow compare, etc.
120 enum pipe_compare_func
{
131 /** Polygon fill mode */
133 PIPE_POLYGON_MODE_FILL
,
134 PIPE_POLYGON_MODE_LINE
,
135 PIPE_POLYGON_MODE_POINT
,
136 PIPE_POLYGON_MODE_FILL_RECTANGLE
,
139 /** Polygon face specification, eg for culling */
140 #define PIPE_FACE_NONE 0
141 #define PIPE_FACE_FRONT 1
142 #define PIPE_FACE_BACK 2
143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK)
146 enum pipe_stencil_op
{
147 PIPE_STENCIL_OP_KEEP
,
148 PIPE_STENCIL_OP_ZERO
,
149 PIPE_STENCIL_OP_REPLACE
,
150 PIPE_STENCIL_OP_INCR
,
151 PIPE_STENCIL_OP_DECR
,
152 PIPE_STENCIL_OP_INCR_WRAP
,
153 PIPE_STENCIL_OP_DECR_WRAP
,
154 PIPE_STENCIL_OP_INVERT
,
158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D
160 enum pipe_texture_target
168 PIPE_TEXTURE_1D_ARRAY
,
169 PIPE_TEXTURE_2D_ARRAY
,
170 PIPE_TEXTURE_CUBE_ARRAY
,
171 PIPE_MAX_TEXTURE_TYPES
,
185 PIPE_TEX_WRAP_REPEAT
,
187 PIPE_TEX_WRAP_CLAMP_TO_EDGE
,
188 PIPE_TEX_WRAP_CLAMP_TO_BORDER
,
189 PIPE_TEX_WRAP_MIRROR_REPEAT
,
190 PIPE_TEX_WRAP_MIRROR_CLAMP
,
191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
,
192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
,
195 /** Between mipmaps, ie mipfilter */
196 enum pipe_tex_mipfilter
{
197 PIPE_TEX_MIPFILTER_NEAREST
,
198 PIPE_TEX_MIPFILTER_LINEAR
,
199 PIPE_TEX_MIPFILTER_NONE
,
202 /** Within a mipmap, ie min/mag filter */
203 enum pipe_tex_filter
{
204 PIPE_TEX_FILTER_NEAREST
,
205 PIPE_TEX_FILTER_LINEAR
,
208 enum pipe_tex_compare
{
209 PIPE_TEX_COMPARE_NONE
,
210 PIPE_TEX_COMPARE_R_TO_TEXTURE
,
216 #define PIPE_CLEAR_DEPTH (1 << 0)
217 #define PIPE_CLEAR_STENCIL (1 << 1)
218 #define PIPE_CLEAR_COLOR0 (1 << 2)
219 #define PIPE_CLEAR_COLOR1 (1 << 3)
220 #define PIPE_CLEAR_COLOR2 (1 << 4)
221 #define PIPE_CLEAR_COLOR3 (1 << 5)
222 #define PIPE_CLEAR_COLOR4 (1 << 6)
223 #define PIPE_CLEAR_COLOR5 (1 << 7)
224 #define PIPE_CLEAR_COLOR6 (1 << 8)
225 #define PIPE_CLEAR_COLOR7 (1 << 9)
226 /** Combined flags */
227 /** All color buffers currently bound */
228 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \
229 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \
230 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \
231 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7)
232 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)
235 * Transfer object usage flags
237 enum pipe_transfer_usage
240 * Resource contents read back (or accessed directly) at transfer
243 PIPE_TRANSFER_READ
= (1 << 0),
246 * Resource contents will be written back at transfer_unmap
247 * time (or modified as a result of being accessed directly).
249 PIPE_TRANSFER_WRITE
= (1 << 1),
254 PIPE_TRANSFER_READ_WRITE
= PIPE_TRANSFER_READ
| PIPE_TRANSFER_WRITE
,
257 * The transfer should map the texture storage directly. The driver may
258 * return NULL if that isn't possible, and the state tracker needs to cope
259 * with that and use an alternative path without this flag.
261 * E.g. the state tracker could have a simpler path which maps textures and
262 * does read/modify/write cycles on them directly, and a more complicated
263 * path which uses minimal read and write transfers.
265 PIPE_TRANSFER_MAP_DIRECTLY
= (1 << 2),
268 * Discards the memory within the mapped region.
270 * It should not be used with PIPE_TRANSFER_READ.
273 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
275 PIPE_TRANSFER_DISCARD_RANGE
= (1 << 8),
278 * Fail if the resource cannot be mapped immediately.
281 * - Direct3D's D3DLOCK_DONOTWAIT flag.
282 * - Mesa's MESA_MAP_NOWAIT_BIT flag.
283 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
285 PIPE_TRANSFER_DONTBLOCK
= (1 << 9),
288 * Do not attempt to synchronize pending operations on the resource when mapping.
290 * It should not be used with PIPE_TRANSFER_READ.
293 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag.
294 * - Direct3D's D3DLOCK_NOOVERWRITE flag.
295 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
297 PIPE_TRANSFER_UNSYNCHRONIZED
= (1 << 10),
300 * Written ranges will be notified later with
301 * pipe_context::transfer_flush_region.
303 * It should not be used with PIPE_TRANSFER_READ.
306 * - pipe_context::transfer_flush_region
307 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
309 PIPE_TRANSFER_FLUSH_EXPLICIT
= (1 << 11),
312 * Discards all memory backing the resource.
314 * It should not be used with PIPE_TRANSFER_READ.
316 * This is equivalent to:
317 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT
318 * - BufferData(NULL) on a GL buffer
319 * - Direct3D's D3DLOCK_DISCARD flag.
320 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag.
321 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
322 * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
324 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
= (1 << 12),
327 * Allows the resource to be used for rendering while mapped.
329 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating
332 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
333 * must be called to ensure the device can see what the CPU has written.
335 PIPE_TRANSFER_PERSISTENT
= (1 << 13),
338 * If PERSISTENT is set, this ensures any writes done by the device are
339 * immediately visible to the CPU and vice versa.
341 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
344 PIPE_TRANSFER_COHERENT
= (1 << 14)
348 * Flags for the flush function.
350 enum pipe_flush_flags
352 PIPE_FLUSH_END_OF_FRAME
= (1 << 0),
353 PIPE_FLUSH_DEFERRED
= (1 << 1),
354 PIPE_FLUSH_FENCE_FD
= (1 << 2),
355 PIPE_FLUSH_ASYNC
= (1 << 3),
356 PIPE_FLUSH_HINT_FINISH
= (1 << 4),
357 PIPE_FLUSH_TOP_OF_PIPE
= (1 << 5),
358 PIPE_FLUSH_BOTTOM_OF_PIPE
= (1 << 6),
362 * Flags for pipe_context::dump_debug_state.
364 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0)
367 * Create a compute-only context. Use in pipe_screen::context_create.
368 * This disables draw, blit, and clear*, render_condition, and other graphics
369 * functions. Interop with other graphics contexts is still allowed.
370 * This allows scheduling jobs on a compute-only hardware command queue that
371 * can run in parallel with graphics without stalling it.
373 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0)
376 * Gather debug information and expect that pipe_context::dump_debug_state
377 * will be called. Use in pipe_screen::context_create.
379 #define PIPE_CONTEXT_DEBUG (1 << 1)
382 * Whether out-of-bounds shader loads must return zero and out-of-bounds
383 * shader stores must be dropped.
385 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2)
388 * Prefer threaded pipe_context. It also implies that video codec functions
389 * will not be used. (they will be either no-ops or NULL when threading is
392 #define PIPE_CONTEXT_PREFER_THREADED (1 << 3)
395 * Create a high priority context.
397 #define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4)
400 * Create a low priority context.
402 #define PIPE_CONTEXT_LOW_PRIORITY (1 << 5)
404 /** Stop execution if the device is reset. */
405 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6)
408 * Flags for pipe_context::memory_barrier.
410 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0)
411 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1)
412 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2)
413 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3)
414 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4)
415 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5)
416 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6)
417 #define PIPE_BARRIER_TEXTURE (1 << 7)
418 #define PIPE_BARRIER_IMAGE (1 << 8)
419 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9)
420 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10)
421 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
422 #define PIPE_BARRIER_ALL ((1 << 12) - 1)
425 * Flags for pipe_context::texture_barrier.
427 #define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0)
428 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1)
431 * Resource binding flags -- state tracker must specify in advance all
432 * the ways a resource might be used.
434 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */
435 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */
436 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */
437 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */
438 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */
439 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */
440 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */
441 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */
443 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */
444 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */
445 #define PIPE_BIND_CUSTOM (1 << 12) /* state-tracker/winsys usages */
446 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */
447 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */
448 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */
449 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */
450 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */
451 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */
454 * The first two flags above were previously part of the amorphous
455 * TEXTURE_USAGE, most of which are now descriptions of the ways a
456 * particular texture can be bound to the gallium pipeline. The two flags
457 * below do not fit within that and probably need to be migrated to some
460 * It seems like scanout is used by the Xorg state tracker to ask for
461 * a texture suitable for actual scanout (hence the name), which
462 * implies extra layout constraints on some hardware. It may also
463 * have some special meaning regarding mouse cursor images.
465 * The shared flag is quite underspecified, but certainly isn't a
466 * binding flag - it seems more like a message to the winsys to create
467 * a shareable allocation.
469 * The third flag has been added to be able to force textures to be created
470 * in linear mode (no tiling).
472 #define PIPE_BIND_SCANOUT (1 << 19) /* */
473 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */
474 #define PIPE_BIND_LINEAR (1 << 21)
478 * Flags for the driver about resource behaviour:
480 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
481 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
482 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
483 #define PIPE_RESOURCE_FLAG_SPARSE (1 << 3)
484 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
485 #define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
488 * Hint about the expected lifecycle of a resource.
489 * Sorted according to GPU vs CPU access.
491 enum pipe_resource_usage
{
492 PIPE_USAGE_DEFAULT
, /* fast GPU access */
493 PIPE_USAGE_IMMUTABLE
, /* fast GPU access, immutable */
494 PIPE_USAGE_DYNAMIC
, /* uploaded data is used multiple times */
495 PIPE_USAGE_STREAM
, /* uploaded data is used once */
496 PIPE_USAGE_STAGING
, /* fast CPU access */
502 enum pipe_shader_type
{
504 PIPE_SHADER_FRAGMENT
,
505 PIPE_SHADER_GEOMETRY
,
506 PIPE_SHADER_TESS_CTRL
,
507 PIPE_SHADER_TESS_EVAL
,
515 enum pipe_prim_type
{
519 PIPE_PRIM_LINE_STRIP
,
521 PIPE_PRIM_TRIANGLE_STRIP
,
522 PIPE_PRIM_TRIANGLE_FAN
,
524 PIPE_PRIM_QUAD_STRIP
,
526 PIPE_PRIM_LINES_ADJACENCY
,
527 PIPE_PRIM_LINE_STRIP_ADJACENCY
,
528 PIPE_PRIM_TRIANGLES_ADJACENCY
,
529 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
,
535 * Tessellator spacing types
537 enum pipe_tess_spacing
{
538 PIPE_TESS_SPACING_FRACTIONAL_ODD
,
539 PIPE_TESS_SPACING_FRACTIONAL_EVEN
,
540 PIPE_TESS_SPACING_EQUAL
,
546 enum pipe_query_type
{
547 PIPE_QUERY_OCCLUSION_COUNTER
,
548 PIPE_QUERY_OCCLUSION_PREDICATE
,
549 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
,
550 PIPE_QUERY_TIMESTAMP
,
551 PIPE_QUERY_TIMESTAMP_DISJOINT
,
552 PIPE_QUERY_TIME_ELAPSED
,
553 PIPE_QUERY_PRIMITIVES_GENERATED
,
554 PIPE_QUERY_PRIMITIVES_EMITTED
,
555 PIPE_QUERY_SO_STATISTICS
,
556 PIPE_QUERY_SO_OVERFLOW_PREDICATE
,
557 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
,
558 PIPE_QUERY_GPU_FINISHED
,
559 PIPE_QUERY_PIPELINE_STATISTICS
,
561 /* start of driver queries, see pipe_screen::get_driver_query_info */
562 PIPE_QUERY_DRIVER_SPECIFIC
= 256,
566 * Conditional rendering modes
568 enum pipe_render_cond_flag
{
569 PIPE_RENDER_COND_WAIT
,
570 PIPE_RENDER_COND_NO_WAIT
,
571 PIPE_RENDER_COND_BY_REGION_WAIT
,
572 PIPE_RENDER_COND_BY_REGION_NO_WAIT
,
576 * Point sprite coord modes
578 enum pipe_sprite_coord_mode
{
579 PIPE_SPRITE_COORD_UPPER_LEFT
,
580 PIPE_SPRITE_COORD_LOWER_LEFT
,
584 * Texture & format swizzles
594 PIPE_SWIZZLE_MAX
, /**< Number of enums counter (must be last) */
597 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
601 * Device reset status.
603 enum pipe_reset_status
606 PIPE_GUILTY_CONTEXT_RESET
,
607 PIPE_INNOCENT_CONTEXT_RESET
,
608 PIPE_UNKNOWN_CONTEXT_RESET
,
613 * Conservative rasterization modes.
615 enum pipe_conservative_raster_mode
617 PIPE_CONSERVATIVE_RASTER_OFF
,
618 PIPE_CONSERVATIVE_RASTER_POST_SNAP
,
619 PIPE_CONSERVATIVE_RASTER_PRE_SNAP
,
624 * resource_get_handle flags.
626 /* Requires pipe_context::flush_resource before external use. */
627 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
628 /* Expected external use of the resource: */
629 #define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1)
630 #define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2)
633 * pipe_image_view access flags.
635 #define PIPE_IMAGE_ACCESS_READ (1 << 0)
636 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1)
637 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \
638 PIPE_IMAGE_ACCESS_WRITE)
641 * Implementation capabilities/limits which are queried through
642 * pipe_screen::get_param()
646 PIPE_CAP_NPOT_TEXTURES
,
647 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
,
648 PIPE_CAP_ANISOTROPIC_FILTER
,
649 PIPE_CAP_POINT_SPRITE
,
650 PIPE_CAP_MAX_RENDER_TARGETS
,
651 PIPE_CAP_OCCLUSION_QUERY
,
652 PIPE_CAP_QUERY_TIME_ELAPSED
,
653 PIPE_CAP_TEXTURE_SWIZZLE
,
654 PIPE_CAP_MAX_TEXTURE_2D_LEVELS
,
655 PIPE_CAP_MAX_TEXTURE_3D_LEVELS
,
656 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
,
657 PIPE_CAP_TEXTURE_MIRROR_CLAMP
,
658 PIPE_CAP_BLEND_EQUATION_SEPARATE
,
660 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
,
661 PIPE_CAP_PRIMITIVE_RESTART
,
662 /** blend enables and write masks per rendertarget */
663 PIPE_CAP_INDEP_BLEND_ENABLE
,
664 /** different blend funcs per rendertarget */
665 PIPE_CAP_INDEP_BLEND_FUNC
,
666 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
,
667 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
,
668 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
,
669 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
,
670 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
,
671 PIPE_CAP_DEPTH_CLIP_DISABLE
,
672 PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
,
673 PIPE_CAP_SHADER_STENCIL_EXPORT
,
674 PIPE_CAP_TGSI_INSTANCEID
,
675 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
,
676 PIPE_CAP_FRAGMENT_COLOR_CLAMPED
,
677 PIPE_CAP_MIXED_COLORBUFFER_FORMATS
,
678 PIPE_CAP_SEAMLESS_CUBE_MAP
,
679 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
,
680 PIPE_CAP_MIN_TEXEL_OFFSET
,
681 PIPE_CAP_MAX_TEXEL_OFFSET
,
682 PIPE_CAP_CONDITIONAL_RENDER
,
683 PIPE_CAP_TEXTURE_BARRIER
,
684 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
,
685 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
,
686 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
,
687 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
,
688 PIPE_CAP_VERTEX_COLOR_UNCLAMPED
,
689 PIPE_CAP_VERTEX_COLOR_CLAMPED
,
690 PIPE_CAP_GLSL_FEATURE_LEVEL
,
691 PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
,
692 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
,
693 PIPE_CAP_USER_VERTEX_BUFFERS
,
694 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
,
695 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
,
696 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
,
698 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
,
699 PIPE_CAP_START_INSTANCE
,
700 PIPE_CAP_QUERY_TIMESTAMP
,
701 PIPE_CAP_TEXTURE_MULTISAMPLE
,
702 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
,
703 PIPE_CAP_CUBE_MAP_ARRAY
,
704 PIPE_CAP_TEXTURE_BUFFER_OBJECTS
,
705 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
,
706 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
,
707 PIPE_CAP_TGSI_TEXCOORD
,
708 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
,
709 PIPE_CAP_QUERY_PIPELINE_STATISTICS
,
710 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
,
711 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
,
712 PIPE_CAP_MAX_VIEWPORTS
,
714 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
,
715 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
,
716 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
,
717 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
,
718 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
,
719 PIPE_CAP_TEXTURE_GATHER_SM5
,
720 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
,
721 PIPE_CAP_FAKE_SW_MSAA
,
722 PIPE_CAP_TEXTURE_QUERY_LOD
,
723 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
,
724 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
,
725 PIPE_CAP_SAMPLE_SHADING
,
726 PIPE_CAP_TEXTURE_GATHER_OFFSETS
,
727 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
,
728 PIPE_CAP_MAX_VERTEX_STREAMS
,
729 PIPE_CAP_DRAW_INDIRECT
,
730 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
,
733 PIPE_CAP_ACCELERATED
,
734 PIPE_CAP_VIDEO_MEMORY
,
736 PIPE_CAP_CONDITIONAL_RENDER_INVERTED
,
737 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
,
738 PIPE_CAP_SAMPLER_VIEW_TARGET
,
740 PIPE_CAP_VERTEXID_NOBASE
,
741 PIPE_CAP_POLYGON_OFFSET_CLAMP
,
742 PIPE_CAP_MULTISAMPLE_Z_RESOLVE
,
743 PIPE_CAP_RESOURCE_FROM_USER_MEMORY
,
744 PIPE_CAP_DEVICE_RESET_STATUS_QUERY
,
745 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
,
746 PIPE_CAP_TEXTURE_FLOAT_LINEAR
,
747 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
,
748 PIPE_CAP_DEPTH_BOUNDS_TEST
,
750 PIPE_CAP_FORCE_PERSAMPLE_INTERP
,
751 PIPE_CAP_SHAREABLE_SHADERS
,
752 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
,
753 PIPE_CAP_CLEAR_TEXTURE
,
754 PIPE_CAP_DRAW_PARAMETERS
,
755 PIPE_CAP_TGSI_PACK_HALF_FLOAT
,
756 PIPE_CAP_MULTI_DRAW_INDIRECT
,
757 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
,
758 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
,
759 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
,
760 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
,
761 PIPE_CAP_INVALIDATE_BUFFER
,
762 PIPE_CAP_GENERATE_MIPMAP
,
763 PIPE_CAP_STRING_MARKER
,
764 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
,
765 PIPE_CAP_QUERY_BUFFER_OBJECT
,
766 PIPE_CAP_QUERY_MEMORY_INFO
,
770 PIPE_CAP_PCI_FUNCTION
,
771 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
,
772 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
,
773 PIPE_CAP_CULL_DISTANCE
,
774 PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
,
776 PIPE_CAP_MAX_WINDOW_RECTANGLES
,
777 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
,
778 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
,
779 PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
,
780 PIPE_CAP_MIXED_COLOR_DEPTH_BITS
,
781 PIPE_CAP_TGSI_ARRAY_COMPONENTS
,
782 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
,
783 PIPE_CAP_TGSI_CAN_READ_OUTPUTS
,
784 PIPE_CAP_NATIVE_FENCE_FD
,
785 PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
,
786 PIPE_CAP_TGSI_FS_FBFETCH
,
787 PIPE_CAP_TGSI_MUL_ZERO_WINS
,
790 PIPE_CAP_INT64_DIVMOD
,
791 PIPE_CAP_TGSI_TEX_TXF_LZ
,
793 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
,
794 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
,
795 PIPE_CAP_TGSI_BALLOT
,
796 PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
,
797 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
,
798 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
,
799 PIPE_CAP_POST_DEPTH_COVERAGE
,
800 PIPE_CAP_BINDLESS_TEXTURE
,
801 PIPE_CAP_NIR_SAMPLERS_AS_DEREF
,
802 PIPE_CAP_QUERY_SO_OVERFLOW
,
804 PIPE_CAP_LOAD_CONSTBUF
,
805 PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
,
806 PIPE_CAP_TILE_RASTER_ORDER
,
807 PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
,
808 PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
,
809 PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
,
810 PIPE_CAP_CONTEXT_PRIORITY_MASK
,
811 PIPE_CAP_FENCE_SIGNAL
,
812 PIPE_CAP_CONSTBUF0_FLAGS
,
813 PIPE_CAP_PACKED_UNIFORMS
,
814 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
,
815 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
,
816 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
,
817 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
,
818 PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
,
819 PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
,
820 PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
,
821 PIPE_CAP_MAX_GS_INVOCATIONS
,
822 PIPE_CAP_MAX_SHADER_BUFFER_SIZE
,
823 PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
,
824 PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
,
825 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
,
826 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
,
827 PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
,
828 PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
,
832 * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should
833 * return a bitmask of the supported priorities. If the driver does not
834 * support prioritized contexts, it can return 0.
836 * Note that these match __DRI2_RENDER_HAS_CONTEXT_PRIORITY_*
838 #define PIPE_CONTEXT_PRIORITY_LOW (1 << 0)
839 #define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1)
840 #define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2)
842 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
843 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1)
847 PIPE_ENDIAN_LITTLE
= 0,
849 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
850 PIPE_ENDIAN_NATIVE
= PIPE_ENDIAN_LITTLE
851 #elif defined(PIPE_ARCH_BIG_ENDIAN)
852 PIPE_ENDIAN_NATIVE
= PIPE_ENDIAN_BIG
857 * Implementation limits which are queried through
858 * pipe_screen::get_paramf()
862 PIPE_CAPF_MAX_LINE_WIDTH
,
863 PIPE_CAPF_MAX_LINE_WIDTH_AA
,
864 PIPE_CAPF_MAX_POINT_WIDTH
,
865 PIPE_CAPF_MAX_POINT_WIDTH_AA
,
866 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
,
867 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
,
868 PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
,
869 PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
,
870 PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
,
873 /** Shader caps not specific to any single stage */
876 PIPE_SHADER_CAP_MAX_INSTRUCTIONS
, /* if 0, it means the stage is unsupported */
877 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
,
878 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
,
879 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
,
880 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
,
881 PIPE_SHADER_CAP_MAX_INPUTS
,
882 PIPE_SHADER_CAP_MAX_OUTPUTS
,
883 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
,
884 PIPE_SHADER_CAP_MAX_CONST_BUFFERS
,
885 PIPE_SHADER_CAP_MAX_TEMPS
,
887 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
,
888 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
,
889 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
,
890 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
,
891 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
,
892 PIPE_SHADER_CAP_SUBROUTINES
, /* BGNSUB, ENDSUB, CAL, RET */
893 PIPE_SHADER_CAP_INTEGERS
,
894 PIPE_SHADER_CAP_INT64_ATOMICS
,
895 PIPE_SHADER_CAP_FP16
,
896 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
,
897 PIPE_SHADER_CAP_PREFERRED_IR
,
898 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
,
899 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
,
900 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
, /* all rounding modes */
901 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
,
902 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
,
903 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
,
904 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
,
905 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
,
906 PIPE_SHADER_CAP_SUPPORTED_IRS
,
907 PIPE_SHADER_CAP_MAX_SHADER_IMAGES
,
908 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
,
909 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
,
910 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
,
911 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
,
912 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
,
913 PIPE_SHADER_CAP_SCALAR_ISA
,
917 * Shader intermediate representation.
919 * Note that if the driver requests something other than TGSI, it must
920 * always be prepared to receive TGSI in addition to its preferred IR.
921 * If the driver requests TGSI as its preferred IR, it will *always*
924 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with
925 * state trackers that only understand TGSI.
929 PIPE_SHADER_IR_TGSI
= 0,
930 PIPE_SHADER_IR_NATIVE
,
935 * Compute-specific implementation capability. They can be queried
936 * using pipe_screen::get_compute_param.
938 enum pipe_compute_cap
940 PIPE_COMPUTE_CAP_ADDRESS_BITS
,
941 PIPE_COMPUTE_CAP_IR_TARGET
,
942 PIPE_COMPUTE_CAP_GRID_DIMENSION
,
943 PIPE_COMPUTE_CAP_MAX_GRID_SIZE
,
944 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
,
945 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
946 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
,
947 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
,
948 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
,
949 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
,
950 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
951 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
,
952 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
,
953 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
,
954 PIPE_COMPUTE_CAP_SUBGROUP_SIZE
,
955 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
,
959 * Types of parameters for pipe_context::set_context_param.
961 enum pipe_context_param
963 /* A hint for the driver that it should pin its execution threads to
964 * a group of cores sharing a specific L3 cache if the CPU has multiple
965 * L3 caches. This is needed for good multithreading performance on
966 * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
967 * any internal threads or don't run on affected CPUs can ignore this.
969 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
,
973 * Composite query types
977 * Query result for PIPE_QUERY_SO_STATISTICS.
979 struct pipe_query_data_so_statistics
981 uint64_t num_primitives_written
;
982 uint64_t primitives_storage_needed
;
986 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
988 struct pipe_query_data_timestamp_disjoint
995 * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
997 struct pipe_query_data_pipeline_statistics
999 uint64_t ia_vertices
; /**< Num vertices read by the vertex fetcher. */
1000 uint64_t ia_primitives
; /**< Num primitives read by the vertex fetcher. */
1001 uint64_t vs_invocations
; /**< Num vertex shader invocations. */
1002 uint64_t gs_invocations
; /**< Num geometry shader invocations. */
1003 uint64_t gs_primitives
; /**< Num primitives output by a geometry shader. */
1004 uint64_t c_invocations
; /**< Num primitives sent to the rasterizer. */
1005 uint64_t c_primitives
; /**< Num primitives that were rendered. */
1006 uint64_t ps_invocations
; /**< Num pixel shader invocations. */
1007 uint64_t hs_invocations
; /**< Num hull shader invocations. */
1008 uint64_t ds_invocations
; /**< Num domain shader invocations. */
1009 uint64_t cs_invocations
; /**< Num compute shader invocations. */
1013 * For batch queries.
1015 union pipe_numeric_type_union
1023 * Query result (returned by pipe_context::get_query_result).
1025 union pipe_query_result
1027 /* PIPE_QUERY_OCCLUSION_PREDICATE */
1028 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */
1029 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
1030 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */
1031 /* PIPE_QUERY_GPU_FINISHED */
1034 /* PIPE_QUERY_OCCLUSION_COUNTER */
1035 /* PIPE_QUERY_TIMESTAMP */
1036 /* PIPE_QUERY_TIME_ELAPSED */
1037 /* PIPE_QUERY_PRIMITIVES_GENERATED */
1038 /* PIPE_QUERY_PRIMITIVES_EMITTED */
1039 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */
1040 /* PIPE_DRIVER_QUERY_TYPE_BYTES */
1041 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */
1042 /* PIPE_DRIVER_QUERY_TYPE_HZ */
1045 /* PIPE_DRIVER_QUERY_TYPE_UINT */
1048 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */
1049 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */
1052 /* PIPE_QUERY_SO_STATISTICS */
1053 struct pipe_query_data_so_statistics so_statistics
;
1055 /* PIPE_QUERY_TIMESTAMP_DISJOINT */
1056 struct pipe_query_data_timestamp_disjoint timestamp_disjoint
;
1058 /* PIPE_QUERY_PIPELINE_STATISTICS */
1059 struct pipe_query_data_pipeline_statistics pipeline_statistics
;
1061 /* batch queries (variable length) */
1062 union pipe_numeric_type_union batch
[1];
1065 enum pipe_query_value_type
1067 PIPE_QUERY_TYPE_I32
,
1068 PIPE_QUERY_TYPE_U32
,
1069 PIPE_QUERY_TYPE_I64
,
1070 PIPE_QUERY_TYPE_U64
,
1073 union pipe_color_union
1080 enum pipe_driver_query_type
1082 PIPE_DRIVER_QUERY_TYPE_UINT64
,
1083 PIPE_DRIVER_QUERY_TYPE_UINT
,
1084 PIPE_DRIVER_QUERY_TYPE_FLOAT
,
1085 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE
,
1086 PIPE_DRIVER_QUERY_TYPE_BYTES
,
1087 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
,
1088 PIPE_DRIVER_QUERY_TYPE_HZ
,
1089 PIPE_DRIVER_QUERY_TYPE_DBM
,
1090 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE
,
1091 PIPE_DRIVER_QUERY_TYPE_VOLTS
,
1092 PIPE_DRIVER_QUERY_TYPE_AMPS
,
1093 PIPE_DRIVER_QUERY_TYPE_WATTS
,
1096 /* Whether an average value per frame or a cumulative value should be
1099 enum pipe_driver_query_result_type
1101 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE
,
1102 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE
,
1106 * Some hardware requires some hardware-specific queries to be submitted
1107 * as batched queries. The corresponding query objects are created using
1108 * create_batch_query, and at most one such query may be active at
1111 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0)
1113 /* Do not list this query in the HUD. */
1114 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1)
1116 struct pipe_driver_query_info
1119 unsigned query_type
; /* PIPE_QUERY_DRIVER_SPECIFIC + i */
1120 union pipe_numeric_type_union max_value
; /* max value that can be returned */
1121 enum pipe_driver_query_type type
;
1122 enum pipe_driver_query_result_type result_type
;
1127 struct pipe_driver_query_group_info
1130 unsigned max_active_queries
;
1131 unsigned num_queries
;
1136 PIPE_FD_TYPE_NATIVE_SYNC
,
1137 PIPE_FD_TYPE_SYNCOBJ
,
1140 enum pipe_debug_type
1142 PIPE_DEBUG_TYPE_OUT_OF_MEMORY
= 1,
1143 PIPE_DEBUG_TYPE_ERROR
,
1144 PIPE_DEBUG_TYPE_SHADER_INFO
,
1145 PIPE_DEBUG_TYPE_PERF_INFO
,
1146 PIPE_DEBUG_TYPE_INFO
,
1147 PIPE_DEBUG_TYPE_FALLBACK
,
1148 PIPE_DEBUG_TYPE_CONFORMANCE
,
1151 #define PIPE_UUID_SIZE 16