2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
42 struct amdgpu_sparse_backing_chunk
{
46 static struct pb_buffer
*
47 amdgpu_bo_create(struct radeon_winsys
*rws
,
50 enum radeon_bo_domain domain
,
51 enum radeon_bo_flag flags
);
53 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
54 enum radeon_bo_usage usage
)
56 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
57 struct amdgpu_winsys
*ws
= bo
->ws
;
61 if (p_atomic_read(&bo
->num_active_ioctls
))
65 abs_timeout
= os_time_get_absolute_timeout(timeout
);
67 /* Wait if any ioctl is being submitted with this buffer. */
68 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
73 /* We can't use user fences for shared buffers, because user fences
74 * are local to this process only. If we want to wait for all buffer
75 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
77 bool buffer_busy
= true;
80 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
82 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
91 mtx_lock(&ws
->bo_fence_lock
);
93 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
94 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
98 /* Release the idle fences to avoid checking them again later. */
99 for (unsigned i
= 0; i
< idle_fences
; ++i
)
100 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
102 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
103 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
104 bo
->num_fences
-= idle_fences
;
106 buffer_idle
= !bo
->num_fences
;
107 mtx_unlock(&ws
->bo_fence_lock
);
111 bool buffer_idle
= true;
113 mtx_lock(&ws
->bo_fence_lock
);
114 while (bo
->num_fences
&& buffer_idle
) {
115 struct pipe_fence_handle
*fence
= NULL
;
116 bool fence_idle
= false;
118 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
120 /* Wait for the fence. */
121 mtx_unlock(&ws
->bo_fence_lock
);
122 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
126 mtx_lock(&ws
->bo_fence_lock
);
128 /* Release an idle fence to avoid checking it again later, keeping in
129 * mind that the fence array may have been modified by other threads.
131 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
132 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
133 memmove(&bo
->fences
[0], &bo
->fences
[1],
134 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
138 amdgpu_fence_reference(&fence
, NULL
);
140 mtx_unlock(&ws
->bo_fence_lock
);
146 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
147 struct pb_buffer
*buf
)
149 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
152 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
154 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
155 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
162 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
164 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
166 assert(bo
->bo
&& "must not be called for slab entries");
168 mtx_lock(&bo
->ws
->global_bo_list_lock
);
169 LIST_DEL(&bo
->u
.real
.global_list_item
);
170 bo
->ws
->num_buffers
--;
171 mtx_unlock(&bo
->ws
->global_bo_list_lock
);
173 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
174 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
175 amdgpu_bo_free(bo
->bo
);
177 amdgpu_bo_remove_fences(bo
);
179 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
180 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
181 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
182 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
184 if (bo
->u
.real
.map_count
>= 1) {
185 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
186 bo
->ws
->mapped_vram
-= bo
->base
.size
;
187 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
188 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
189 bo
->ws
->num_mapped_buffers
--;
195 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
197 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
199 assert(bo
->bo
); /* slab buffers have a separate vtbl */
201 if (bo
->u
.real
.use_reusable_pool
)
202 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
204 amdgpu_bo_destroy(_buf
);
207 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
208 struct radeon_winsys_cs
*rcs
,
209 enum pipe_transfer_usage usage
)
211 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
212 struct amdgpu_winsys_bo
*real
;
213 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
220 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
221 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
222 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
223 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
224 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
227 * Since we are mapping for read, we don't need to wait
228 * if the GPU is using the buffer for read too
229 * (neither one is changing it).
231 * Only check whether the buffer is being used for write. */
232 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
233 RADEON_USAGE_WRITE
)) {
234 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
238 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
239 RADEON_USAGE_WRITE
)) {
243 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
244 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
248 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
249 RADEON_USAGE_READWRITE
)) {
254 uint64_t time
= os_time_get_nano();
256 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
259 * Since we are mapping for read, we don't need to wait
260 * if the GPU is using the buffer for read too
261 * (neither one is changing it).
263 * Only check whether the buffer is being used for write. */
265 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
266 RADEON_USAGE_WRITE
)) {
267 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
269 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
270 if (p_atomic_read(&bo
->num_active_ioctls
))
271 amdgpu_cs_sync_flush(rcs
);
275 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
278 /* Mapping for write. */
280 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
281 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
283 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
284 if (p_atomic_read(&bo
->num_active_ioctls
))
285 amdgpu_cs_sync_flush(rcs
);
289 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
290 RADEON_USAGE_READWRITE
);
293 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
297 /* If the buffer is created from user memory, return the user pointer. */
304 real
= bo
->u
.slab
.real
;
305 offset
= bo
->va
- real
->va
;
308 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
310 /* Clear the cache and try again. */
311 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
312 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
317 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
318 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
319 real
->ws
->mapped_vram
+= real
->base
.size
;
320 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
321 real
->ws
->mapped_gtt
+= real
->base
.size
;
322 real
->ws
->num_mapped_buffers
++;
324 return (uint8_t*)cpu
+ offset
;
327 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
329 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
330 struct amdgpu_winsys_bo
*real
;
337 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
339 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
340 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
341 real
->ws
->mapped_vram
-= real
->base
.size
;
342 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
343 real
->ws
->mapped_gtt
-= real
->base
.size
;
344 real
->ws
->num_mapped_buffers
--;
347 amdgpu_bo_cpu_unmap(real
->bo
);
350 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
351 amdgpu_bo_destroy_or_cache
352 /* other functions are never called */
355 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
357 struct amdgpu_winsys
*ws
= bo
->ws
;
361 mtx_lock(&ws
->global_bo_list_lock
);
362 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
364 mtx_unlock(&ws
->global_bo_list_lock
);
367 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
371 enum radeon_bo_domain initial_domain
,
373 unsigned pb_cache_bucket
)
375 struct amdgpu_bo_alloc_request request
= {0};
376 amdgpu_bo_handle buf_handle
;
378 struct amdgpu_winsys_bo
*bo
;
379 amdgpu_va_handle va_handle
;
380 unsigned va_gap_size
;
383 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
384 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
389 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
391 request
.alloc_size
= size
;
392 request
.phys_alignment
= alignment
;
394 if (initial_domain
& RADEON_DOMAIN_VRAM
)
395 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
396 if (initial_domain
& RADEON_DOMAIN_GTT
)
397 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
399 if (flags
& RADEON_FLAG_CPU_ACCESS
)
400 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
401 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
402 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
403 if (flags
& RADEON_FLAG_GTT_WC
)
404 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
406 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
408 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
409 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
410 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
411 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
415 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
416 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
417 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
421 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
425 pipe_reference_init(&bo
->base
.reference
, 1);
426 bo
->base
.alignment
= alignment
;
427 bo
->base
.usage
= usage
;
428 bo
->base
.size
= size
;
429 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
433 bo
->u
.real
.va_handle
= va_handle
;
434 bo
->initial_domain
= initial_domain
;
435 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
437 if (initial_domain
& RADEON_DOMAIN_VRAM
)
438 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
439 else if (initial_domain
& RADEON_DOMAIN_GTT
)
440 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
442 amdgpu_add_buffer_to_global_list(bo
);
447 amdgpu_va_range_free(va_handle
);
450 amdgpu_bo_free(buf_handle
);
457 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
459 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
461 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
465 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
468 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
470 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
471 bo
= container_of(entry
, bo
, u
.slab
.entry
);
473 return amdgpu_bo_can_reclaim(&bo
->base
);
476 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
478 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
482 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
485 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
486 amdgpu_bo_slab_destroy
487 /* other functions are never called */
490 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
492 unsigned group_index
)
494 struct amdgpu_winsys
*ws
= priv
;
495 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
496 enum radeon_bo_domain domains
;
497 enum radeon_bo_flag flags
= 0;
504 flags
|= RADEON_FLAG_GTT_WC
;
506 flags
|= RADEON_FLAG_CPU_ACCESS
;
510 domains
= RADEON_DOMAIN_VRAM
;
514 domains
= RADEON_DOMAIN_VRAM_GTT
;
517 domains
= RADEON_DOMAIN_GTT
;
521 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
522 64 * 1024, 64 * 1024,
527 assert(slab
->buffer
->bo
);
529 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
530 slab
->base
.num_free
= slab
->base
.num_entries
;
531 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
535 LIST_INITHEAD(&slab
->base
.free
);
537 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
539 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
540 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
542 bo
->base
.alignment
= entry_size
;
543 bo
->base
.usage
= slab
->buffer
->base
.usage
;
544 bo
->base
.size
= entry_size
;
545 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
547 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
548 bo
->initial_domain
= domains
;
549 bo
->unique_id
= base_id
+ i
;
550 bo
->u
.slab
.entry
.slab
= &slab
->base
;
551 bo
->u
.slab
.entry
.group_index
= group_index
;
552 bo
->u
.slab
.real
= slab
->buffer
;
554 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
560 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
566 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
568 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
570 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
571 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
574 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
579 * Attempt to allocate the given number of backing pages. Fewer pages may be
580 * allocated (depending on the fragmentation of existing backing buffers),
581 * which will be reflected by a change to *pnum_pages.
583 static struct amdgpu_sparse_backing
*
584 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
586 struct amdgpu_sparse_backing
*best_backing
;
588 uint32_t best_num_pages
;
594 /* This is a very simple and inefficient best-fit algorithm. */
595 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
596 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
597 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
598 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
599 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
600 best_backing
= backing
;
602 best_num_pages
= cur_num_pages
;
607 /* Allocate a new backing buffer if necessary. */
609 struct pb_buffer
*buf
;
613 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
617 best_backing
->max_chunks
= 4;
618 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
619 sizeof(*best_backing
->chunks
));
620 if (!best_backing
->chunks
) {
625 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
627 size
= MIN3(bo
->base
.size
/ 16,
629 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
630 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
632 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
634 bo
->u
.sparse
.flags
| RADEON_FLAG_HANDLE
);
636 FREE(best_backing
->chunks
);
641 /* We might have gotten a bigger buffer than requested via caching. */
642 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
644 best_backing
->bo
= amdgpu_winsys_bo(buf
);
645 best_backing
->num_chunks
= 1;
646 best_backing
->chunks
[0].begin
= 0;
647 best_backing
->chunks
[0].end
= pages
;
649 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
650 bo
->u
.sparse
.num_backing_pages
+= pages
;
653 best_num_pages
= pages
;
656 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
657 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
658 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
660 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
661 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
662 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
663 best_backing
->num_chunks
--;
670 sparse_free_backing_buffer(struct amdgpu_sparse_backing
*backing
)
672 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
674 list_del(&backing
->list
);
675 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
676 FREE(backing
->chunks
);
681 * Return a range of pages from the given backing buffer back into the
685 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
686 struct amdgpu_sparse_backing
*backing
,
687 uint32_t start_page
, uint32_t num_pages
)
689 uint32_t end_page
= start_page
+ num_pages
;
691 unsigned high
= backing
->num_chunks
;
693 /* Find the first chunk with begin >= start_page. */
695 unsigned mid
= low
+ (high
- low
) / 2;
697 if (backing
->chunks
[mid
].begin
>= start_page
)
703 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
704 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
706 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
707 backing
->chunks
[low
- 1].end
= end_page
;
709 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
710 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
711 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
712 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
713 backing
->num_chunks
--;
715 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
716 backing
->chunks
[low
].begin
= start_page
;
718 if (backing
->num_chunks
>= backing
->max_chunks
) {
719 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
720 struct amdgpu_sparse_backing_chunk
*new_chunks
=
721 REALLOC(backing
->chunks
,
722 sizeof(*backing
->chunks
) * backing
->max_chunks
,
723 sizeof(*backing
->chunks
) * new_max_chunks
);
727 backing
->max_chunks
= new_max_chunks
;
728 backing
->chunks
= new_chunks
;
731 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
732 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
733 backing
->chunks
[low
].begin
= start_page
;
734 backing
->chunks
[low
].end
= end_page
;
735 backing
->num_chunks
++;
738 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
739 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
740 sparse_free_backing_buffer(backing
);
745 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
747 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
750 assert(!bo
->bo
&& bo
->sparse
);
752 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
753 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
754 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
756 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
759 while (!list_empty(&bo
->u
.sparse
.backing
)) {
760 struct amdgpu_sparse_backing
*dummy
= NULL
;
761 sparse_free_backing_buffer(container_of(bo
->u
.sparse
.backing
.next
,
765 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
766 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
767 FREE(bo
->u
.sparse
.commitments
);
771 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
772 amdgpu_bo_sparse_destroy
773 /* other functions are never called */
776 static struct pb_buffer
*
777 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
778 enum radeon_bo_domain domain
,
779 enum radeon_bo_flag flags
)
781 struct amdgpu_winsys_bo
*bo
;
783 uint64_t va_gap_size
;
786 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
787 * that exceed this limit. This is not really a restriction: we don't have
788 * that much virtual address space anyway.
790 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
793 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
797 pipe_reference_init(&bo
->base
.reference
, 1);
798 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
799 bo
->base
.size
= size
;
800 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
802 bo
->initial_domain
= domain
;
803 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
805 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
807 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
808 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
809 sizeof(*bo
->u
.sparse
.commitments
));
810 if (!bo
->u
.sparse
.commitments
)
811 goto error_alloc_commitments
;
813 mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
814 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
816 /* For simplicity, we always map a multiple of the page size. */
817 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
818 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
819 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
820 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
821 0, &bo
->va
, &bo
->u
.sparse
.va_handle
, 0);
825 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
826 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
833 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
835 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
836 FREE(bo
->u
.sparse
.commitments
);
837 error_alloc_commitments
:
843 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
846 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
847 struct amdgpu_sparse_commitment
*comm
;
848 uint32_t va_page
, end_va_page
;
853 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
854 assert(offset
<= bo
->base
.size
);
855 assert(size
<= bo
->base
.size
- offset
);
856 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
858 comm
= bo
->u
.sparse
.commitments
;
859 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
860 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
862 mtx_lock(&bo
->u
.sparse
.commit_lock
);
865 while (va_page
< end_va_page
) {
866 uint32_t span_va_page
;
868 /* Skip pages that are already committed. */
869 if (comm
[va_page
].backing
) {
874 /* Determine length of uncommitted span. */
875 span_va_page
= va_page
;
876 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
879 /* Fill the uncommitted span with chunks of backing memory. */
880 while (span_va_page
< va_page
) {
881 struct amdgpu_sparse_backing
*backing
;
882 uint32_t backing_start
, backing_size
;
884 backing_size
= va_page
- span_va_page
;
885 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
891 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
892 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
893 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
894 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
895 AMDGPU_VM_PAGE_READABLE
|
896 AMDGPU_VM_PAGE_WRITEABLE
|
897 AMDGPU_VM_PAGE_EXECUTABLE
,
898 AMDGPU_VA_OP_REPLACE
);
900 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
901 assert(ok
&& "sufficient memory should already be allocated");
907 while (backing_size
) {
908 comm
[span_va_page
].backing
= backing
;
909 comm
[span_va_page
].page
= backing_start
;
917 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
918 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
919 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
920 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
926 while (va_page
< end_va_page
) {
927 struct amdgpu_sparse_backing
*backing
;
928 uint32_t backing_start
;
931 /* Skip pages that are already uncommitted. */
932 if (!comm
[va_page
].backing
) {
937 /* Group contiguous spans of pages. */
938 backing
= comm
[va_page
].backing
;
939 backing_start
= comm
[va_page
].page
;
940 comm
[va_page
].backing
= NULL
;
945 while (va_page
< end_va_page
&&
946 comm
[va_page
].backing
== backing
&&
947 comm
[va_page
].page
== backing_start
+ span_pages
) {
948 comm
[va_page
].backing
= NULL
;
953 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
954 /* Couldn't allocate tracking data structures, so we have to leak */
955 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
962 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
967 static unsigned eg_tile_split(unsigned tile_split
)
969 switch (tile_split
) {
970 case 0: tile_split
= 64; break;
971 case 1: tile_split
= 128; break;
972 case 2: tile_split
= 256; break;
973 case 3: tile_split
= 512; break;
975 case 4: tile_split
= 1024; break;
976 case 5: tile_split
= 2048; break;
977 case 6: tile_split
= 4096; break;
982 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
984 switch (eg_tile_split
) {
996 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
997 struct radeon_bo_metadata
*md
)
999 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1000 struct amdgpu_bo_info info
= {0};
1001 uint64_t tiling_flags
;
1004 assert(bo
->bo
&& "must not be called for slab entries");
1006 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1010 tiling_flags
= info
.metadata
.tiling_info
;
1012 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1013 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1015 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1016 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1018 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1019 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1020 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1021 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1023 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1024 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1025 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1026 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1027 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1028 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1029 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1032 md
->size_metadata
= info
.metadata
.size_metadata
;
1033 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1036 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1037 struct radeon_bo_metadata
*md
)
1039 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1040 struct amdgpu_bo_metadata metadata
= {0};
1041 uint64_t tiling_flags
= 0;
1043 assert(bo
->bo
&& "must not be called for slab entries");
1045 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1046 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1048 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1049 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1050 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1051 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1053 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1055 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1056 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1057 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1058 if (md
->u
.legacy
.tile_split
)
1059 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1060 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1061 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1063 if (md
->u
.legacy
.scanout
)
1064 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1066 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1069 metadata
.tiling_info
= tiling_flags
;
1070 metadata
.size_metadata
= md
->size_metadata
;
1071 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1073 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1076 static struct pb_buffer
*
1077 amdgpu_bo_create(struct radeon_winsys
*rws
,
1080 enum radeon_bo_domain domain
,
1081 enum radeon_bo_flag flags
)
1083 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1084 struct amdgpu_winsys_bo
*bo
;
1085 unsigned usage
= 0, pb_cache_bucket
;
1087 /* Sub-allocate small buffers from slabs. */
1088 if (!(flags
& (RADEON_FLAG_HANDLE
| RADEON_FLAG_SPARSE
)) &&
1089 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1090 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1091 struct pb_slab_entry
*entry
;
1094 if (flags
& RADEON_FLAG_GTT_WC
)
1096 if (flags
& RADEON_FLAG_CPU_ACCESS
)
1098 if (flags
& ~(RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
))
1102 case RADEON_DOMAIN_VRAM
:
1105 case RADEON_DOMAIN_VRAM_GTT
:
1108 case RADEON_DOMAIN_GTT
:
1115 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1117 /* Clear the cache and try again. */
1118 pb_cache_release_all_buffers(&ws
->bo_cache
);
1120 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1126 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1128 pipe_reference_init(&bo
->base
.reference
, 1);
1134 if (flags
& RADEON_FLAG_SPARSE
) {
1135 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1136 assert(!(flags
& RADEON_FLAG_CPU_ACCESS
));
1138 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1140 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1143 /* This flag is irrelevant for the cache. */
1144 flags
&= ~RADEON_FLAG_HANDLE
;
1146 /* Align size to page size. This is the minimum alignment for normal
1147 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1148 * like constant/uniform buffers, can benefit from better and more reuse.
1150 size
= align64(size
, ws
->info
.gart_page_size
);
1151 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1153 /* Only set one usage bit each for domains and flags, or the cache manager
1154 * might consider different sets of domains / flags compatible
1156 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
1159 usage
= domain
>> 1;
1160 assert(flags
< sizeof(usage
) * 8 - 3);
1161 usage
|= 1 << (flags
+ 3);
1163 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
1164 pb_cache_bucket
= 0;
1165 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
1166 pb_cache_bucket
+= 1;
1167 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
1168 pb_cache_bucket
+= 2;
1169 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
1171 /* Get a buffer from the cache. */
1172 bo
= (struct amdgpu_winsys_bo
*)
1173 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
1178 /* Create a new one. */
1179 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1182 /* Clear the cache and try again. */
1183 pb_slabs_reclaim(&ws
->bo_slabs
);
1184 pb_cache_release_all_buffers(&ws
->bo_cache
);
1185 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1191 bo
->u
.real
.use_reusable_pool
= true;
1195 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1196 struct winsys_handle
*whandle
,
1200 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1201 struct amdgpu_winsys_bo
*bo
;
1202 enum amdgpu_bo_handle_type type
;
1203 struct amdgpu_bo_import_result result
= {0};
1205 amdgpu_va_handle va_handle
;
1206 struct amdgpu_bo_info info
= {0};
1207 enum radeon_bo_domain initial
= 0;
1210 /* Initialize the structure. */
1211 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1216 switch (whandle
->type
) {
1217 case DRM_API_HANDLE_TYPE_SHARED
:
1218 type
= amdgpu_bo_handle_type_gem_flink_name
;
1220 case DRM_API_HANDLE_TYPE_FD
:
1221 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1227 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1231 /* Get initial domains. */
1232 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1236 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1237 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
1241 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1245 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1246 initial
|= RADEON_DOMAIN_VRAM
;
1247 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1248 initial
|= RADEON_DOMAIN_GTT
;
1251 pipe_reference_init(&bo
->base
.reference
, 1);
1252 bo
->base
.alignment
= info
.phys_alignment
;
1253 bo
->bo
= result
.buf_handle
;
1254 bo
->base
.size
= result
.alloc_size
;
1255 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1258 bo
->u
.real
.va_handle
= va_handle
;
1259 bo
->initial_domain
= initial
;
1260 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1261 bo
->is_shared
= true;
1264 *stride
= whandle
->stride
;
1266 *offset
= whandle
->offset
;
1268 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1269 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1270 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1271 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1273 amdgpu_add_buffer_to_global_list(bo
);
1278 amdgpu_va_range_free(va_handle
);
1281 amdgpu_bo_free(result
.buf_handle
);
1288 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1289 unsigned stride
, unsigned offset
,
1290 unsigned slice_size
,
1291 struct winsys_handle
*whandle
)
1293 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1294 enum amdgpu_bo_handle_type type
;
1298 offset
+= bo
->va
- bo
->u
.slab
.real
->va
;
1299 bo
= bo
->u
.slab
.real
;
1302 bo
->u
.real
.use_reusable_pool
= false;
1304 switch (whandle
->type
) {
1305 case DRM_API_HANDLE_TYPE_SHARED
:
1306 type
= amdgpu_bo_handle_type_gem_flink_name
;
1308 case DRM_API_HANDLE_TYPE_FD
:
1309 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1311 case DRM_API_HANDLE_TYPE_KMS
:
1312 type
= amdgpu_bo_handle_type_kms
;
1318 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1322 whandle
->stride
= stride
;
1323 whandle
->offset
= offset
;
1324 whandle
->offset
+= slice_size
* whandle
->layer
;
1325 bo
->is_shared
= true;
1329 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1330 void *pointer
, uint64_t size
)
1332 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1333 amdgpu_bo_handle buf_handle
;
1334 struct amdgpu_winsys_bo
*bo
;
1336 amdgpu_va_handle va_handle
;
1338 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1342 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
1345 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1346 size
, 1 << 12, 0, &va
, &va_handle
, 0))
1347 goto error_va_alloc
;
1349 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
1352 /* Initialize it. */
1353 pipe_reference_init(&bo
->base
.reference
, 1);
1354 bo
->bo
= buf_handle
;
1355 bo
->base
.alignment
= 0;
1356 bo
->base
.size
= size
;
1357 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1359 bo
->user_ptr
= pointer
;
1361 bo
->u
.real
.va_handle
= va_handle
;
1362 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1363 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1365 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1367 amdgpu_add_buffer_to_global_list(bo
);
1369 return (struct pb_buffer
*)bo
;
1372 amdgpu_va_range_free(va_handle
);
1375 amdgpu_bo_free(buf_handle
);
1382 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1384 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1387 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1389 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1392 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1394 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1395 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1396 ws
->base
.buffer_map
= amdgpu_bo_map
;
1397 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1398 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1399 ws
->base
.buffer_create
= amdgpu_bo_create
;
1400 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1401 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1402 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1403 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1404 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1405 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1406 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;