2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
31 #include "state_tracker/drm_driver.h"
32 #include <amdgpu_drm.h>
37 #ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
38 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
41 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
42 #define DEBUG_SPARSE_COMMITS 0
44 struct amdgpu_sparse_backing_chunk
{
48 static struct pb_buffer
*
49 amdgpu_bo_create(struct radeon_winsys
*rws
,
52 enum radeon_bo_domain domain
,
53 enum radeon_bo_flag flags
);
55 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
56 enum radeon_bo_usage usage
)
58 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
59 struct amdgpu_winsys
*ws
= bo
->ws
;
63 if (p_atomic_read(&bo
->num_active_ioctls
))
67 abs_timeout
= os_time_get_absolute_timeout(timeout
);
69 /* Wait if any ioctl is being submitted with this buffer. */
70 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
75 /* We can't use user fences for shared buffers, because user fences
76 * are local to this process only. If we want to wait for all buffer
77 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
79 bool buffer_busy
= true;
82 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
84 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
93 simple_mtx_lock(&ws
->bo_fence_lock
);
95 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
96 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
100 /* Release the idle fences to avoid checking them again later. */
101 for (unsigned i
= 0; i
< idle_fences
; ++i
)
102 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
104 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
105 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
106 bo
->num_fences
-= idle_fences
;
108 buffer_idle
= !bo
->num_fences
;
109 simple_mtx_unlock(&ws
->bo_fence_lock
);
113 bool buffer_idle
= true;
115 simple_mtx_lock(&ws
->bo_fence_lock
);
116 while (bo
->num_fences
&& buffer_idle
) {
117 struct pipe_fence_handle
*fence
= NULL
;
118 bool fence_idle
= false;
120 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
122 /* Wait for the fence. */
123 simple_mtx_unlock(&ws
->bo_fence_lock
);
124 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
128 simple_mtx_lock(&ws
->bo_fence_lock
);
130 /* Release an idle fence to avoid checking it again later, keeping in
131 * mind that the fence array may have been modified by other threads.
133 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
134 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
135 memmove(&bo
->fences
[0], &bo
->fences
[1],
136 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
140 amdgpu_fence_reference(&fence
, NULL
);
142 simple_mtx_unlock(&ws
->bo_fence_lock
);
148 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
149 struct pb_buffer
*buf
)
151 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
154 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
156 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
157 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
164 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
166 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
168 assert(bo
->bo
&& "must not be called for slab entries");
170 if (bo
->ws
->debug_all_bos
) {
171 simple_mtx_lock(&bo
->ws
->global_bo_list_lock
);
172 LIST_DEL(&bo
->u
.real
.global_list_item
);
173 bo
->ws
->num_buffers
--;
174 simple_mtx_unlock(&bo
->ws
->global_bo_list_lock
);
177 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
178 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
179 amdgpu_bo_free(bo
->bo
);
181 amdgpu_bo_remove_fences(bo
);
183 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
184 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
185 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
186 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
188 if (bo
->u
.real
.map_count
>= 1) {
189 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
190 bo
->ws
->mapped_vram
-= bo
->base
.size
;
191 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
192 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
193 bo
->ws
->num_mapped_buffers
--;
199 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
201 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
203 assert(bo
->bo
); /* slab buffers have a separate vtbl */
205 if (bo
->u
.real
.use_reusable_pool
)
206 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
208 amdgpu_bo_destroy(_buf
);
211 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
212 struct radeon_winsys_cs
*rcs
,
213 enum pipe_transfer_usage usage
)
215 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
216 struct amdgpu_winsys_bo
*real
;
217 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
224 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
225 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
226 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
227 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
228 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
231 * Since we are mapping for read, we don't need to wait
232 * if the GPU is using the buffer for read too
233 * (neither one is changing it).
235 * Only check whether the buffer is being used for write. */
236 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
237 RADEON_USAGE_WRITE
)) {
238 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
242 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
243 RADEON_USAGE_WRITE
)) {
247 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
248 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
252 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
253 RADEON_USAGE_READWRITE
)) {
258 uint64_t time
= os_time_get_nano();
260 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
263 * Since we are mapping for read, we don't need to wait
264 * if the GPU is using the buffer for read too
265 * (neither one is changing it).
267 * Only check whether the buffer is being used for write. */
269 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
270 RADEON_USAGE_WRITE
)) {
271 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
273 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
274 if (p_atomic_read(&bo
->num_active_ioctls
))
275 amdgpu_cs_sync_flush(rcs
);
279 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
282 /* Mapping for write. */
284 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
285 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
287 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
288 if (p_atomic_read(&bo
->num_active_ioctls
))
289 amdgpu_cs_sync_flush(rcs
);
293 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
294 RADEON_USAGE_READWRITE
);
297 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
301 /* If the buffer is created from user memory, return the user pointer. */
308 real
= bo
->u
.slab
.real
;
309 offset
= bo
->va
- real
->va
;
312 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
314 /* Clear the cache and try again. */
315 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
316 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
321 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
322 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
323 real
->ws
->mapped_vram
+= real
->base
.size
;
324 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
325 real
->ws
->mapped_gtt
+= real
->base
.size
;
326 real
->ws
->num_mapped_buffers
++;
328 return (uint8_t*)cpu
+ offset
;
331 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
333 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
334 struct amdgpu_winsys_bo
*real
;
341 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
343 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
344 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
345 real
->ws
->mapped_vram
-= real
->base
.size
;
346 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
347 real
->ws
->mapped_gtt
-= real
->base
.size
;
348 real
->ws
->num_mapped_buffers
--;
351 amdgpu_bo_cpu_unmap(real
->bo
);
354 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
355 amdgpu_bo_destroy_or_cache
356 /* other functions are never called */
359 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
361 struct amdgpu_winsys
*ws
= bo
->ws
;
365 if (ws
->debug_all_bos
) {
366 simple_mtx_lock(&ws
->global_bo_list_lock
);
367 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
369 simple_mtx_unlock(&ws
->global_bo_list_lock
);
373 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
377 enum radeon_bo_domain initial_domain
,
379 unsigned pb_cache_bucket
)
381 struct amdgpu_bo_alloc_request request
= {0};
382 amdgpu_bo_handle buf_handle
;
384 struct amdgpu_winsys_bo
*bo
;
385 amdgpu_va_handle va_handle
;
386 unsigned va_gap_size
;
389 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
390 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
395 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
397 request
.alloc_size
= size
;
398 request
.phys_alignment
= alignment
;
400 if (initial_domain
& RADEON_DOMAIN_VRAM
)
401 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
402 if (initial_domain
& RADEON_DOMAIN_GTT
)
403 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
405 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
406 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
407 if (flags
& RADEON_FLAG_GTT_WC
)
408 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
409 if (flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
410 ws
->info
.drm_minor
>= 20)
411 request
.flags
|= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
;
413 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
415 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
416 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
417 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
418 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
422 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
423 if (size
> ws
->info
.pte_fragment_size
)
424 alignment
= MAX2(alignment
, ws
->info
.pte_fragment_size
);
425 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
426 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
430 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
434 pipe_reference_init(&bo
->base
.reference
, 1);
435 bo
->base
.alignment
= alignment
;
436 bo
->base
.usage
= usage
;
437 bo
->base
.size
= size
;
438 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
442 bo
->u
.real
.va_handle
= va_handle
;
443 bo
->initial_domain
= initial_domain
;
444 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
445 bo
->is_local
= !!(request
.flags
& AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
);
447 if (initial_domain
& RADEON_DOMAIN_VRAM
)
448 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
449 else if (initial_domain
& RADEON_DOMAIN_GTT
)
450 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
452 amdgpu_add_buffer_to_global_list(bo
);
457 amdgpu_va_range_free(va_handle
);
460 amdgpu_bo_free(buf_handle
);
467 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
469 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
471 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
475 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
478 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
480 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
481 bo
= container_of(entry
, bo
, u
.slab
.entry
);
483 return amdgpu_bo_can_reclaim(&bo
->base
);
486 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
488 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
492 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
495 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
496 amdgpu_bo_slab_destroy
497 /* other functions are never called */
500 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
502 unsigned group_index
)
504 struct amdgpu_winsys
*ws
= priv
;
505 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
506 enum radeon_bo_domain domains
= radeon_domain_from_heap(heap
);
507 enum radeon_bo_flag flags
= radeon_flags_from_heap(heap
);
513 unsigned slab_size
= 1 << AMDGPU_SLAB_BO_SIZE_LOG2
;
514 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
515 slab_size
, slab_size
,
520 assert(slab
->buffer
->bo
);
522 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
523 slab
->base
.num_free
= slab
->base
.num_entries
;
524 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
528 LIST_INITHEAD(&slab
->base
.free
);
530 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
532 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
533 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
535 bo
->base
.alignment
= entry_size
;
536 bo
->base
.usage
= slab
->buffer
->base
.usage
;
537 bo
->base
.size
= entry_size
;
538 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
540 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
541 bo
->initial_domain
= domains
;
542 bo
->unique_id
= base_id
+ i
;
543 bo
->u
.slab
.entry
.slab
= &slab
->base
;
544 bo
->u
.slab
.entry
.group_index
= group_index
;
545 bo
->u
.slab
.real
= slab
->buffer
;
547 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
553 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
559 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
561 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
563 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
564 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
567 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
571 #if DEBUG_SPARSE_COMMITS
573 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
575 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
577 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
579 struct amdgpu_sparse_backing
*span_backing
= NULL
;
580 uint32_t span_first_backing_page
= 0;
581 uint32_t span_first_va_page
= 0;
582 uint32_t va_page
= 0;
585 struct amdgpu_sparse_backing
*backing
= 0;
586 uint32_t backing_page
= 0;
588 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
589 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
590 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
594 (backing
!= span_backing
||
595 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
596 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
597 span_first_va_page
, va_page
- 1, span_backing
,
598 span_first_backing_page
,
599 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
604 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
607 if (backing
&& !span_backing
) {
608 span_backing
= backing
;
609 span_first_backing_page
= backing_page
;
610 span_first_va_page
= va_page
;
616 fprintf(stderr
, "Backing:\n");
618 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
619 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
620 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
621 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
627 * Attempt to allocate the given number of backing pages. Fewer pages may be
628 * allocated (depending on the fragmentation of existing backing buffers),
629 * which will be reflected by a change to *pnum_pages.
631 static struct amdgpu_sparse_backing
*
632 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
634 struct amdgpu_sparse_backing
*best_backing
;
636 uint32_t best_num_pages
;
642 /* This is a very simple and inefficient best-fit algorithm. */
643 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
644 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
645 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
646 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
647 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
648 best_backing
= backing
;
650 best_num_pages
= cur_num_pages
;
655 /* Allocate a new backing buffer if necessary. */
657 struct pb_buffer
*buf
;
661 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
665 best_backing
->max_chunks
= 4;
666 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
667 sizeof(*best_backing
->chunks
));
668 if (!best_backing
->chunks
) {
673 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
675 size
= MIN3(bo
->base
.size
/ 16,
677 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
678 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
680 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
682 bo
->u
.sparse
.flags
| RADEON_FLAG_NO_SUBALLOC
);
684 FREE(best_backing
->chunks
);
689 /* We might have gotten a bigger buffer than requested via caching. */
690 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
692 best_backing
->bo
= amdgpu_winsys_bo(buf
);
693 best_backing
->num_chunks
= 1;
694 best_backing
->chunks
[0].begin
= 0;
695 best_backing
->chunks
[0].end
= pages
;
697 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
698 bo
->u
.sparse
.num_backing_pages
+= pages
;
701 best_num_pages
= pages
;
704 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
705 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
706 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
708 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
709 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
710 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
711 best_backing
->num_chunks
--;
718 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
719 struct amdgpu_sparse_backing
*backing
)
721 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
723 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
725 simple_mtx_lock(&ws
->bo_fence_lock
);
726 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
727 simple_mtx_unlock(&ws
->bo_fence_lock
);
729 list_del(&backing
->list
);
730 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
731 FREE(backing
->chunks
);
736 * Return a range of pages from the given backing buffer back into the
740 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
741 struct amdgpu_sparse_backing
*backing
,
742 uint32_t start_page
, uint32_t num_pages
)
744 uint32_t end_page
= start_page
+ num_pages
;
746 unsigned high
= backing
->num_chunks
;
748 /* Find the first chunk with begin >= start_page. */
750 unsigned mid
= low
+ (high
- low
) / 2;
752 if (backing
->chunks
[mid
].begin
>= start_page
)
758 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
759 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
761 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
762 backing
->chunks
[low
- 1].end
= end_page
;
764 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
765 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
766 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
767 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
768 backing
->num_chunks
--;
770 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
771 backing
->chunks
[low
].begin
= start_page
;
773 if (backing
->num_chunks
>= backing
->max_chunks
) {
774 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
775 struct amdgpu_sparse_backing_chunk
*new_chunks
=
776 REALLOC(backing
->chunks
,
777 sizeof(*backing
->chunks
) * backing
->max_chunks
,
778 sizeof(*backing
->chunks
) * new_max_chunks
);
782 backing
->max_chunks
= new_max_chunks
;
783 backing
->chunks
= new_chunks
;
786 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
787 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
788 backing
->chunks
[low
].begin
= start_page
;
789 backing
->chunks
[low
].end
= end_page
;
790 backing
->num_chunks
++;
793 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
794 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
795 sparse_free_backing_buffer(bo
, backing
);
800 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
802 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
805 assert(!bo
->bo
&& bo
->sparse
);
807 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
808 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
809 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
811 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
814 while (!list_empty(&bo
->u
.sparse
.backing
)) {
815 struct amdgpu_sparse_backing
*dummy
= NULL
;
816 sparse_free_backing_buffer(bo
,
817 container_of(bo
->u
.sparse
.backing
.next
,
821 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
822 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
823 FREE(bo
->u
.sparse
.commitments
);
827 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
828 amdgpu_bo_sparse_destroy
829 /* other functions are never called */
832 static struct pb_buffer
*
833 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
834 enum radeon_bo_domain domain
,
835 enum radeon_bo_flag flags
)
837 struct amdgpu_winsys_bo
*bo
;
839 uint64_t va_gap_size
;
842 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
843 * that exceed this limit. This is not really a restriction: we don't have
844 * that much virtual address space anyway.
846 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
849 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
853 pipe_reference_init(&bo
->base
.reference
, 1);
854 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
855 bo
->base
.size
= size
;
856 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
858 bo
->initial_domain
= domain
;
859 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
861 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
863 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
864 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
865 sizeof(*bo
->u
.sparse
.commitments
));
866 if (!bo
->u
.sparse
.commitments
)
867 goto error_alloc_commitments
;
869 simple_mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
870 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
872 /* For simplicity, we always map a multiple of the page size. */
873 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
874 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
875 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
876 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
877 0, &bo
->va
, &bo
->u
.sparse
.va_handle
, 0);
881 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
882 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
889 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
891 simple_mtx_destroy(&bo
->u
.sparse
.commit_lock
);
892 FREE(bo
->u
.sparse
.commitments
);
893 error_alloc_commitments
:
899 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
902 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
903 struct amdgpu_sparse_commitment
*comm
;
904 uint32_t va_page
, end_va_page
;
909 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
910 assert(offset
<= bo
->base
.size
);
911 assert(size
<= bo
->base
.size
- offset
);
912 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
914 comm
= bo
->u
.sparse
.commitments
;
915 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
916 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
918 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
920 #if DEBUG_SPARSE_COMMITS
921 sparse_dump(bo
, __func__
);
925 while (va_page
< end_va_page
) {
926 uint32_t span_va_page
;
928 /* Skip pages that are already committed. */
929 if (comm
[va_page
].backing
) {
934 /* Determine length of uncommitted span. */
935 span_va_page
= va_page
;
936 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
939 /* Fill the uncommitted span with chunks of backing memory. */
940 while (span_va_page
< va_page
) {
941 struct amdgpu_sparse_backing
*backing
;
942 uint32_t backing_start
, backing_size
;
944 backing_size
= va_page
- span_va_page
;
945 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
951 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
952 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
953 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
954 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
955 AMDGPU_VM_PAGE_READABLE
|
956 AMDGPU_VM_PAGE_WRITEABLE
|
957 AMDGPU_VM_PAGE_EXECUTABLE
,
958 AMDGPU_VA_OP_REPLACE
);
960 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
961 assert(ok
&& "sufficient memory should already be allocated");
967 while (backing_size
) {
968 comm
[span_va_page
].backing
= backing
;
969 comm
[span_va_page
].page
= backing_start
;
977 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
978 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
979 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
980 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
986 while (va_page
< end_va_page
) {
987 struct amdgpu_sparse_backing
*backing
;
988 uint32_t backing_start
;
991 /* Skip pages that are already uncommitted. */
992 if (!comm
[va_page
].backing
) {
997 /* Group contiguous spans of pages. */
998 backing
= comm
[va_page
].backing
;
999 backing_start
= comm
[va_page
].page
;
1000 comm
[va_page
].backing
= NULL
;
1005 while (va_page
< end_va_page
&&
1006 comm
[va_page
].backing
== backing
&&
1007 comm
[va_page
].page
== backing_start
+ span_pages
) {
1008 comm
[va_page
].backing
= NULL
;
1013 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1014 /* Couldn't allocate tracking data structures, so we have to leak */
1015 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1022 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1027 static unsigned eg_tile_split(unsigned tile_split
)
1029 switch (tile_split
) {
1030 case 0: tile_split
= 64; break;
1031 case 1: tile_split
= 128; break;
1032 case 2: tile_split
= 256; break;
1033 case 3: tile_split
= 512; break;
1035 case 4: tile_split
= 1024; break;
1036 case 5: tile_split
= 2048; break;
1037 case 6: tile_split
= 4096; break;
1042 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1044 switch (eg_tile_split
) {
1050 case 1024: return 4;
1051 case 2048: return 5;
1052 case 4096: return 6;
1056 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1057 struct radeon_bo_metadata
*md
)
1059 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1060 struct amdgpu_bo_info info
= {0};
1061 uint64_t tiling_flags
;
1064 assert(bo
->bo
&& "must not be called for slab entries");
1066 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1070 tiling_flags
= info
.metadata
.tiling_info
;
1072 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1073 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1075 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1076 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1078 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1079 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1080 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1081 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1083 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1084 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1085 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1086 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1087 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1088 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1089 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1092 md
->size_metadata
= info
.metadata
.size_metadata
;
1093 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1096 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1097 struct radeon_bo_metadata
*md
)
1099 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1100 struct amdgpu_bo_metadata metadata
= {0};
1101 uint64_t tiling_flags
= 0;
1103 assert(bo
->bo
&& "must not be called for slab entries");
1105 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1106 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1108 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1109 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1110 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1111 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1113 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1115 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1116 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1117 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1118 if (md
->u
.legacy
.tile_split
)
1119 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1120 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1121 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1123 if (md
->u
.legacy
.scanout
)
1124 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1126 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1129 metadata
.tiling_info
= tiling_flags
;
1130 metadata
.size_metadata
= md
->size_metadata
;
1131 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1133 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1136 static struct pb_buffer
*
1137 amdgpu_bo_create(struct radeon_winsys
*rws
,
1140 enum radeon_bo_domain domain
,
1141 enum radeon_bo_flag flags
)
1143 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1144 struct amdgpu_winsys_bo
*bo
;
1145 unsigned usage
= 0, pb_cache_bucket
= 0;
1147 /* VRAM implies WC. This is not optional. */
1148 assert(!(domain
& RADEON_DOMAIN_VRAM
) || flags
& RADEON_FLAG_GTT_WC
);
1150 /* NO_CPU_ACCESS is valid with VRAM only. */
1151 assert(domain
== RADEON_DOMAIN_VRAM
|| !(flags
& RADEON_FLAG_NO_CPU_ACCESS
));
1153 /* Sub-allocate small buffers from slabs. */
1154 if (!(flags
& (RADEON_FLAG_NO_SUBALLOC
| RADEON_FLAG_SPARSE
)) &&
1155 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1156 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1157 struct pb_slab_entry
*entry
;
1158 int heap
= radeon_get_heap_index(domain
, flags
);
1160 if (heap
< 0 || heap
>= RADEON_MAX_SLAB_HEAPS
)
1163 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1165 /* Clear the cache and try again. */
1166 pb_cache_release_all_buffers(&ws
->bo_cache
);
1168 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1174 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1176 pipe_reference_init(&bo
->base
.reference
, 1);
1182 if (flags
& RADEON_FLAG_SPARSE
) {
1183 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1185 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1187 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1190 /* This flag is irrelevant for the cache. */
1191 flags
&= ~RADEON_FLAG_NO_SUBALLOC
;
1193 /* Align size to page size. This is the minimum alignment for normal
1194 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1195 * like constant/uniform buffers, can benefit from better and more reuse.
1197 size
= align64(size
, ws
->info
.gart_page_size
);
1198 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1200 bool use_reusable_pool
= flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1202 if (use_reusable_pool
) {
1203 int heap
= radeon_get_heap_index(domain
, flags
);
1204 assert(heap
>= 0 && heap
< RADEON_MAX_CACHED_HEAPS
);
1205 usage
= 1 << heap
; /* Only set one usage bit for each heap. */
1207 pb_cache_bucket
= radeon_get_pb_cache_bucket_index(heap
);
1208 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
1210 /* Get a buffer from the cache. */
1211 bo
= (struct amdgpu_winsys_bo
*)
1212 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
1218 /* Create a new one. */
1219 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1222 /* Clear the cache and try again. */
1223 pb_slabs_reclaim(&ws
->bo_slabs
);
1224 pb_cache_release_all_buffers(&ws
->bo_cache
);
1225 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1231 bo
->u
.real
.use_reusable_pool
= use_reusable_pool
;
1235 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1236 struct winsys_handle
*whandle
,
1240 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1241 struct amdgpu_winsys_bo
*bo
;
1242 enum amdgpu_bo_handle_type type
;
1243 struct amdgpu_bo_import_result result
= {0};
1245 amdgpu_va_handle va_handle
;
1246 struct amdgpu_bo_info info
= {0};
1247 enum radeon_bo_domain initial
= 0;
1250 /* Initialize the structure. */
1251 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1256 switch (whandle
->type
) {
1257 case DRM_API_HANDLE_TYPE_SHARED
:
1258 type
= amdgpu_bo_handle_type_gem_flink_name
;
1260 case DRM_API_HANDLE_TYPE_FD
:
1261 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1267 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1271 /* Get initial domains. */
1272 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1276 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1277 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
1281 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1285 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1286 initial
|= RADEON_DOMAIN_VRAM
;
1287 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1288 initial
|= RADEON_DOMAIN_GTT
;
1291 pipe_reference_init(&bo
->base
.reference
, 1);
1292 bo
->base
.alignment
= info
.phys_alignment
;
1293 bo
->bo
= result
.buf_handle
;
1294 bo
->base
.size
= result
.alloc_size
;
1295 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1298 bo
->u
.real
.va_handle
= va_handle
;
1299 bo
->initial_domain
= initial
;
1300 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1301 bo
->is_shared
= true;
1304 *stride
= whandle
->stride
;
1306 *offset
= whandle
->offset
;
1308 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1309 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1310 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1311 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1313 amdgpu_add_buffer_to_global_list(bo
);
1318 amdgpu_va_range_free(va_handle
);
1321 amdgpu_bo_free(result
.buf_handle
);
1328 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1329 unsigned stride
, unsigned offset
,
1330 unsigned slice_size
,
1331 struct winsys_handle
*whandle
)
1333 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1334 enum amdgpu_bo_handle_type type
;
1337 /* Don't allow exports of slab entries and sparse buffers. */
1341 bo
->u
.real
.use_reusable_pool
= false;
1343 switch (whandle
->type
) {
1344 case DRM_API_HANDLE_TYPE_SHARED
:
1345 type
= amdgpu_bo_handle_type_gem_flink_name
;
1347 case DRM_API_HANDLE_TYPE_FD
:
1348 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1350 case DRM_API_HANDLE_TYPE_KMS
:
1351 type
= amdgpu_bo_handle_type_kms
;
1357 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1361 whandle
->stride
= stride
;
1362 whandle
->offset
= offset
;
1363 whandle
->offset
+= slice_size
* whandle
->layer
;
1364 bo
->is_shared
= true;
1368 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1369 void *pointer
, uint64_t size
)
1371 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1372 amdgpu_bo_handle buf_handle
;
1373 struct amdgpu_winsys_bo
*bo
;
1375 amdgpu_va_handle va_handle
;
1377 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1381 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
1384 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1385 size
, 1 << 12, 0, &va
, &va_handle
, 0))
1386 goto error_va_alloc
;
1388 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
1391 /* Initialize it. */
1392 pipe_reference_init(&bo
->base
.reference
, 1);
1393 bo
->bo
= buf_handle
;
1394 bo
->base
.alignment
= 0;
1395 bo
->base
.size
= size
;
1396 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1398 bo
->user_ptr
= pointer
;
1400 bo
->u
.real
.va_handle
= va_handle
;
1401 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1402 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1404 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1406 amdgpu_add_buffer_to_global_list(bo
);
1408 return (struct pb_buffer
*)bo
;
1411 amdgpu_va_range_free(va_handle
);
1414 amdgpu_bo_free(buf_handle
);
1421 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1423 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1426 static bool amdgpu_bo_is_suballocated(struct pb_buffer
*buf
)
1428 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
1430 return !bo
->bo
&& !bo
->sparse
;
1433 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1435 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1438 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1440 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1441 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1442 ws
->base
.buffer_map
= amdgpu_bo_map
;
1443 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1444 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1445 ws
->base
.buffer_create
= amdgpu_bo_create
;
1446 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1447 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1448 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1449 ws
->base
.buffer_is_suballocated
= amdgpu_bo_is_suballocated
;
1450 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1451 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1452 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1453 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;