2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
41 /* Set to 1 for verbose output showing committed sparse buffer ranges. */
42 #define DEBUG_SPARSE_COMMITS 0
44 struct amdgpu_sparse_backing_chunk
{
48 static struct pb_buffer
*
49 amdgpu_bo_create(struct radeon_winsys
*rws
,
52 enum radeon_bo_domain domain
,
53 enum radeon_bo_flag flags
);
55 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
56 enum radeon_bo_usage usage
)
58 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
59 struct amdgpu_winsys
*ws
= bo
->ws
;
63 if (p_atomic_read(&bo
->num_active_ioctls
))
67 abs_timeout
= os_time_get_absolute_timeout(timeout
);
69 /* Wait if any ioctl is being submitted with this buffer. */
70 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
75 /* We can't use user fences for shared buffers, because user fences
76 * are local to this process only. If we want to wait for all buffer
77 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
79 bool buffer_busy
= true;
82 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
84 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
93 mtx_lock(&ws
->bo_fence_lock
);
95 for (idle_fences
= 0; idle_fences
< bo
->num_fences
; ++idle_fences
) {
96 if (!amdgpu_fence_wait(bo
->fences
[idle_fences
], 0, false))
100 /* Release the idle fences to avoid checking them again later. */
101 for (unsigned i
= 0; i
< idle_fences
; ++i
)
102 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
104 memmove(&bo
->fences
[0], &bo
->fences
[idle_fences
],
105 (bo
->num_fences
- idle_fences
) * sizeof(*bo
->fences
));
106 bo
->num_fences
-= idle_fences
;
108 buffer_idle
= !bo
->num_fences
;
109 mtx_unlock(&ws
->bo_fence_lock
);
113 bool buffer_idle
= true;
115 mtx_lock(&ws
->bo_fence_lock
);
116 while (bo
->num_fences
&& buffer_idle
) {
117 struct pipe_fence_handle
*fence
= NULL
;
118 bool fence_idle
= false;
120 amdgpu_fence_reference(&fence
, bo
->fences
[0]);
122 /* Wait for the fence. */
123 mtx_unlock(&ws
->bo_fence_lock
);
124 if (amdgpu_fence_wait(fence
, abs_timeout
, true))
128 mtx_lock(&ws
->bo_fence_lock
);
130 /* Release an idle fence to avoid checking it again later, keeping in
131 * mind that the fence array may have been modified by other threads.
133 if (fence_idle
&& bo
->num_fences
&& bo
->fences
[0] == fence
) {
134 amdgpu_fence_reference(&bo
->fences
[0], NULL
);
135 memmove(&bo
->fences
[0], &bo
->fences
[1],
136 (bo
->num_fences
- 1) * sizeof(*bo
->fences
));
140 amdgpu_fence_reference(&fence
, NULL
);
142 mtx_unlock(&ws
->bo_fence_lock
);
148 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
149 struct pb_buffer
*buf
)
151 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
154 static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo
*bo
)
156 for (unsigned i
= 0; i
< bo
->num_fences
; ++i
)
157 amdgpu_fence_reference(&bo
->fences
[i
], NULL
);
164 void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
166 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
168 assert(bo
->bo
&& "must not be called for slab entries");
170 mtx_lock(&bo
->ws
->global_bo_list_lock
);
171 LIST_DEL(&bo
->u
.real
.global_list_item
);
172 bo
->ws
->num_buffers
--;
173 mtx_unlock(&bo
->ws
->global_bo_list_lock
);
175 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
176 amdgpu_va_range_free(bo
->u
.real
.va_handle
);
177 amdgpu_bo_free(bo
->bo
);
179 amdgpu_bo_remove_fences(bo
);
181 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
182 bo
->ws
->allocated_vram
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
183 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
184 bo
->ws
->allocated_gtt
-= align64(bo
->base
.size
, bo
->ws
->info
.gart_page_size
);
186 if (bo
->u
.real
.map_count
>= 1) {
187 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
188 bo
->ws
->mapped_vram
-= bo
->base
.size
;
189 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
190 bo
->ws
->mapped_gtt
-= bo
->base
.size
;
191 bo
->ws
->num_mapped_buffers
--;
197 static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf
)
199 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
201 assert(bo
->bo
); /* slab buffers have a separate vtbl */
203 if (bo
->u
.real
.use_reusable_pool
)
204 pb_cache_add_buffer(&bo
->u
.real
.cache_entry
);
206 amdgpu_bo_destroy(_buf
);
209 static void *amdgpu_bo_map(struct pb_buffer
*buf
,
210 struct radeon_winsys_cs
*rcs
,
211 enum pipe_transfer_usage usage
)
213 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
214 struct amdgpu_winsys_bo
*real
;
215 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
222 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
223 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
224 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
225 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
226 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
229 * Since we are mapping for read, we don't need to wait
230 * if the GPU is using the buffer for read too
231 * (neither one is changing it).
233 * Only check whether the buffer is being used for write. */
234 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
235 RADEON_USAGE_WRITE
)) {
236 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
240 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
241 RADEON_USAGE_WRITE
)) {
245 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
246 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
250 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
251 RADEON_USAGE_READWRITE
)) {
256 uint64_t time
= os_time_get_nano();
258 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
261 * Since we are mapping for read, we don't need to wait
262 * if the GPU is using the buffer for read too
263 * (neither one is changing it).
265 * Only check whether the buffer is being used for write. */
267 if (amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
268 RADEON_USAGE_WRITE
)) {
269 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
271 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
272 if (p_atomic_read(&bo
->num_active_ioctls
))
273 amdgpu_cs_sync_flush(rcs
);
277 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
280 /* Mapping for write. */
282 if (amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
283 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
285 /* Try to avoid busy-waiting in amdgpu_bo_wait. */
286 if (p_atomic_read(&bo
->num_active_ioctls
))
287 amdgpu_cs_sync_flush(rcs
);
291 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
292 RADEON_USAGE_READWRITE
);
295 bo
->ws
->buffer_wait_time
+= os_time_get_nano() - time
;
299 /* If the buffer is created from user memory, return the user pointer. */
306 real
= bo
->u
.slab
.real
;
307 offset
= bo
->va
- real
->va
;
310 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
312 /* Clear the cache and try again. */
313 pb_cache_release_all_buffers(&real
->ws
->bo_cache
);
314 r
= amdgpu_bo_cpu_map(real
->bo
, &cpu
);
319 if (p_atomic_inc_return(&real
->u
.real
.map_count
) == 1) {
320 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
321 real
->ws
->mapped_vram
+= real
->base
.size
;
322 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
323 real
->ws
->mapped_gtt
+= real
->base
.size
;
324 real
->ws
->num_mapped_buffers
++;
326 return (uint8_t*)cpu
+ offset
;
329 static void amdgpu_bo_unmap(struct pb_buffer
*buf
)
331 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
332 struct amdgpu_winsys_bo
*real
;
339 real
= bo
->bo
? bo
: bo
->u
.slab
.real
;
341 if (p_atomic_dec_zero(&real
->u
.real
.map_count
)) {
342 if (real
->initial_domain
& RADEON_DOMAIN_VRAM
)
343 real
->ws
->mapped_vram
-= real
->base
.size
;
344 else if (real
->initial_domain
& RADEON_DOMAIN_GTT
)
345 real
->ws
->mapped_gtt
-= real
->base
.size
;
346 real
->ws
->num_mapped_buffers
--;
349 amdgpu_bo_cpu_unmap(real
->bo
);
352 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
353 amdgpu_bo_destroy_or_cache
354 /* other functions are never called */
357 static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo
*bo
)
359 struct amdgpu_winsys
*ws
= bo
->ws
;
363 mtx_lock(&ws
->global_bo_list_lock
);
364 LIST_ADDTAIL(&bo
->u
.real
.global_list_item
, &ws
->global_bo_list
);
366 mtx_unlock(&ws
->global_bo_list_lock
);
369 static struct amdgpu_winsys_bo
*amdgpu_create_bo(struct amdgpu_winsys
*ws
,
373 enum radeon_bo_domain initial_domain
,
375 unsigned pb_cache_bucket
)
377 struct amdgpu_bo_alloc_request request
= {0};
378 amdgpu_bo_handle buf_handle
;
380 struct amdgpu_winsys_bo
*bo
;
381 amdgpu_va_handle va_handle
;
382 unsigned va_gap_size
;
385 assert(initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
386 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
391 pb_cache_init_entry(&ws
->bo_cache
, &bo
->u
.real
.cache_entry
, &bo
->base
,
393 request
.alloc_size
= size
;
394 request
.phys_alignment
= alignment
;
396 if (initial_domain
& RADEON_DOMAIN_VRAM
)
397 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
398 if (initial_domain
& RADEON_DOMAIN_GTT
)
399 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
401 if (flags
& RADEON_FLAG_CPU_ACCESS
)
402 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
403 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
404 request
.flags
|= AMDGPU_GEM_CREATE_NO_CPU_ACCESS
;
405 if (flags
& RADEON_FLAG_GTT_WC
)
406 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
408 r
= amdgpu_bo_alloc(ws
->dev
, &request
, &buf_handle
);
410 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
411 fprintf(stderr
, "amdgpu: size : %"PRIu64
" bytes\n", size
);
412 fprintf(stderr
, "amdgpu: alignment : %u bytes\n", alignment
);
413 fprintf(stderr
, "amdgpu: domains : %u\n", initial_domain
);
417 va_gap_size
= ws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
418 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
419 size
+ va_gap_size
, alignment
, 0, &va
, &va_handle
, 0);
423 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
427 pipe_reference_init(&bo
->base
.reference
, 1);
428 bo
->base
.alignment
= alignment
;
429 bo
->base
.usage
= usage
;
430 bo
->base
.size
= size
;
431 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
435 bo
->u
.real
.va_handle
= va_handle
;
436 bo
->initial_domain
= initial_domain
;
437 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
439 if (initial_domain
& RADEON_DOMAIN_VRAM
)
440 ws
->allocated_vram
+= align64(size
, ws
->info
.gart_page_size
);
441 else if (initial_domain
& RADEON_DOMAIN_GTT
)
442 ws
->allocated_gtt
+= align64(size
, ws
->info
.gart_page_size
);
444 amdgpu_add_buffer_to_global_list(bo
);
449 amdgpu_va_range_free(va_handle
);
452 amdgpu_bo_free(buf_handle
);
459 bool amdgpu_bo_can_reclaim(struct pb_buffer
*_buf
)
461 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
463 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
467 return amdgpu_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
470 bool amdgpu_bo_can_reclaim_slab(void *priv
, struct pb_slab_entry
*entry
)
472 struct amdgpu_winsys_bo
*bo
= NULL
; /* fix container_of */
473 bo
= container_of(entry
, bo
, u
.slab
.entry
);
475 return amdgpu_bo_can_reclaim(&bo
->base
);
478 static void amdgpu_bo_slab_destroy(struct pb_buffer
*_buf
)
480 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
484 pb_slab_free(&bo
->ws
->bo_slabs
, &bo
->u
.slab
.entry
);
487 static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl
= {
488 amdgpu_bo_slab_destroy
489 /* other functions are never called */
492 struct pb_slab
*amdgpu_bo_slab_alloc(void *priv
, unsigned heap
,
494 unsigned group_index
)
496 struct amdgpu_winsys
*ws
= priv
;
497 struct amdgpu_slab
*slab
= CALLOC_STRUCT(amdgpu_slab
);
498 enum radeon_bo_domain domains
;
499 enum radeon_bo_flag flags
= 0;
506 flags
|= RADEON_FLAG_GTT_WC
;
508 flags
|= RADEON_FLAG_CPU_ACCESS
;
512 domains
= RADEON_DOMAIN_VRAM
;
516 domains
= RADEON_DOMAIN_VRAM_GTT
;
519 domains
= RADEON_DOMAIN_GTT
;
523 slab
->buffer
= amdgpu_winsys_bo(amdgpu_bo_create(&ws
->base
,
524 64 * 1024, 64 * 1024,
529 assert(slab
->buffer
->bo
);
531 slab
->base
.num_entries
= slab
->buffer
->base
.size
/ entry_size
;
532 slab
->base
.num_free
= slab
->base
.num_entries
;
533 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
537 LIST_INITHEAD(&slab
->base
.free
);
539 base_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, slab
->base
.num_entries
);
541 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
542 struct amdgpu_winsys_bo
*bo
= &slab
->entries
[i
];
544 bo
->base
.alignment
= entry_size
;
545 bo
->base
.usage
= slab
->buffer
->base
.usage
;
546 bo
->base
.size
= entry_size
;
547 bo
->base
.vtbl
= &amdgpu_winsys_bo_slab_vtbl
;
549 bo
->va
= slab
->buffer
->va
+ i
* entry_size
;
550 bo
->initial_domain
= domains
;
551 bo
->unique_id
= base_id
+ i
;
552 bo
->u
.slab
.entry
.slab
= &slab
->base
;
553 bo
->u
.slab
.entry
.group_index
= group_index
;
554 bo
->u
.slab
.real
= slab
->buffer
;
556 LIST_ADDTAIL(&bo
->u
.slab
.entry
.head
, &slab
->base
.free
);
562 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
568 void amdgpu_bo_slab_free(void *priv
, struct pb_slab
*pslab
)
570 struct amdgpu_slab
*slab
= amdgpu_slab(pslab
);
572 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
)
573 amdgpu_bo_remove_fences(&slab
->entries
[i
]);
576 amdgpu_winsys_bo_reference(&slab
->buffer
, NULL
);
580 #if DEBUG_SPARSE_COMMITS
582 sparse_dump(struct amdgpu_winsys_bo
*bo
, const char *func
)
584 fprintf(stderr
, "%s: %p (size=%"PRIu64
", num_va_pages=%u) @ %s\n"
586 __func__
, bo
, bo
->base
.size
, bo
->u
.sparse
.num_va_pages
, func
);
588 struct amdgpu_sparse_backing
*span_backing
= NULL
;
589 uint32_t span_first_backing_page
= 0;
590 uint32_t span_first_va_page
= 0;
591 uint32_t va_page
= 0;
594 struct amdgpu_sparse_backing
*backing
= 0;
595 uint32_t backing_page
= 0;
597 if (va_page
< bo
->u
.sparse
.num_va_pages
) {
598 backing
= bo
->u
.sparse
.commitments
[va_page
].backing
;
599 backing_page
= bo
->u
.sparse
.commitments
[va_page
].page
;
603 (backing
!= span_backing
||
604 backing_page
!= span_first_backing_page
+ (va_page
- span_first_va_page
))) {
605 fprintf(stderr
, " %u..%u: backing=%p:%u..%u\n",
606 span_first_va_page
, va_page
- 1, span_backing
,
607 span_first_backing_page
,
608 span_first_backing_page
+ (va_page
- span_first_va_page
) - 1);
613 if (va_page
>= bo
->u
.sparse
.num_va_pages
)
616 if (backing
&& !span_backing
) {
617 span_backing
= backing
;
618 span_first_backing_page
= backing_page
;
619 span_first_va_page
= va_page
;
625 fprintf(stderr
, "Backing:\n");
627 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
628 fprintf(stderr
, " %p (size=%"PRIu64
")\n", backing
, backing
->bo
->base
.size
);
629 for (unsigned i
= 0; i
< backing
->num_chunks
; ++i
)
630 fprintf(stderr
, " %u..%u\n", backing
->chunks
[i
].begin
, backing
->chunks
[i
].end
);
636 * Attempt to allocate the given number of backing pages. Fewer pages may be
637 * allocated (depending on the fragmentation of existing backing buffers),
638 * which will be reflected by a change to *pnum_pages.
640 static struct amdgpu_sparse_backing
*
641 sparse_backing_alloc(struct amdgpu_winsys_bo
*bo
, uint32_t *pstart_page
, uint32_t *pnum_pages
)
643 struct amdgpu_sparse_backing
*best_backing
;
645 uint32_t best_num_pages
;
651 /* This is a very simple and inefficient best-fit algorithm. */
652 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
653 for (unsigned idx
= 0; idx
< backing
->num_chunks
; ++idx
) {
654 uint32_t cur_num_pages
= backing
->chunks
[idx
].end
- backing
->chunks
[idx
].begin
;
655 if ((best_num_pages
< *pnum_pages
&& cur_num_pages
> best_num_pages
) ||
656 (best_num_pages
> *pnum_pages
&& cur_num_pages
< best_num_pages
)) {
657 best_backing
= backing
;
659 best_num_pages
= cur_num_pages
;
664 /* Allocate a new backing buffer if necessary. */
666 struct pb_buffer
*buf
;
670 best_backing
= CALLOC_STRUCT(amdgpu_sparse_backing
);
674 best_backing
->max_chunks
= 4;
675 best_backing
->chunks
= CALLOC(best_backing
->max_chunks
,
676 sizeof(*best_backing
->chunks
));
677 if (!best_backing
->chunks
) {
682 assert(bo
->u
.sparse
.num_backing_pages
< DIV_ROUND_UP(bo
->base
.size
, RADEON_SPARSE_PAGE_SIZE
));
684 size
= MIN3(bo
->base
.size
/ 16,
686 bo
->base
.size
- (uint64_t)bo
->u
.sparse
.num_backing_pages
* RADEON_SPARSE_PAGE_SIZE
);
687 size
= MAX2(size
, RADEON_SPARSE_PAGE_SIZE
);
689 buf
= amdgpu_bo_create(&bo
->ws
->base
, size
, RADEON_SPARSE_PAGE_SIZE
,
691 bo
->u
.sparse
.flags
| RADEON_FLAG_HANDLE
);
693 FREE(best_backing
->chunks
);
698 /* We might have gotten a bigger buffer than requested via caching. */
699 pages
= buf
->size
/ RADEON_SPARSE_PAGE_SIZE
;
701 best_backing
->bo
= amdgpu_winsys_bo(buf
);
702 best_backing
->num_chunks
= 1;
703 best_backing
->chunks
[0].begin
= 0;
704 best_backing
->chunks
[0].end
= pages
;
706 list_add(&best_backing
->list
, &bo
->u
.sparse
.backing
);
707 bo
->u
.sparse
.num_backing_pages
+= pages
;
710 best_num_pages
= pages
;
713 *pnum_pages
= MIN2(*pnum_pages
, best_num_pages
);
714 *pstart_page
= best_backing
->chunks
[best_idx
].begin
;
715 best_backing
->chunks
[best_idx
].begin
+= *pnum_pages
;
717 if (best_backing
->chunks
[best_idx
].begin
>= best_backing
->chunks
[best_idx
].end
) {
718 memmove(&best_backing
->chunks
[best_idx
], &best_backing
->chunks
[best_idx
+ 1],
719 sizeof(*best_backing
->chunks
) * (best_backing
->num_chunks
- best_idx
- 1));
720 best_backing
->num_chunks
--;
727 sparse_free_backing_buffer(struct amdgpu_winsys_bo
*bo
,
728 struct amdgpu_sparse_backing
*backing
)
730 struct amdgpu_winsys
*ws
= backing
->bo
->ws
;
732 bo
->u
.sparse
.num_backing_pages
-= backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
;
734 mtx_lock(&ws
->bo_fence_lock
);
735 amdgpu_add_fences(backing
->bo
, bo
->num_fences
, bo
->fences
);
736 mtx_unlock(&ws
->bo_fence_lock
);
738 list_del(&backing
->list
);
739 amdgpu_winsys_bo_reference(&backing
->bo
, NULL
);
740 FREE(backing
->chunks
);
745 * Return a range of pages from the given backing buffer back into the
749 sparse_backing_free(struct amdgpu_winsys_bo
*bo
,
750 struct amdgpu_sparse_backing
*backing
,
751 uint32_t start_page
, uint32_t num_pages
)
753 uint32_t end_page
= start_page
+ num_pages
;
755 unsigned high
= backing
->num_chunks
;
757 /* Find the first chunk with begin >= start_page. */
759 unsigned mid
= low
+ (high
- low
) / 2;
761 if (backing
->chunks
[mid
].begin
>= start_page
)
767 assert(low
>= backing
->num_chunks
|| end_page
<= backing
->chunks
[low
].begin
);
768 assert(low
== 0 || backing
->chunks
[low
- 1].end
<= start_page
);
770 if (low
> 0 && backing
->chunks
[low
- 1].end
== start_page
) {
771 backing
->chunks
[low
- 1].end
= end_page
;
773 if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
774 backing
->chunks
[low
- 1].end
= backing
->chunks
[low
].end
;
775 memmove(&backing
->chunks
[low
], &backing
->chunks
[low
+ 1],
776 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
- 1));
777 backing
->num_chunks
--;
779 } else if (low
< backing
->num_chunks
&& end_page
== backing
->chunks
[low
].begin
) {
780 backing
->chunks
[low
].begin
= start_page
;
782 if (backing
->num_chunks
>= backing
->max_chunks
) {
783 unsigned new_max_chunks
= 2 * backing
->max_chunks
;
784 struct amdgpu_sparse_backing_chunk
*new_chunks
=
785 REALLOC(backing
->chunks
,
786 sizeof(*backing
->chunks
) * backing
->max_chunks
,
787 sizeof(*backing
->chunks
) * new_max_chunks
);
791 backing
->max_chunks
= new_max_chunks
;
792 backing
->chunks
= new_chunks
;
795 memmove(&backing
->chunks
[low
+ 1], &backing
->chunks
[low
],
796 sizeof(*backing
->chunks
) * (backing
->num_chunks
- low
));
797 backing
->chunks
[low
].begin
= start_page
;
798 backing
->chunks
[low
].end
= end_page
;
799 backing
->num_chunks
++;
802 if (backing
->num_chunks
== 1 && backing
->chunks
[0].begin
== 0 &&
803 backing
->chunks
[0].end
== backing
->bo
->base
.size
/ RADEON_SPARSE_PAGE_SIZE
)
804 sparse_free_backing_buffer(bo
, backing
);
809 static void amdgpu_bo_sparse_destroy(struct pb_buffer
*_buf
)
811 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
814 assert(!bo
->bo
&& bo
->sparse
);
816 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
817 (uint64_t)bo
->u
.sparse
.num_va_pages
* RADEON_SPARSE_PAGE_SIZE
,
818 bo
->va
, 0, AMDGPU_VA_OP_CLEAR
);
820 fprintf(stderr
, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r
);
823 while (!list_empty(&bo
->u
.sparse
.backing
)) {
824 struct amdgpu_sparse_backing
*dummy
= NULL
;
825 sparse_free_backing_buffer(bo
,
826 container_of(bo
->u
.sparse
.backing
.next
,
830 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
831 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
832 FREE(bo
->u
.sparse
.commitments
);
836 static const struct pb_vtbl amdgpu_winsys_bo_sparse_vtbl
= {
837 amdgpu_bo_sparse_destroy
838 /* other functions are never called */
841 static struct pb_buffer
*
842 amdgpu_bo_sparse_create(struct amdgpu_winsys
*ws
, uint64_t size
,
843 enum radeon_bo_domain domain
,
844 enum radeon_bo_flag flags
)
846 struct amdgpu_winsys_bo
*bo
;
848 uint64_t va_gap_size
;
851 /* We use 32-bit page numbers; refuse to attempt allocating sparse buffers
852 * that exceed this limit. This is not really a restriction: we don't have
853 * that much virtual address space anyway.
855 if (size
> (uint64_t)INT32_MAX
* RADEON_SPARSE_PAGE_SIZE
)
858 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
862 pipe_reference_init(&bo
->base
.reference
, 1);
863 bo
->base
.alignment
= RADEON_SPARSE_PAGE_SIZE
;
864 bo
->base
.size
= size
;
865 bo
->base
.vtbl
= &amdgpu_winsys_bo_sparse_vtbl
;
867 bo
->initial_domain
= domain
;
868 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
870 bo
->u
.sparse
.flags
= flags
& ~RADEON_FLAG_SPARSE
;
872 bo
->u
.sparse
.num_va_pages
= DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
873 bo
->u
.sparse
.commitments
= CALLOC(bo
->u
.sparse
.num_va_pages
,
874 sizeof(*bo
->u
.sparse
.commitments
));
875 if (!bo
->u
.sparse
.commitments
)
876 goto error_alloc_commitments
;
878 mtx_init(&bo
->u
.sparse
.commit_lock
, mtx_plain
);
879 LIST_INITHEAD(&bo
->u
.sparse
.backing
);
881 /* For simplicity, we always map a multiple of the page size. */
882 map_size
= align64(size
, RADEON_SPARSE_PAGE_SIZE
);
883 va_gap_size
= ws
->check_vm
? 4 * RADEON_SPARSE_PAGE_SIZE
: 0;
884 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
885 map_size
+ va_gap_size
, RADEON_SPARSE_PAGE_SIZE
,
886 0, &bo
->va
, &bo
->u
.sparse
.va_handle
, 0);
890 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0, size
, bo
->va
,
891 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_MAP
);
898 amdgpu_va_range_free(bo
->u
.sparse
.va_handle
);
900 mtx_destroy(&bo
->u
.sparse
.commit_lock
);
901 FREE(bo
->u
.sparse
.commitments
);
902 error_alloc_commitments
:
908 amdgpu_bo_sparse_commit(struct pb_buffer
*buf
, uint64_t offset
, uint64_t size
,
911 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buf
);
912 struct amdgpu_sparse_commitment
*comm
;
913 uint32_t va_page
, end_va_page
;
918 assert(offset
% RADEON_SPARSE_PAGE_SIZE
== 0);
919 assert(offset
<= bo
->base
.size
);
920 assert(size
<= bo
->base
.size
- offset
);
921 assert(size
% RADEON_SPARSE_PAGE_SIZE
== 0 || offset
+ size
== bo
->base
.size
);
923 comm
= bo
->u
.sparse
.commitments
;
924 va_page
= offset
/ RADEON_SPARSE_PAGE_SIZE
;
925 end_va_page
= va_page
+ DIV_ROUND_UP(size
, RADEON_SPARSE_PAGE_SIZE
);
927 mtx_lock(&bo
->u
.sparse
.commit_lock
);
929 #if DEBUG_SPARSE_COMMITS
930 sparse_dump(bo
, __func__
);
934 while (va_page
< end_va_page
) {
935 uint32_t span_va_page
;
937 /* Skip pages that are already committed. */
938 if (comm
[va_page
].backing
) {
943 /* Determine length of uncommitted span. */
944 span_va_page
= va_page
;
945 while (va_page
< end_va_page
&& !comm
[va_page
].backing
)
948 /* Fill the uncommitted span with chunks of backing memory. */
949 while (span_va_page
< va_page
) {
950 struct amdgpu_sparse_backing
*backing
;
951 uint32_t backing_start
, backing_size
;
953 backing_size
= va_page
- span_va_page
;
954 backing
= sparse_backing_alloc(bo
, &backing_start
, &backing_size
);
960 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, backing
->bo
->bo
,
961 (uint64_t)backing_start
* RADEON_SPARSE_PAGE_SIZE
,
962 (uint64_t)backing_size
* RADEON_SPARSE_PAGE_SIZE
,
963 bo
->va
+ (uint64_t)span_va_page
* RADEON_SPARSE_PAGE_SIZE
,
964 AMDGPU_VM_PAGE_READABLE
|
965 AMDGPU_VM_PAGE_WRITEABLE
|
966 AMDGPU_VM_PAGE_EXECUTABLE
,
967 AMDGPU_VA_OP_REPLACE
);
969 ok
= sparse_backing_free(bo
, backing
, backing_start
, backing_size
);
970 assert(ok
&& "sufficient memory should already be allocated");
976 while (backing_size
) {
977 comm
[span_va_page
].backing
= backing
;
978 comm
[span_va_page
].page
= backing_start
;
986 r
= amdgpu_bo_va_op_raw(bo
->ws
->dev
, NULL
, 0,
987 (uint64_t)(end_va_page
- va_page
) * RADEON_SPARSE_PAGE_SIZE
,
988 bo
->va
+ (uint64_t)va_page
* RADEON_SPARSE_PAGE_SIZE
,
989 AMDGPU_VM_PAGE_PRT
, AMDGPU_VA_OP_REPLACE
);
995 while (va_page
< end_va_page
) {
996 struct amdgpu_sparse_backing
*backing
;
997 uint32_t backing_start
;
1000 /* Skip pages that are already uncommitted. */
1001 if (!comm
[va_page
].backing
) {
1006 /* Group contiguous spans of pages. */
1007 backing
= comm
[va_page
].backing
;
1008 backing_start
= comm
[va_page
].page
;
1009 comm
[va_page
].backing
= NULL
;
1014 while (va_page
< end_va_page
&&
1015 comm
[va_page
].backing
== backing
&&
1016 comm
[va_page
].page
== backing_start
+ span_pages
) {
1017 comm
[va_page
].backing
= NULL
;
1022 if (!sparse_backing_free(bo
, backing
, backing_start
, span_pages
)) {
1023 /* Couldn't allocate tracking data structures, so we have to leak */
1024 fprintf(stderr
, "amdgpu: leaking PRT backing memory\n");
1031 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1036 static unsigned eg_tile_split(unsigned tile_split
)
1038 switch (tile_split
) {
1039 case 0: tile_split
= 64; break;
1040 case 1: tile_split
= 128; break;
1041 case 2: tile_split
= 256; break;
1042 case 3: tile_split
= 512; break;
1044 case 4: tile_split
= 1024; break;
1045 case 5: tile_split
= 2048; break;
1046 case 6: tile_split
= 4096; break;
1051 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
1053 switch (eg_tile_split
) {
1059 case 1024: return 4;
1060 case 2048: return 5;
1061 case 4096: return 6;
1065 static void amdgpu_buffer_get_metadata(struct pb_buffer
*_buf
,
1066 struct radeon_bo_metadata
*md
)
1068 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1069 struct amdgpu_bo_info info
= {0};
1070 uint64_t tiling_flags
;
1073 assert(bo
->bo
&& "must not be called for slab entries");
1075 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
1079 tiling_flags
= info
.metadata
.tiling_info
;
1081 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1082 md
->u
.gfx9
.swizzle_mode
= AMDGPU_TILING_GET(tiling_flags
, SWIZZLE_MODE
);
1084 md
->u
.legacy
.microtile
= RADEON_LAYOUT_LINEAR
;
1085 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_LINEAR
;
1087 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
1088 md
->u
.legacy
.macrotile
= RADEON_LAYOUT_TILED
;
1089 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
1090 md
->u
.legacy
.microtile
= RADEON_LAYOUT_TILED
;
1092 md
->u
.legacy
.pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
1093 md
->u
.legacy
.bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
1094 md
->u
.legacy
.bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
1095 md
->u
.legacy
.tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
1096 md
->u
.legacy
.mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
1097 md
->u
.legacy
.num_banks
= 2 << AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
1098 md
->u
.legacy
.scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
1101 md
->size_metadata
= info
.metadata
.size_metadata
;
1102 memcpy(md
->metadata
, info
.metadata
.umd_metadata
, sizeof(md
->metadata
));
1105 static void amdgpu_buffer_set_metadata(struct pb_buffer
*_buf
,
1106 struct radeon_bo_metadata
*md
)
1108 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
1109 struct amdgpu_bo_metadata metadata
= {0};
1110 uint64_t tiling_flags
= 0;
1112 assert(bo
->bo
&& "must not be called for slab entries");
1114 if (bo
->ws
->info
.chip_class
>= GFX9
) {
1115 tiling_flags
|= AMDGPU_TILING_SET(SWIZZLE_MODE
, md
->u
.gfx9
.swizzle_mode
);
1117 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1118 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
1119 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1120 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
1122 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
1124 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, md
->u
.legacy
.pipe_config
);
1125 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(md
->u
.legacy
.bankw
));
1126 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(md
->u
.legacy
.bankh
));
1127 if (md
->u
.legacy
.tile_split
)
1128 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(md
->u
.legacy
.tile_split
));
1129 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(md
->u
.legacy
.mtilea
));
1130 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(md
->u
.legacy
.num_banks
)-1);
1132 if (md
->u
.legacy
.scanout
)
1133 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
1135 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
1138 metadata
.tiling_info
= tiling_flags
;
1139 metadata
.size_metadata
= md
->size_metadata
;
1140 memcpy(metadata
.umd_metadata
, md
->metadata
, sizeof(md
->metadata
));
1142 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
1145 static struct pb_buffer
*
1146 amdgpu_bo_create(struct radeon_winsys
*rws
,
1149 enum radeon_bo_domain domain
,
1150 enum radeon_bo_flag flags
)
1152 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1153 struct amdgpu_winsys_bo
*bo
;
1154 unsigned usage
= 0, pb_cache_bucket
;
1156 /* Sub-allocate small buffers from slabs. */
1157 if (!(flags
& (RADEON_FLAG_HANDLE
| RADEON_FLAG_SPARSE
)) &&
1158 size
<= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2
) &&
1159 alignment
<= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2
, util_next_power_of_two(size
))) {
1160 struct pb_slab_entry
*entry
;
1163 if (flags
& RADEON_FLAG_GTT_WC
)
1165 if (flags
& RADEON_FLAG_CPU_ACCESS
)
1167 if (flags
& ~(RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
))
1171 case RADEON_DOMAIN_VRAM
:
1174 case RADEON_DOMAIN_VRAM_GTT
:
1177 case RADEON_DOMAIN_GTT
:
1184 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1186 /* Clear the cache and try again. */
1187 pb_cache_release_all_buffers(&ws
->bo_cache
);
1189 entry
= pb_slab_alloc(&ws
->bo_slabs
, size
, heap
);
1195 bo
= container_of(entry
, bo
, u
.slab
.entry
);
1197 pipe_reference_init(&bo
->base
.reference
, 1);
1203 if (flags
& RADEON_FLAG_SPARSE
) {
1204 assert(RADEON_SPARSE_PAGE_SIZE
% alignment
== 0);
1205 assert(!(flags
& RADEON_FLAG_CPU_ACCESS
));
1207 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
1209 return amdgpu_bo_sparse_create(ws
, size
, domain
, flags
);
1212 /* This flag is irrelevant for the cache. */
1213 flags
&= ~RADEON_FLAG_HANDLE
;
1215 /* Align size to page size. This is the minimum alignment for normal
1216 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
1217 * like constant/uniform buffers, can benefit from better and more reuse.
1219 size
= align64(size
, ws
->info
.gart_page_size
);
1220 alignment
= align(alignment
, ws
->info
.gart_page_size
);
1222 /* Only set one usage bit each for domains and flags, or the cache manager
1223 * might consider different sets of domains / flags compatible
1225 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
1228 usage
= domain
>> 1;
1229 assert(flags
< sizeof(usage
) * 8 - 3);
1230 usage
|= 1 << (flags
+ 3);
1232 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
1233 pb_cache_bucket
= 0;
1234 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
1235 pb_cache_bucket
+= 1;
1236 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
1237 pb_cache_bucket
+= 2;
1238 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
1240 /* Get a buffer from the cache. */
1241 bo
= (struct amdgpu_winsys_bo
*)
1242 pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
,
1247 /* Create a new one. */
1248 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1251 /* Clear the cache and try again. */
1252 pb_slabs_reclaim(&ws
->bo_slabs
);
1253 pb_cache_release_all_buffers(&ws
->bo_cache
);
1254 bo
= amdgpu_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
1260 bo
->u
.real
.use_reusable_pool
= true;
1264 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
1265 struct winsys_handle
*whandle
,
1269 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1270 struct amdgpu_winsys_bo
*bo
;
1271 enum amdgpu_bo_handle_type type
;
1272 struct amdgpu_bo_import_result result
= {0};
1274 amdgpu_va_handle va_handle
;
1275 struct amdgpu_bo_info info
= {0};
1276 enum radeon_bo_domain initial
= 0;
1279 /* Initialize the structure. */
1280 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1285 switch (whandle
->type
) {
1286 case DRM_API_HANDLE_TYPE_SHARED
:
1287 type
= amdgpu_bo_handle_type_gem_flink_name
;
1289 case DRM_API_HANDLE_TYPE_FD
:
1290 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1296 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
1300 /* Get initial domains. */
1301 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
1305 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1306 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
1310 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
1314 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
1315 initial
|= RADEON_DOMAIN_VRAM
;
1316 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
1317 initial
|= RADEON_DOMAIN_GTT
;
1320 pipe_reference_init(&bo
->base
.reference
, 1);
1321 bo
->base
.alignment
= info
.phys_alignment
;
1322 bo
->bo
= result
.buf_handle
;
1323 bo
->base
.size
= result
.alloc_size
;
1324 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1327 bo
->u
.real
.va_handle
= va_handle
;
1328 bo
->initial_domain
= initial
;
1329 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1330 bo
->is_shared
= true;
1333 *stride
= whandle
->stride
;
1335 *offset
= whandle
->offset
;
1337 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1338 ws
->allocated_vram
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1339 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1340 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1342 amdgpu_add_buffer_to_global_list(bo
);
1347 amdgpu_va_range_free(va_handle
);
1350 amdgpu_bo_free(result
.buf_handle
);
1357 static bool amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
1358 unsigned stride
, unsigned offset
,
1359 unsigned slice_size
,
1360 struct winsys_handle
*whandle
)
1362 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(buffer
);
1363 enum amdgpu_bo_handle_type type
;
1367 offset
+= bo
->va
- bo
->u
.slab
.real
->va
;
1368 bo
= bo
->u
.slab
.real
;
1371 bo
->u
.real
.use_reusable_pool
= false;
1373 switch (whandle
->type
) {
1374 case DRM_API_HANDLE_TYPE_SHARED
:
1375 type
= amdgpu_bo_handle_type_gem_flink_name
;
1377 case DRM_API_HANDLE_TYPE_FD
:
1378 type
= amdgpu_bo_handle_type_dma_buf_fd
;
1380 case DRM_API_HANDLE_TYPE_KMS
:
1381 type
= amdgpu_bo_handle_type_kms
;
1387 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
1391 whandle
->stride
= stride
;
1392 whandle
->offset
= offset
;
1393 whandle
->offset
+= slice_size
* whandle
->layer
;
1394 bo
->is_shared
= true;
1398 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
1399 void *pointer
, uint64_t size
)
1401 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
1402 amdgpu_bo_handle buf_handle
;
1403 struct amdgpu_winsys_bo
*bo
;
1405 amdgpu_va_handle va_handle
;
1407 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
1411 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
1414 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
1415 size
, 1 << 12, 0, &va
, &va_handle
, 0))
1416 goto error_va_alloc
;
1418 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
1421 /* Initialize it. */
1422 pipe_reference_init(&bo
->base
.reference
, 1);
1423 bo
->bo
= buf_handle
;
1424 bo
->base
.alignment
= 0;
1425 bo
->base
.size
= size
;
1426 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
1428 bo
->user_ptr
= pointer
;
1430 bo
->u
.real
.va_handle
= va_handle
;
1431 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
1432 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
1434 ws
->allocated_gtt
+= align64(bo
->base
.size
, ws
->info
.gart_page_size
);
1436 amdgpu_add_buffer_to_global_list(bo
);
1438 return (struct pb_buffer
*)bo
;
1441 amdgpu_va_range_free(va_handle
);
1444 amdgpu_bo_free(buf_handle
);
1451 static bool amdgpu_bo_is_user_ptr(struct pb_buffer
*buf
)
1453 return ((struct amdgpu_winsys_bo
*)buf
)->user_ptr
!= NULL
;
1456 static uint64_t amdgpu_bo_get_va(struct pb_buffer
*buf
)
1458 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
1461 void amdgpu_bo_init_functions(struct amdgpu_winsys
*ws
)
1463 ws
->base
.buffer_set_metadata
= amdgpu_buffer_set_metadata
;
1464 ws
->base
.buffer_get_metadata
= amdgpu_buffer_get_metadata
;
1465 ws
->base
.buffer_map
= amdgpu_bo_map
;
1466 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
1467 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
1468 ws
->base
.buffer_create
= amdgpu_bo_create
;
1469 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
1470 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
1471 ws
->base
.buffer_is_user_ptr
= amdgpu_bo_is_user_ptr
;
1472 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
1473 ws
->base
.buffer_commit
= amdgpu_bo_sparse_commit
;
1474 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
1475 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;