2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
3 * Copyright © 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Marek Olšák <maraeo@gmail.com>
32 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
35 #include "state_tracker/drm_driver.h"
36 #include <amdgpu_drm.h>
40 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
;
42 static inline struct amdgpu_winsys_bo
*amdgpu_winsys_bo(struct pb_buffer
*bo
)
44 assert(bo
->vtbl
== &amdgpu_winsys_bo_vtbl
);
45 return (struct amdgpu_winsys_bo
*)bo
;
49 struct pb_manager base
;
50 struct amdgpu_winsys
*rws
;
53 static struct amdgpu_winsys
*get_winsys(struct pb_manager
*mgr
)
55 return ((struct amdgpu_bomgr
*)mgr
)->rws
;
58 static struct amdgpu_winsys_bo
*get_amdgpu_winsys_bo(struct pb_buffer
*_buf
)
60 struct amdgpu_winsys_bo
*bo
= NULL
;
62 if (_buf
->vtbl
== &amdgpu_winsys_bo_vtbl
) {
63 bo
= amdgpu_winsys_bo(_buf
);
65 struct pb_buffer
*base_buf
;
67 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
69 if (base_buf
->vtbl
== &amdgpu_winsys_bo_vtbl
)
70 bo
= amdgpu_winsys_bo(base_buf
);
76 static bool amdgpu_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
77 enum radeon_bo_usage usage
)
79 struct amdgpu_winsys_bo
*bo
= get_amdgpu_winsys_bo(_buf
);
80 struct amdgpu_winsys
*ws
= bo
->rws
;
84 /* We can't use user fences for shared buffers, because user fences
85 * are local to this process only. If we want to wait for all buffer
86 * uses in all processes, we have to use amdgpu_bo_wait_for_idle.
88 bool buffer_busy
= true;
91 r
= amdgpu_bo_wait_for_idle(bo
->bo
, timeout
, &buffer_busy
);
93 fprintf(stderr
, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__
,
99 /* Timeout == 0 is quite simple. */
100 pipe_mutex_lock(ws
->bo_fence_lock
);
101 for (i
= 0; i
< RING_LAST
; i
++)
103 if (amdgpu_fence_wait(bo
->fence
[i
], 0, false)) {
104 /* Release the idle fence to avoid checking it again later. */
105 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
107 pipe_mutex_unlock(ws
->bo_fence_lock
);
111 pipe_mutex_unlock(ws
->bo_fence_lock
);
115 struct pipe_fence_handle
*fence
[RING_LAST
] = {};
116 bool fence_idle
[RING_LAST
] = {};
117 bool buffer_idle
= true;
118 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
120 /* Take references to all fences, so that we can wait for them
121 * without the lock. */
122 pipe_mutex_lock(ws
->bo_fence_lock
);
123 for (i
= 0; i
< RING_LAST
; i
++)
124 amdgpu_fence_reference(&fence
[i
], bo
->fence
[i
]);
125 pipe_mutex_unlock(ws
->bo_fence_lock
);
127 /* Now wait for the fences. */
128 for (i
= 0; i
< RING_LAST
; i
++) {
130 if (amdgpu_fence_wait(fence
[i
], abs_timeout
, true))
131 fence_idle
[i
] = true;
137 /* Release idle fences to avoid checking them again later. */
138 pipe_mutex_lock(ws
->bo_fence_lock
);
139 for (i
= 0; i
< RING_LAST
; i
++) {
140 if (fence
[i
] == bo
->fence
[i
] && fence_idle
[i
])
141 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
143 amdgpu_fence_reference(&fence
[i
], NULL
);
145 pipe_mutex_unlock(ws
->bo_fence_lock
);
151 static enum radeon_bo_domain
amdgpu_bo_get_initial_domain(
152 struct radeon_winsys_cs_handle
*buf
)
154 return ((struct amdgpu_winsys_bo
*)buf
)->initial_domain
;
157 static void amdgpu_bo_destroy(struct pb_buffer
*_buf
)
159 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
162 amdgpu_bo_va_op(bo
->bo
, 0, bo
->base
.size
, bo
->va
, 0, AMDGPU_VA_OP_UNMAP
);
163 amdgpu_va_range_free(bo
->va_handle
);
164 amdgpu_bo_free(bo
->bo
);
166 for (i
= 0; i
< RING_LAST
; i
++)
167 amdgpu_fence_reference(&bo
->fence
[i
], NULL
);
169 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
170 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, bo
->rws
->gart_page_size
);
171 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
172 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, bo
->rws
->gart_page_size
);
176 static void *amdgpu_bo_map(struct radeon_winsys_cs_handle
*buf
,
177 struct radeon_winsys_cs
*rcs
,
178 enum pipe_transfer_usage usage
)
180 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
181 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
185 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
186 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
187 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
188 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
189 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
192 * Since we are mapping for read, we don't need to wait
193 * if the GPU is using the buffer for read too
194 * (neither one is changing it).
196 * Only check whether the buffer is being used for write. */
197 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
198 RADEON_USAGE_WRITE
)) {
199 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
203 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
204 RADEON_USAGE_WRITE
)) {
208 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
)) {
209 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
213 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0,
214 RADEON_USAGE_READWRITE
)) {
219 uint64_t time
= os_time_get_nano();
221 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
224 * Since we are mapping for read, we don't need to wait
225 * if the GPU is using the buffer for read too
226 * (neither one is changing it).
228 * Only check whether the buffer is being used for write. */
229 if (cs
&& amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
,
230 RADEON_USAGE_WRITE
)) {
231 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
233 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
236 /* Mapping for write. */
237 if (cs
&& amdgpu_bo_is_referenced_by_cs(cs
, bo
))
238 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
240 amdgpu_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
241 RADEON_USAGE_READWRITE
);
244 bo
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
248 /* If the buffer is created from user memory, return the user pointer. */
252 r
= amdgpu_bo_cpu_map(bo
->bo
, &cpu
);
253 return r
? NULL
: cpu
;
256 static void amdgpu_bo_unmap(struct radeon_winsys_cs_handle
*buf
)
258 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
260 amdgpu_bo_cpu_unmap(bo
->bo
);
263 static void amdgpu_bo_get_base_buffer(struct pb_buffer
*buf
,
264 struct pb_buffer
**base_buf
,
271 static enum pipe_error
amdgpu_bo_validate(struct pb_buffer
*_buf
,
272 struct pb_validate
*vl
,
279 static void amdgpu_bo_fence(struct pb_buffer
*buf
,
280 struct pipe_fence_handle
*fence
)
284 static const struct pb_vtbl amdgpu_winsys_bo_vtbl
= {
286 NULL
, /* never called */
287 NULL
, /* never called */
290 amdgpu_bo_get_base_buffer
,
293 static struct pb_buffer
*amdgpu_bomgr_create_bo(struct pb_manager
*_mgr
,
295 const struct pb_desc
*desc
)
297 struct amdgpu_winsys
*rws
= get_winsys(_mgr
);
298 struct amdgpu_bo_desc
*rdesc
= (struct amdgpu_bo_desc
*)desc
;
299 struct amdgpu_bo_alloc_request request
= {0};
300 amdgpu_bo_handle buf_handle
;
302 struct amdgpu_winsys_bo
*bo
;
303 amdgpu_va_handle va_handle
;
306 assert(rdesc
->initial_domain
& RADEON_DOMAIN_VRAM_GTT
);
307 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
312 request
.alloc_size
= size
;
313 request
.phys_alignment
= desc
->alignment
;
315 if (rdesc
->initial_domain
& RADEON_DOMAIN_VRAM
) {
316 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_VRAM
;
317 if (rdesc
->flags
& RADEON_FLAG_CPU_ACCESS
)
318 request
.flags
|= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
;
320 if (rdesc
->initial_domain
& RADEON_DOMAIN_GTT
) {
321 request
.preferred_heap
|= AMDGPU_GEM_DOMAIN_GTT
;
322 if (rdesc
->flags
& RADEON_FLAG_GTT_WC
)
323 request
.flags
|= AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
326 r
= amdgpu_bo_alloc(rws
->dev
, &request
, &buf_handle
);
328 fprintf(stderr
, "amdgpu: Failed to allocate a buffer:\n");
329 fprintf(stderr
, "amdgpu: size : %d bytes\n", size
);
330 fprintf(stderr
, "amdgpu: alignment : %d bytes\n", desc
->alignment
);
331 fprintf(stderr
, "amdgpu: domains : %d\n", rdesc
->initial_domain
);
335 r
= amdgpu_va_range_alloc(rws
->dev
, amdgpu_gpu_va_range_general
,
336 size
, desc
->alignment
, 0, &va
, &va_handle
, 0);
340 r
= amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
);
344 pipe_reference_init(&bo
->base
.reference
, 1);
345 bo
->base
.alignment
= desc
->alignment
;
346 bo
->base
.usage
= desc
->usage
;
347 bo
->base
.size
= size
;
348 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
352 bo
->va_handle
= va_handle
;
353 bo
->initial_domain
= rdesc
->initial_domain
;
354 bo
->unique_id
= __sync_fetch_and_add(&rws
->next_bo_unique_id
, 1);
356 if (rdesc
->initial_domain
& RADEON_DOMAIN_VRAM
)
357 rws
->allocated_vram
+= align(size
, rws
->gart_page_size
);
358 else if (rdesc
->initial_domain
& RADEON_DOMAIN_GTT
)
359 rws
->allocated_gtt
+= align(size
, rws
->gart_page_size
);
364 amdgpu_va_range_free(va_handle
);
367 amdgpu_bo_free(buf_handle
);
374 static void amdgpu_bomgr_flush(struct pb_manager
*mgr
)
379 /* This is for the cache bufmgr. */
380 static boolean
amdgpu_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
381 struct pb_buffer
*_buf
)
383 struct amdgpu_winsys_bo
*bo
= amdgpu_winsys_bo(_buf
);
385 if (amdgpu_bo_is_referenced_by_any_cs(bo
)) {
389 if (!amdgpu_bo_wait((struct pb_buffer
*)bo
, 0, RADEON_USAGE_READWRITE
)) {
396 static void amdgpu_bomgr_destroy(struct pb_manager
*mgr
)
401 struct pb_manager
*amdgpu_bomgr_create(struct amdgpu_winsys
*rws
)
403 struct amdgpu_bomgr
*mgr
;
405 mgr
= CALLOC_STRUCT(amdgpu_bomgr
);
409 mgr
->base
.destroy
= amdgpu_bomgr_destroy
;
410 mgr
->base
.create_buffer
= amdgpu_bomgr_create_bo
;
411 mgr
->base
.flush
= amdgpu_bomgr_flush
;
412 mgr
->base
.is_buffer_busy
= amdgpu_bomgr_is_buffer_busy
;
418 static unsigned eg_tile_split(unsigned tile_split
)
420 switch (tile_split
) {
421 case 0: tile_split
= 64; break;
422 case 1: tile_split
= 128; break;
423 case 2: tile_split
= 256; break;
424 case 3: tile_split
= 512; break;
426 case 4: tile_split
= 1024; break;
427 case 5: tile_split
= 2048; break;
428 case 6: tile_split
= 4096; break;
433 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
435 switch (eg_tile_split
) {
447 static void amdgpu_bo_get_tiling(struct pb_buffer
*_buf
,
448 enum radeon_bo_layout
*microtiled
,
449 enum radeon_bo_layout
*macrotiled
,
450 unsigned *bankw
, unsigned *bankh
,
451 unsigned *tile_split
,
452 unsigned *stencil_tile_split
,
456 struct amdgpu_winsys_bo
*bo
= get_amdgpu_winsys_bo(_buf
);
457 struct amdgpu_bo_info info
= {0};
458 uint32_t tiling_flags
;
461 r
= amdgpu_bo_query_info(bo
->bo
, &info
);
465 tiling_flags
= info
.metadata
.tiling_info
;
467 *microtiled
= RADEON_LAYOUT_LINEAR
;
468 *macrotiled
= RADEON_LAYOUT_LINEAR
;
470 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 4) /* 2D_TILED_THIN1 */
471 *macrotiled
= RADEON_LAYOUT_TILED
;
472 else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == 2) /* 1D_TILED_THIN1 */
473 *microtiled
= RADEON_LAYOUT_TILED
;
475 if (bankw
&& tile_split
&& mtilea
&& tile_split
) {
476 *bankw
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
477 *bankh
= 1 << AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
478 *tile_split
= eg_tile_split(AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
));
479 *mtilea
= 1 << AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
482 *scanout
= AMDGPU_TILING_GET(tiling_flags
, MICRO_TILE_MODE
) == 0; /* DISPLAY */
485 static void amdgpu_bo_set_tiling(struct pb_buffer
*_buf
,
486 struct radeon_winsys_cs
*rcs
,
487 enum radeon_bo_layout microtiled
,
488 enum radeon_bo_layout macrotiled
,
489 unsigned pipe_config
,
490 unsigned bankw
, unsigned bankh
,
492 unsigned stencil_tile_split
,
493 unsigned mtilea
, unsigned num_banks
,
497 struct amdgpu_winsys_bo
*bo
= get_amdgpu_winsys_bo(_buf
);
498 struct amdgpu_bo_metadata metadata
= {0};
499 uint32_t tiling_flags
= 0;
501 if (macrotiled
== RADEON_LAYOUT_TILED
)
502 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 4); /* 2D_TILED_THIN1 */
503 else if (microtiled
== RADEON_LAYOUT_TILED
)
504 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 2); /* 1D_TILED_THIN1 */
506 tiling_flags
|= AMDGPU_TILING_SET(ARRAY_MODE
, 1); /* LINEAR_ALIGNED */
508 tiling_flags
|= AMDGPU_TILING_SET(PIPE_CONFIG
, pipe_config
);
509 tiling_flags
|= AMDGPU_TILING_SET(BANK_WIDTH
, util_logbase2(bankw
));
510 tiling_flags
|= AMDGPU_TILING_SET(BANK_HEIGHT
, util_logbase2(bankh
));
512 tiling_flags
|= AMDGPU_TILING_SET(TILE_SPLIT
, eg_tile_split_rev(tile_split
));
513 tiling_flags
|= AMDGPU_TILING_SET(MACRO_TILE_ASPECT
, util_logbase2(mtilea
));
514 tiling_flags
|= AMDGPU_TILING_SET(NUM_BANKS
, util_logbase2(num_banks
)-1);
517 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 0); /* DISPLAY_MICRO_TILING */
519 tiling_flags
|= AMDGPU_TILING_SET(MICRO_TILE_MODE
, 1); /* THIN_MICRO_TILING */
521 metadata
.tiling_info
= tiling_flags
;
523 amdgpu_bo_set_metadata(bo
->bo
, &metadata
);
526 static struct radeon_winsys_cs_handle
*amdgpu_get_cs_handle(struct pb_buffer
*_buf
)
528 /* return a direct pointer to amdgpu_winsys_bo. */
529 return (struct radeon_winsys_cs_handle
*)get_amdgpu_winsys_bo(_buf
);
532 static struct pb_buffer
*
533 amdgpu_bo_create(struct radeon_winsys
*rws
,
536 boolean use_reusable_pool
,
537 enum radeon_bo_domain domain
,
538 enum radeon_bo_flag flags
)
540 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
541 struct amdgpu_bo_desc desc
;
542 struct pb_manager
*provider
;
543 struct pb_buffer
*buffer
;
545 /* Don't use VRAM if the GPU doesn't have much. This is only the initial
546 * domain. The kernel is free to move the buffer if it wants to.
548 * 64MB means no VRAM by todays standards.
550 if (domain
& RADEON_DOMAIN_VRAM
&& ws
->info
.vram_size
<= 64*1024*1024) {
551 domain
= RADEON_DOMAIN_GTT
;
552 flags
= RADEON_FLAG_GTT_WC
;
555 memset(&desc
, 0, sizeof(desc
));
556 desc
.base
.alignment
= alignment
;
558 /* Align size to page size. This is the minimum alignment for normal
559 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
560 * like constant/uniform buffers, can benefit from better and more reuse.
562 size
= align(size
, ws
->gart_page_size
);
564 /* Only set one usage bit each for domains and flags, or the cache manager
565 * might consider different sets of domains / flags compatible
567 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
568 desc
.base
.usage
= 1 << 2;
570 desc
.base
.usage
= domain
>> 1;
571 assert(flags
< sizeof(desc
.base
.usage
) * 8 - 3);
572 desc
.base
.usage
|= 1 << (flags
+ 3);
574 desc
.initial_domain
= domain
;
577 /* Assign a buffer manager. */
578 if (use_reusable_pool
)
583 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
587 return (struct pb_buffer
*)buffer
;
590 static struct pb_buffer
*amdgpu_bo_from_handle(struct radeon_winsys
*rws
,
591 struct winsys_handle
*whandle
,
594 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
595 struct amdgpu_winsys_bo
*bo
;
596 enum amdgpu_bo_handle_type type
;
597 struct amdgpu_bo_import_result result
= {0};
599 amdgpu_va_handle va_handle
;
600 struct amdgpu_bo_info info
= {0};
601 enum radeon_bo_domain initial
= 0;
604 /* Initialize the structure. */
605 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
610 switch (whandle
->type
) {
611 case DRM_API_HANDLE_TYPE_SHARED
:
612 type
= amdgpu_bo_handle_type_gem_flink_name
;
614 case DRM_API_HANDLE_TYPE_FD
:
615 type
= amdgpu_bo_handle_type_dma_buf_fd
;
621 r
= amdgpu_bo_import(ws
->dev
, type
, whandle
->handle
, &result
);
625 /* Get initial domains. */
626 r
= amdgpu_bo_query_info(result
.buf_handle
, &info
);
630 r
= amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
631 result
.alloc_size
, 1 << 20, 0, &va
, &va_handle
, 0);
635 r
= amdgpu_bo_va_op(result
.buf_handle
, 0, result
.alloc_size
, va
, 0, AMDGPU_VA_OP_MAP
);
639 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_VRAM
)
640 initial
|= RADEON_DOMAIN_VRAM
;
641 if (info
.preferred_heap
& AMDGPU_GEM_DOMAIN_GTT
)
642 initial
|= RADEON_DOMAIN_GTT
;
645 pipe_reference_init(&bo
->base
.reference
, 1);
646 bo
->base
.alignment
= info
.phys_alignment
;
647 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
648 bo
->bo
= result
.buf_handle
;
649 bo
->base
.size
= result
.alloc_size
;
650 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
653 bo
->va_handle
= va_handle
;
654 bo
->initial_domain
= initial
;
655 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
656 bo
->is_shared
= true;
659 *stride
= whandle
->stride
;
661 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
662 ws
->allocated_vram
+= align(bo
->base
.size
, ws
->gart_page_size
);
663 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
664 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->gart_page_size
);
669 amdgpu_va_range_free(va_handle
);
672 amdgpu_bo_free(result
.buf_handle
);
679 static boolean
amdgpu_bo_get_handle(struct pb_buffer
*buffer
,
681 struct winsys_handle
*whandle
)
683 struct amdgpu_winsys_bo
*bo
= get_amdgpu_winsys_bo(buffer
);
684 enum amdgpu_bo_handle_type type
;
687 switch (whandle
->type
) {
688 case DRM_API_HANDLE_TYPE_SHARED
:
689 type
= amdgpu_bo_handle_type_gem_flink_name
;
691 case DRM_API_HANDLE_TYPE_FD
:
692 type
= amdgpu_bo_handle_type_dma_buf_fd
;
694 case DRM_API_HANDLE_TYPE_KMS
:
695 type
= amdgpu_bo_handle_type_kms
;
701 r
= amdgpu_bo_export(bo
->bo
, type
, &whandle
->handle
);
705 whandle
->stride
= stride
;
706 bo
->is_shared
= true;
710 static struct pb_buffer
*amdgpu_bo_from_ptr(struct radeon_winsys
*rws
,
711 void *pointer
, unsigned size
)
713 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
714 amdgpu_bo_handle buf_handle
;
715 struct amdgpu_winsys_bo
*bo
;
717 amdgpu_va_handle va_handle
;
719 bo
= CALLOC_STRUCT(amdgpu_winsys_bo
);
723 if (amdgpu_create_bo_from_user_mem(ws
->dev
, pointer
, size
, &buf_handle
))
726 if (amdgpu_va_range_alloc(ws
->dev
, amdgpu_gpu_va_range_general
,
727 size
, 1 << 12, 0, &va
, &va_handle
, 0))
730 if (amdgpu_bo_va_op(buf_handle
, 0, size
, va
, 0, AMDGPU_VA_OP_MAP
))
734 pipe_reference_init(&bo
->base
.reference
, 1);
736 bo
->base
.alignment
= 0;
737 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
738 bo
->base
.size
= size
;
739 bo
->base
.vtbl
= &amdgpu_winsys_bo_vtbl
;
741 bo
->user_ptr
= pointer
;
743 bo
->va_handle
= va_handle
;
744 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
745 bo
->unique_id
= __sync_fetch_and_add(&ws
->next_bo_unique_id
, 1);
747 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->gart_page_size
);
749 return (struct pb_buffer
*)bo
;
752 amdgpu_va_range_free(va_handle
);
755 amdgpu_bo_free(buf_handle
);
762 static uint64_t amdgpu_bo_get_va(struct radeon_winsys_cs_handle
*buf
)
764 return ((struct amdgpu_winsys_bo
*)buf
)->va
;
767 void amdgpu_bomgr_init_functions(struct amdgpu_winsys
*ws
)
769 ws
->base
.buffer_get_cs_handle
= amdgpu_get_cs_handle
;
770 ws
->base
.buffer_set_tiling
= amdgpu_bo_set_tiling
;
771 ws
->base
.buffer_get_tiling
= amdgpu_bo_get_tiling
;
772 ws
->base
.buffer_map
= amdgpu_bo_map
;
773 ws
->base
.buffer_unmap
= amdgpu_bo_unmap
;
774 ws
->base
.buffer_wait
= amdgpu_bo_wait
;
775 ws
->base
.buffer_create
= amdgpu_bo_create
;
776 ws
->base
.buffer_from_handle
= amdgpu_bo_from_handle
;
777 ws
->base
.buffer_from_ptr
= amdgpu_bo_from_ptr
;
778 ws
->base
.buffer_get_handle
= amdgpu_bo_get_handle
;
779 ws
->base
.buffer_get_virtual_address
= amdgpu_bo_get_va
;
780 ws
->base
.buffer_get_initial_domain
= amdgpu_bo_get_initial_domain
;