2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 #ifndef AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
37 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
40 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
44 static struct pipe_fence_handle
*
45 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
46 unsigned ip_instance
, unsigned ring
)
48 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
50 fence
->reference
.count
= 1;
53 fence
->fence
.context
= ctx
->ctx
;
54 fence
->fence
.ip_type
= ip_type
;
55 fence
->fence
.ip_instance
= ip_instance
;
56 fence
->fence
.ring
= ring
;
57 util_queue_fence_init(&fence
->submitted
);
58 util_queue_fence_reset(&fence
->submitted
);
59 p_atomic_inc(&ctx
->refcount
);
60 return (struct pipe_fence_handle
*)fence
;
63 static struct pipe_fence_handle
*
64 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
66 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
67 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
73 pipe_reference_init(&fence
->reference
, 1);
76 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
82 util_queue_fence_init(&fence
->submitted
);
84 assert(amdgpu_fence_is_syncobj(fence
));
85 return (struct pipe_fence_handle
*)fence
;
88 static struct pipe_fence_handle
*
89 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
91 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
92 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
97 pipe_reference_init(&fence
->reference
, 1);
99 /* fence->ctx == NULL means that the fence is syncobj-based. */
101 /* Convert sync_file into syncobj. */
102 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
108 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
110 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
115 util_queue_fence_init(&fence
->submitted
);
117 return (struct pipe_fence_handle
*)fence
;
120 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
121 struct pipe_fence_handle
*pfence
)
123 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
124 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
126 if (amdgpu_fence_is_syncobj(fence
)) {
129 /* Convert syncobj into sync_file. */
130 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
134 util_queue_fence_wait(&fence
->submitted
);
136 /* Convert the amdgpu fence into a fence FD. */
138 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
139 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
146 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
148 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
152 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
158 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
163 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
167 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
169 uint64_t *user_fence_cpu_address
)
171 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
173 rfence
->fence
.fence
= seq_no
;
174 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
175 util_queue_fence_signal(&rfence
->submitted
);
178 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
180 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
182 rfence
->signalled
= true;
183 util_queue_fence_signal(&rfence
->submitted
);
186 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
189 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
192 uint64_t *user_fence_cpu
;
195 if (rfence
->signalled
)
198 /* Handle syncobjs. */
199 if (amdgpu_fence_is_syncobj(rfence
)) {
200 /* Absolute timeouts are only be used by BO fences, which aren't
201 * backed by syncobjs.
205 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
209 rfence
->signalled
= true;
214 abs_timeout
= timeout
;
216 abs_timeout
= os_time_get_absolute_timeout(timeout
);
218 /* The fence might not have a number assigned if its IB is being
219 * submitted in the other thread right now. Wait until the submission
221 if (!util_queue_fence_wait_timeout(&rfence
->submitted
, abs_timeout
))
224 user_fence_cpu
= rfence
->user_fence_cpu_address
;
225 if (user_fence_cpu
) {
226 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
227 rfence
->signalled
= true;
231 /* No timeout, just query: no need for the ioctl. */
232 if (!absolute
&& !timeout
)
236 /* Now use the libdrm query. */
237 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
239 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
242 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
247 /* This variable can only transition from false to true, so it doesn't
248 * matter if threads race for it. */
249 rfence
->signalled
= true;
255 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
256 struct pipe_fence_handle
*fence
,
259 return amdgpu_fence_wait(fence
, timeout
, false);
262 static struct pipe_fence_handle
*
263 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
265 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
266 struct pipe_fence_handle
*fence
= NULL
;
268 if (debug_get_option_noop())
271 if (cs
->next_fence
) {
272 amdgpu_fence_reference(&fence
, cs
->next_fence
);
276 fence
= amdgpu_fence_create(cs
->ctx
,
277 cs
->csc
->ib
[IB_MAIN
].ip_type
,
278 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
279 cs
->csc
->ib
[IB_MAIN
].ring
);
283 amdgpu_fence_reference(&cs
->next_fence
, fence
);
289 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
291 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
293 struct amdgpu_bo_alloc_request alloc_buffer
= {};
294 amdgpu_bo_handle buf_handle
;
299 ctx
->ws
= amdgpu_winsys(ws
);
301 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
303 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
305 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
309 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
310 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
311 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
313 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
315 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
316 goto error_user_fence_alloc
;
319 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
321 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
322 goto error_user_fence_map
;
325 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
326 ctx
->user_fence_bo
= buf_handle
;
328 return (struct radeon_winsys_ctx
*)ctx
;
330 error_user_fence_map
:
331 amdgpu_bo_free(buf_handle
);
332 error_user_fence_alloc
:
333 amdgpu_cs_ctx_free(ctx
->ctx
);
339 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
341 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
344 static enum pipe_reset_status
345 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
347 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
348 uint32_t result
, hangs
;
351 /* Return a failure due to a rejected command submission. */
352 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
353 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
354 PIPE_INNOCENT_CONTEXT_RESET
;
357 /* Return a failure due to a GPU hang. */
358 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
360 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
361 return PIPE_NO_RESET
;
365 case AMDGPU_CTX_GUILTY_RESET
:
366 return PIPE_GUILTY_CONTEXT_RESET
;
367 case AMDGPU_CTX_INNOCENT_RESET
:
368 return PIPE_INNOCENT_CONTEXT_RESET
;
369 case AMDGPU_CTX_UNKNOWN_RESET
:
370 return PIPE_UNKNOWN_CONTEXT_RESET
;
371 case AMDGPU_CTX_NO_RESET
:
373 return PIPE_NO_RESET
;
377 /* COMMAND SUBMISSION */
379 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
381 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
382 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
383 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
384 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
385 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
;
388 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
390 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
391 cs
->ring_type
== RING_GFX
;
394 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
396 if (ring_type
== RING_GFX
)
397 return 4; /* for chaining */
402 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
404 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
405 int i
= cs
->buffer_indices_hashlist
[hash
];
406 struct amdgpu_cs_buffer
*buffers
;
410 buffers
= cs
->real_buffers
;
411 num_buffers
= cs
->num_real_buffers
;
412 } else if (!bo
->sparse
) {
413 buffers
= cs
->slab_buffers
;
414 num_buffers
= cs
->num_slab_buffers
;
416 buffers
= cs
->sparse_buffers
;
417 num_buffers
= cs
->num_sparse_buffers
;
420 /* not found or found */
421 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
424 /* Hash collision, look for the BO in the list of buffers linearly. */
425 for (i
= num_buffers
- 1; i
>= 0; i
--) {
426 if (buffers
[i
].bo
== bo
) {
427 /* Put this buffer in the hash list.
428 * This will prevent additional hash collisions if there are
429 * several consecutive lookup_buffer calls for the same buffer.
431 * Example: Assuming buffers A,B,C collide in the hash list,
432 * the following sequence of buffers:
433 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
434 * will collide here: ^ and here: ^,
435 * meaning that we should get very few collisions in the end. */
436 cs
->buffer_indices_hashlist
[hash
] = i
;
444 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
446 struct amdgpu_cs_buffer
*buffer
;
449 /* New buffer, check if the backing array is large enough. */
450 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
452 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
453 struct amdgpu_cs_buffer
*new_buffers
;
455 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
458 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
463 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
465 FREE(cs
->real_buffers
);
467 cs
->max_real_buffers
= new_max
;
468 cs
->real_buffers
= new_buffers
;
471 idx
= cs
->num_real_buffers
;
472 buffer
= &cs
->real_buffers
[idx
];
474 memset(buffer
, 0, sizeof(*buffer
));
475 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
476 p_atomic_inc(&bo
->num_cs_references
);
477 cs
->num_real_buffers
++;
483 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
485 struct amdgpu_cs_context
*cs
= acs
->csc
;
487 int idx
= amdgpu_lookup_buffer(cs
, bo
);
492 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
494 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
495 cs
->buffer_indices_hashlist
[hash
] = idx
;
497 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
498 acs
->main
.base
.used_vram
+= bo
->base
.size
;
499 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
500 acs
->main
.base
.used_gart
+= bo
->base
.size
;
505 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
506 struct amdgpu_winsys_bo
*bo
)
508 struct amdgpu_cs_context
*cs
= acs
->csc
;
509 struct amdgpu_cs_buffer
*buffer
;
511 int idx
= amdgpu_lookup_buffer(cs
, bo
);
517 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
521 /* New buffer, check if the backing array is large enough. */
522 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
524 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
525 struct amdgpu_cs_buffer
*new_buffers
;
527 new_buffers
= REALLOC(cs
->slab_buffers
,
528 cs
->max_slab_buffers
* sizeof(*new_buffers
),
529 new_max
* sizeof(*new_buffers
));
531 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
535 cs
->max_slab_buffers
= new_max
;
536 cs
->slab_buffers
= new_buffers
;
539 idx
= cs
->num_slab_buffers
;
540 buffer
= &cs
->slab_buffers
[idx
];
542 memset(buffer
, 0, sizeof(*buffer
));
543 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
544 buffer
->u
.slab
.real_idx
= real_idx
;
545 p_atomic_inc(&bo
->num_cs_references
);
546 cs
->num_slab_buffers
++;
548 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
549 cs
->buffer_indices_hashlist
[hash
] = idx
;
554 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
555 struct amdgpu_winsys_bo
*bo
)
557 struct amdgpu_cs_context
*cs
= acs
->csc
;
558 struct amdgpu_cs_buffer
*buffer
;
560 int idx
= amdgpu_lookup_buffer(cs
, bo
);
565 /* New buffer, check if the backing array is large enough. */
566 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
568 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
569 struct amdgpu_cs_buffer
*new_buffers
;
571 new_buffers
= REALLOC(cs
->sparse_buffers
,
572 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
573 new_max
* sizeof(*new_buffers
));
575 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
579 cs
->max_sparse_buffers
= new_max
;
580 cs
->sparse_buffers
= new_buffers
;
583 idx
= cs
->num_sparse_buffers
;
584 buffer
= &cs
->sparse_buffers
[idx
];
586 memset(buffer
, 0, sizeof(*buffer
));
587 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
588 p_atomic_inc(&bo
->num_cs_references
);
589 cs
->num_sparse_buffers
++;
591 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
592 cs
->buffer_indices_hashlist
[hash
] = idx
;
594 /* We delay adding the backing buffers until we really have to. However,
595 * we cannot delay accounting for memory use.
597 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
599 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
600 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
601 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
602 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
603 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
606 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
611 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
612 struct pb_buffer
*buf
,
613 enum radeon_bo_usage usage
,
614 enum radeon_bo_domain domains
,
615 enum radeon_bo_priority priority
)
617 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
618 * the buffer placement during command submission.
620 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
621 struct amdgpu_cs_context
*cs
= acs
->csc
;
622 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
623 struct amdgpu_cs_buffer
*buffer
;
626 /* Fast exit for no-op calls.
627 * This is very effective with suballocators and linear uploaders that
628 * are outside of the winsys.
630 if (bo
== cs
->last_added_bo
&&
631 (usage
& cs
->last_added_bo_usage
) == usage
&&
632 (1u << priority
) & cs
->last_added_bo_priority_usage
)
633 return cs
->last_added_bo_index
;
637 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
641 buffer
= &cs
->slab_buffers
[index
];
642 buffer
->usage
|= usage
;
644 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
645 index
= buffer
->u
.slab
.real_idx
;
647 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
652 buffer
= &cs
->real_buffers
[index
];
654 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
658 buffer
= &cs
->sparse_buffers
[index
];
661 buffer
->u
.real
.priority_usage
|= 1u << priority
;
662 buffer
->usage
|= usage
;
664 cs
->last_added_bo
= bo
;
665 cs
->last_added_bo_index
= index
;
666 cs
->last_added_bo_usage
= buffer
->usage
;
667 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
671 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
672 enum ring_type ring_type
)
674 struct pb_buffer
*pb
;
676 unsigned buffer_size
;
678 /* Always create a buffer that is at least as large as the maximum seen IB
679 * size, aligned to a power of two (and multiplied by 4 to reduce internal
680 * fragmentation if chaining is not available). Limit to 512k dwords, which
681 * is the largest power of two that fits into the size field of the
682 * INDIRECT_BUFFER packet.
684 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
685 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
687 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
689 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
691 switch (ib
->ib_type
) {
693 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
696 unreachable("unhandled IB type");
699 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
700 ws
->info
.gart_page_size
,
702 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
703 (ring_type
== RING_GFX
||
704 ring_type
== RING_COMPUTE
||
705 ring_type
== RING_DMA
?
706 RADEON_FLAG_READ_ONLY
| RADEON_FLAG_GTT_WC
: 0));
710 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
712 pb_reference(&pb
, NULL
);
716 pb_reference(&ib
->big_ib_buffer
, pb
);
717 pb_reference(&pb
, NULL
);
719 ib
->ib_mapped
= mapped
;
720 ib
->used_ib_space
= 0;
725 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
729 /* Smaller submits means the GPU gets busy sooner and there is less
730 * waiting for buffers and fences. Proof:
731 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
735 unreachable("bad ib_type");
739 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
740 enum ib_type ib_type
)
742 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
743 /* Small IBs are better than big IBs, because the GPU goes idle quicker
744 * and there is less waiting for buffers and fences. Proof:
745 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
747 struct amdgpu_ib
*ib
= NULL
;
748 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
749 unsigned ib_size
= 0;
754 ib_size
= 4 * 1024 * 4;
757 unreachable("unhandled IB type");
760 if (!amdgpu_cs_has_chaining(cs
)) {
761 ib_size
= MAX2(ib_size
,
762 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
763 amdgpu_ib_max_submit_dwords(ib_type
)));
766 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
768 ib
->base
.prev_dw
= 0;
769 ib
->base
.num_prev
= 0;
770 ib
->base
.current
.cdw
= 0;
771 ib
->base
.current
.buf
= NULL
;
773 /* Allocate a new buffer for IBs if the current buffer is all used. */
774 if (!ib
->big_ib_buffer
||
775 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
776 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
780 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
782 /* ib_bytes is in dwords and the conversion to bytes will be done before
784 ib
->ptr_ib_size
= &info
->ib_bytes
;
785 ib
->ptr_ib_size_inside_ib
= false;
787 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
788 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
790 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
792 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
793 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
797 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
799 if (ib
->ptr_ib_size_inside_ib
) {
800 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
801 S_3F2_CHAIN(1) | S_3F2_VALID(1);
803 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
807 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
809 amdgpu_set_ib_size(ib
);
810 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
811 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_start_alignment
);
812 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
815 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
816 struct amdgpu_cs_context
*cs
,
817 enum ring_type ring_type
)
821 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
825 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
829 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
833 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
837 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
841 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
846 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
847 AMDGPU_HW_IP_COMPUTE
;
849 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
850 * invalidation is the beginning of IBs (the previous commit does that),
851 * because completion of an IB doesn't care about the state of GPU caches,
852 * but the beginning of an IB does. Draw calls from multiple IBs can be
853 * executed in parallel, so draw calls from the current IB can finish after
854 * the next IB starts drawing, and so the cache flush at the end of IB
857 if (ws
->info
.drm_minor
>= 26)
858 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
865 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
866 cs
->last_added_bo
= NULL
;
870 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
874 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
875 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
876 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
878 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
879 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
880 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
882 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
883 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
884 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
886 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
887 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
888 for (i
= 0; i
< cs
->num_syncobj_to_signal
; i
++)
889 amdgpu_fence_reference(&cs
->syncobj_to_signal
[i
], NULL
);
891 cs
->num_real_buffers
= 0;
892 cs
->num_slab_buffers
= 0;
893 cs
->num_sparse_buffers
= 0;
894 cs
->num_fence_dependencies
= 0;
895 cs
->num_syncobj_to_signal
= 0;
896 amdgpu_fence_reference(&cs
->fence
, NULL
);
898 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
899 cs
->last_added_bo
= NULL
;
902 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
904 amdgpu_cs_context_cleanup(cs
);
905 FREE(cs
->real_buffers
);
906 FREE(cs
->slab_buffers
);
907 FREE(cs
->sparse_buffers
);
908 FREE(cs
->fence_dependencies
);
909 FREE(cs
->syncobj_to_signal
);
913 static struct radeon_cmdbuf
*
914 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
915 enum ring_type ring_type
,
916 void (*flush
)(void *ctx
, unsigned flags
,
917 struct pipe_fence_handle
**fence
),
920 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
921 struct amdgpu_cs
*cs
;
923 cs
= CALLOC_STRUCT(amdgpu_cs
);
928 util_queue_fence_init(&cs
->flush_completed
);
931 cs
->flush_cs
= flush
;
932 cs
->flush_data
= flush_ctx
;
933 cs
->ring_type
= ring_type
;
935 struct amdgpu_cs_fence_info fence_info
;
936 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
937 fence_info
.offset
= cs
->ring_type
;
938 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
940 cs
->main
.ib_type
= IB_MAIN
;
942 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
947 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
948 amdgpu_destroy_cs_context(&cs
->csc1
);
953 /* Set the first submission context as current. */
957 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
958 amdgpu_destroy_cs_context(&cs
->csc2
);
959 amdgpu_destroy_cs_context(&cs
->csc1
);
964 p_atomic_inc(&ctx
->ws
->num_cs
);
965 return &cs
->main
.base
;
968 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
973 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
)
975 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
976 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
977 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
979 uint32_t *new_ptr_ib_size
;
981 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
983 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
986 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
988 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
991 if (!amdgpu_cs_has_chaining(cs
))
994 /* Allocate a new chunk */
995 if (rcs
->num_prev
>= rcs
->max_prev
) {
996 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
997 struct radeon_cmdbuf_chunk
*new_prev
;
999 new_prev
= REALLOC(rcs
->prev
,
1000 sizeof(*new_prev
) * rcs
->max_prev
,
1001 sizeof(*new_prev
) * new_max_prev
);
1005 rcs
->prev
= new_prev
;
1006 rcs
->max_prev
= new_max_prev
;
1009 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1012 assert(ib
->used_ib_space
== 0);
1013 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1015 /* This space was originally reserved. */
1016 rcs
->current
.max_dw
+= 4;
1017 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
1019 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1020 while ((rcs
->current
.cdw
& 7) != 4)
1021 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1023 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
1024 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
1025 radeon_emit(rcs
, va
);
1026 radeon_emit(rcs
, va
>> 32);
1027 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1029 assert((rcs
->current
.cdw
& 7) == 0);
1030 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1032 amdgpu_set_ib_size(ib
);
1033 ib
->ptr_ib_size
= new_ptr_ib_size
;
1034 ib
->ptr_ib_size_inside_ib
= true;
1036 /* Hook up the new chunk */
1037 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1038 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1039 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1042 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1043 ib
->base
.current
.cdw
= 0;
1045 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1046 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
1048 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1049 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1054 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1055 struct radeon_bo_list_item
*list
)
1057 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1061 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1062 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1063 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1064 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1067 return cs
->num_real_buffers
;
1070 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
1072 unsigned idx
= cs
->num_fence_dependencies
++;
1074 if (idx
>= cs
->max_fence_dependencies
) {
1076 const unsigned increment
= 8;
1078 cs
->max_fence_dependencies
= idx
+ increment
;
1079 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1080 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1081 /* Clear the newly-allocated elements. */
1082 memset(cs
->fence_dependencies
+ idx
, 0,
1083 increment
* sizeof(cs
->fence_dependencies
[0]));
1088 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1089 struct amdgpu_fence
*fence
)
1091 struct amdgpu_cs_context
*cs
= acs
->csc
;
1093 if (!amdgpu_fence_is_syncobj(fence
) &&
1094 fence
->ctx
== acs
->ctx
&&
1095 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1096 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1097 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1100 return amdgpu_fence_wait((void *)fence
, 0, false);
1103 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1104 struct pipe_fence_handle
*pfence
)
1106 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1107 struct amdgpu_cs_context
*cs
= acs
->csc
;
1108 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1110 util_queue_fence_wait(&fence
->submitted
);
1112 if (is_noop_fence_dependency(acs
, fence
))
1115 unsigned idx
= add_fence_dependency_entry(cs
);
1116 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1117 (struct pipe_fence_handle
*)fence
);
1120 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1121 struct amdgpu_cs_buffer
*buffer
)
1123 struct amdgpu_cs_context
*cs
= acs
->csc
;
1124 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1125 unsigned new_num_fences
= 0;
1127 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1128 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1130 if (is_noop_fence_dependency(acs
, bo_fence
))
1133 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1136 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1139 unsigned idx
= add_fence_dependency_entry(cs
);
1140 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1141 (struct pipe_fence_handle
*)bo_fence
);
1144 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1145 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1147 bo
->num_fences
= new_num_fences
;
1150 /* Add the given list of fences to the buffer's fence list.
1152 * Must be called with the winsys bo_fence_lock held.
1154 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1155 unsigned num_fences
,
1156 struct pipe_fence_handle
**fences
)
1158 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1159 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1160 struct pipe_fence_handle
**new_fences
=
1162 bo
->num_fences
* sizeof(*new_fences
),
1163 new_max_fences
* sizeof(*new_fences
));
1164 if (likely(new_fences
)) {
1165 bo
->fences
= new_fences
;
1166 bo
->max_fences
= new_max_fences
;
1170 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1171 if (!bo
->num_fences
)
1174 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1175 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1177 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1183 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1184 bo
->fences
[bo
->num_fences
] = NULL
;
1185 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1190 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1191 struct pipe_fence_handle
*fence
,
1192 unsigned num_buffers
,
1193 struct amdgpu_cs_buffer
*buffers
)
1195 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1196 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1197 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1199 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1200 p_atomic_inc(&bo
->num_active_ioctls
);
1201 amdgpu_add_fences(bo
, 1, &fence
);
1205 /* Since the kernel driver doesn't synchronize execution between different
1206 * rings automatically, we have to add fence dependencies manually.
1208 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1210 struct amdgpu_cs_context
*cs
= acs
->csc
;
1212 cs
->num_fence_dependencies
= 0;
1214 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1215 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1216 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1219 static unsigned add_syncobj_to_signal_entry(struct amdgpu_cs_context
*cs
)
1221 unsigned idx
= cs
->num_syncobj_to_signal
++;
1223 if (idx
>= cs
->max_syncobj_to_signal
) {
1225 const unsigned increment
= 8;
1227 cs
->max_syncobj_to_signal
= idx
+ increment
;
1228 size
= cs
->max_syncobj_to_signal
* sizeof(cs
->syncobj_to_signal
[0]);
1229 cs
->syncobj_to_signal
= realloc(cs
->syncobj_to_signal
, size
);
1230 /* Clear the newly-allocated elements. */
1231 memset(cs
->syncobj_to_signal
+ idx
, 0,
1232 increment
* sizeof(cs
->syncobj_to_signal
[0]));
1237 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1238 struct pipe_fence_handle
*fence
)
1240 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1241 struct amdgpu_cs_context
*cs
= acs
->csc
;
1243 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1245 unsigned idx
= add_syncobj_to_signal_entry(cs
);
1246 amdgpu_fence_reference(&cs
->syncobj_to_signal
[idx
], fence
);
1249 /* Add backing of sparse buffers to the buffer list.
1251 * This is done late, during submission, to keep the buffer list short before
1252 * submit, and to avoid managing fences for the backing buffers.
1254 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1256 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1257 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1258 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1260 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
1262 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1263 /* We can directly add the buffer here, because we know that each
1264 * backing buffer occurs only once.
1266 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1268 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1269 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1273 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1274 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1275 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1278 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1284 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1286 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1287 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1288 struct amdgpu_cs_context
*cs
= acs
->cst
;
1290 amdgpu_bo_list_handle bo_list
= NULL
;
1291 uint64_t seq_no
= 0;
1292 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1294 /* Create the buffer list.
1295 * Use a buffer list containing all allocated buffers if requested.
1297 if (ws
->debug_all_bos
) {
1298 struct amdgpu_winsys_bo
*bo
;
1299 amdgpu_bo_handle
*handles
;
1302 simple_mtx_lock(&ws
->global_bo_list_lock
);
1303 handles
= alloca(sizeof(handles
[0]) * ws
->num_buffers
);
1305 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1306 assert(num
< ws
->num_buffers
);
1307 handles
[num
++] = bo
->bo
;
1310 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1311 handles
, NULL
, &bo_list
);
1312 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1314 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1318 unsigned num_handles
;
1320 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1321 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1326 amdgpu_bo_handle
*handles
= alloca(sizeof(*handles
) * cs
->num_real_buffers
);
1327 uint8_t *flags
= alloca(sizeof(*flags
) * cs
->num_real_buffers
);
1330 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1331 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1333 if (buffer
->bo
->is_local
)
1336 assert(buffer
->u
.real
.priority_usage
!= 0);
1338 handles
[num_handles
] = buffer
->bo
->bo
;
1339 flags
[num_handles
] = (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1344 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1345 handles
, flags
, &bo_list
);
1347 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1353 if (acs
->ring_type
== RING_GFX
)
1354 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1356 if (acs
->ctx
->num_rejected_cs
) {
1359 struct drm_amdgpu_cs_chunk chunks
[5];
1360 unsigned num_chunks
= 0;
1362 /* Convert from dwords to bytes. */
1363 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1366 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1367 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1368 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1372 if (has_user_fence
) {
1373 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1374 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1375 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1380 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1381 unsigned num_syncobj_dependencies
= 0;
1383 if (num_dependencies
) {
1384 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1385 alloca(num_dependencies
* sizeof(*dep_chunk
));
1388 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1389 struct amdgpu_fence
*fence
=
1390 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1392 if (amdgpu_fence_is_syncobj(fence
)) {
1393 num_syncobj_dependencies
++;
1397 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1398 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1401 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1402 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1403 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1407 /* Syncobj dependencies. */
1408 if (num_syncobj_dependencies
) {
1409 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1410 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1413 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1414 struct amdgpu_fence
*fence
=
1415 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1417 if (!amdgpu_fence_is_syncobj(fence
))
1420 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1421 sem_chunk
[num
++].handle
= fence
->syncobj
;
1424 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1425 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1426 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1430 /* Syncobj sygnals. */
1431 if (cs
->num_syncobj_to_signal
) {
1432 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1433 alloca(cs
->num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1435 for (unsigned i
= 0; i
< cs
->num_syncobj_to_signal
; i
++) {
1436 struct amdgpu_fence
*fence
=
1437 (struct amdgpu_fence
*)cs
->syncobj_to_signal
[i
];
1439 assert(amdgpu_fence_is_syncobj(fence
));
1440 sem_chunk
[i
].handle
= fence
->syncobj
;
1443 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1444 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1445 * cs
->num_syncobj_to_signal
;
1446 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1450 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1452 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1453 num_chunks
, chunks
, &seq_no
);
1458 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1459 else if (r
== -ECANCELED
)
1460 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1462 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1463 "see dmesg for more information (%i).\n", r
);
1465 acs
->ctx
->num_rejected_cs
++;
1466 ws
->num_total_rejected_cs
++;
1469 uint64_t *user_fence
= NULL
;
1472 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1473 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1478 amdgpu_bo_list_destroy(bo_list
);
1481 /* If there was an error, signal the fence, because it won't be signalled
1482 * by the hardware. */
1484 amdgpu_fence_signalled(cs
->fence
);
1488 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1489 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1490 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1491 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1492 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1493 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1495 amdgpu_cs_context_cleanup(cs
);
1498 /* Make sure the previous submission is completed. */
1499 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1501 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1503 /* Wait for any pending ioctl of this CS to complete. */
1504 util_queue_fence_wait(&cs
->flush_completed
);
1507 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1509 struct pipe_fence_handle
**fence
)
1511 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1512 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1515 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1517 switch (cs
->ring_type
) {
1519 /* pad DMA ring to 8 DWs */
1520 if (ws
->info
.chip_class
<= SI
) {
1521 while (rcs
->current
.cdw
& 7)
1522 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1524 while (rcs
->current
.cdw
& 7)
1525 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1530 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1531 if (ws
->info
.gfx_ib_pad_with_type2
) {
1532 while (rcs
->current
.cdw
& 7)
1533 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1535 while (rcs
->current
.cdw
& 7)
1536 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1538 if (cs
->ring_type
== RING_GFX
)
1539 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1543 while (rcs
->current
.cdw
& 15)
1544 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1547 while (rcs
->current
.cdw
& 15)
1548 radeon_emit(rcs
, 0x81ff); /* nop packet */
1554 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1555 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1558 /* If the CS is not empty or overflowed.... */
1559 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1560 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1561 !debug_get_option_noop())) {
1562 struct amdgpu_cs_context
*cur
= cs
->csc
;
1565 amdgpu_ib_finalize(ws
, &cs
->main
);
1567 /* Create a fence. */
1568 amdgpu_fence_reference(&cur
->fence
, NULL
);
1569 if (cs
->next_fence
) {
1570 /* just move the reference */
1571 cur
->fence
= cs
->next_fence
;
1572 cs
->next_fence
= NULL
;
1574 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1575 cur
->ib
[IB_MAIN
].ip_type
,
1576 cur
->ib
[IB_MAIN
].ip_instance
,
1577 cur
->ib
[IB_MAIN
].ring
);
1580 amdgpu_fence_reference(fence
, cur
->fence
);
1582 amdgpu_cs_sync_flush(rcs
);
1586 * This fence must be held until the submission is queued to ensure
1587 * that the order of fence dependency updates matches the order of
1590 simple_mtx_lock(&ws
->bo_fence_lock
);
1591 amdgpu_add_fence_dependencies_bo_lists(cs
);
1593 /* Swap command streams. "cst" is going to be submitted. */
1598 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1599 amdgpu_cs_submit_ib
, NULL
);
1600 /* The submission has been queued, unlock the fence now. */
1601 simple_mtx_unlock(&ws
->bo_fence_lock
);
1603 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1604 amdgpu_cs_sync_flush(rcs
);
1605 error_code
= cur
->error_code
;
1608 amdgpu_cs_context_cleanup(cs
->csc
);
1611 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1613 cs
->main
.base
.used_gart
= 0;
1614 cs
->main
.base
.used_vram
= 0;
1616 if (cs
->ring_type
== RING_GFX
)
1618 else if (cs
->ring_type
== RING_DMA
)
1624 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1626 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1628 amdgpu_cs_sync_flush(rcs
);
1629 util_queue_fence_destroy(&cs
->flush_completed
);
1630 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1631 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1632 FREE(cs
->main
.base
.prev
);
1633 amdgpu_destroy_cs_context(&cs
->csc1
);
1634 amdgpu_destroy_cs_context(&cs
->csc2
);
1635 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1639 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1640 struct pb_buffer
*_buf
,
1641 enum radeon_bo_usage usage
)
1643 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1644 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1646 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1649 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1651 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1652 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1653 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1654 ws
->base
.cs_create
= amdgpu_cs_create
;
1655 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1656 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1657 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1658 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1659 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1660 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1661 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1662 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1663 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1664 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1665 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1666 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1667 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1668 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1669 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1670 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1671 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;