2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
30 * Marek Olšák <maraeo@gmail.com>
33 #include "amdgpu_cs.h"
34 #include "os/os_time.h"
36 #include <amdgpu_drm.h>
38 #include "amd/common/sid.h"
40 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
44 static struct pipe_fence_handle
*
45 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
46 unsigned ip_instance
, unsigned ring
)
48 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
50 fence
->reference
.count
= 1;
52 fence
->fence
.context
= ctx
->ctx
;
53 fence
->fence
.ip_type
= ip_type
;
54 fence
->fence
.ip_instance
= ip_instance
;
55 fence
->fence
.ring
= ring
;
56 fence
->submission_in_progress
= true;
57 p_atomic_inc(&ctx
->refcount
);
58 return (struct pipe_fence_handle
*)fence
;
61 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
62 struct amdgpu_cs_request
* request
,
63 uint64_t *user_fence_cpu_address
)
65 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
67 rfence
->fence
.fence
= request
->seq_no
;
68 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
69 rfence
->submission_in_progress
= false;
72 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
74 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
76 rfence
->signalled
= true;
77 rfence
->submission_in_progress
= false;
80 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
83 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
86 uint64_t *user_fence_cpu
;
89 if (rfence
->signalled
)
93 abs_timeout
= timeout
;
95 abs_timeout
= os_time_get_absolute_timeout(timeout
);
97 /* The fence might not have a number assigned if its IB is being
98 * submitted in the other thread right now. Wait until the submission
100 if (!os_wait_until_zero_abs_timeout(&rfence
->submission_in_progress
,
104 user_fence_cpu
= rfence
->user_fence_cpu_address
;
105 if (user_fence_cpu
) {
106 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
107 rfence
->signalled
= true;
111 /* No timeout, just query: no need for the ioctl. */
112 if (!absolute
&& !timeout
)
116 /* Now use the libdrm query. */
117 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
119 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
122 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
127 /* This variable can only transition from false to true, so it doesn't
128 * matter if threads race for it. */
129 rfence
->signalled
= true;
135 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
136 struct pipe_fence_handle
*fence
,
139 return amdgpu_fence_wait(fence
, timeout
, false);
142 static struct pipe_fence_handle
*
143 amdgpu_cs_get_next_fence(struct radeon_winsys_cs
*rcs
)
145 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
146 struct pipe_fence_handle
*fence
= NULL
;
148 if (debug_get_option_noop())
151 if (cs
->next_fence
) {
152 amdgpu_fence_reference(&fence
, cs
->next_fence
);
156 fence
= amdgpu_fence_create(cs
->ctx
,
157 cs
->csc
->request
.ip_type
,
158 cs
->csc
->request
.ip_instance
,
159 cs
->csc
->request
.ring
);
163 amdgpu_fence_reference(&cs
->next_fence
, fence
);
169 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
171 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
173 struct amdgpu_bo_alloc_request alloc_buffer
= {};
174 amdgpu_bo_handle buf_handle
;
179 ctx
->ws
= amdgpu_winsys(ws
);
181 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
183 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
185 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
189 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
190 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
191 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
193 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
195 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
196 goto error_user_fence_alloc
;
199 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
201 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
202 goto error_user_fence_map
;
205 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
206 ctx
->user_fence_bo
= buf_handle
;
208 return (struct radeon_winsys_ctx
*)ctx
;
210 error_user_fence_map
:
211 amdgpu_bo_free(buf_handle
);
212 error_user_fence_alloc
:
213 amdgpu_cs_ctx_free(ctx
->ctx
);
219 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
221 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
224 static enum pipe_reset_status
225 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
227 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
228 uint32_t result
, hangs
;
231 /* Return a failure due to a rejected command submission. */
232 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
233 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
234 PIPE_INNOCENT_CONTEXT_RESET
;
237 /* Return a failure due to a GPU hang. */
238 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
240 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
241 return PIPE_NO_RESET
;
245 case AMDGPU_CTX_GUILTY_RESET
:
246 return PIPE_GUILTY_CONTEXT_RESET
;
247 case AMDGPU_CTX_INNOCENT_RESET
:
248 return PIPE_INNOCENT_CONTEXT_RESET
;
249 case AMDGPU_CTX_UNKNOWN_RESET
:
250 return PIPE_UNKNOWN_CONTEXT_RESET
;
251 case AMDGPU_CTX_NO_RESET
:
253 return PIPE_NO_RESET
;
257 /* COMMAND SUBMISSION */
259 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
261 return cs
->request
.ip_type
!= AMDGPU_HW_IP_UVD
&&
262 cs
->request
.ip_type
!= AMDGPU_HW_IP_VCE
;
265 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
267 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
268 cs
->ring_type
== RING_GFX
;
271 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
273 if (ring_type
== RING_GFX
)
274 return 4; /* for chaining */
279 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
281 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
282 int i
= cs
->buffer_indices_hashlist
[hash
];
283 struct amdgpu_cs_buffer
*buffers
;
287 buffers
= cs
->real_buffers
;
288 num_buffers
= cs
->num_real_buffers
;
289 } else if (!bo
->sparse
) {
290 buffers
= cs
->slab_buffers
;
291 num_buffers
= cs
->num_slab_buffers
;
293 buffers
= cs
->sparse_buffers
;
294 num_buffers
= cs
->num_sparse_buffers
;
297 /* not found or found */
298 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
301 /* Hash collision, look for the BO in the list of buffers linearly. */
302 for (i
= num_buffers
- 1; i
>= 0; i
--) {
303 if (buffers
[i
].bo
== bo
) {
304 /* Put this buffer in the hash list.
305 * This will prevent additional hash collisions if there are
306 * several consecutive lookup_buffer calls for the same buffer.
308 * Example: Assuming buffers A,B,C collide in the hash list,
309 * the following sequence of buffers:
310 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
311 * will collide here: ^ and here: ^,
312 * meaning that we should get very few collisions in the end. */
313 cs
->buffer_indices_hashlist
[hash
] = i
;
321 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
323 struct amdgpu_cs_buffer
*buffer
;
326 /* New buffer, check if the backing array is large enough. */
327 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
329 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
330 struct amdgpu_cs_buffer
*new_buffers
;
332 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
335 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
340 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
342 FREE(cs
->real_buffers
);
344 cs
->max_real_buffers
= new_max
;
345 cs
->real_buffers
= new_buffers
;
348 idx
= cs
->num_real_buffers
;
349 buffer
= &cs
->real_buffers
[idx
];
351 memset(buffer
, 0, sizeof(*buffer
));
352 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
353 p_atomic_inc(&bo
->num_cs_references
);
354 cs
->num_real_buffers
++;
360 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
362 struct amdgpu_cs_context
*cs
= acs
->csc
;
364 int idx
= amdgpu_lookup_buffer(cs
, bo
);
369 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
371 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
372 cs
->buffer_indices_hashlist
[hash
] = idx
;
374 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
375 acs
->main
.base
.used_vram
+= bo
->base
.size
;
376 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
377 acs
->main
.base
.used_gart
+= bo
->base
.size
;
382 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
383 struct amdgpu_winsys_bo
*bo
)
385 struct amdgpu_cs_context
*cs
= acs
->csc
;
386 struct amdgpu_cs_buffer
*buffer
;
388 int idx
= amdgpu_lookup_buffer(cs
, bo
);
394 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
398 /* New buffer, check if the backing array is large enough. */
399 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
401 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
402 struct amdgpu_cs_buffer
*new_buffers
;
404 new_buffers
= REALLOC(cs
->slab_buffers
,
405 cs
->max_slab_buffers
* sizeof(*new_buffers
),
406 new_max
* sizeof(*new_buffers
));
408 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
412 cs
->max_slab_buffers
= new_max
;
413 cs
->slab_buffers
= new_buffers
;
416 idx
= cs
->num_slab_buffers
;
417 buffer
= &cs
->slab_buffers
[idx
];
419 memset(buffer
, 0, sizeof(*buffer
));
420 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
421 buffer
->u
.slab
.real_idx
= real_idx
;
422 p_atomic_inc(&bo
->num_cs_references
);
423 cs
->num_slab_buffers
++;
425 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
426 cs
->buffer_indices_hashlist
[hash
] = idx
;
431 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
432 struct amdgpu_winsys_bo
*bo
)
434 struct amdgpu_cs_context
*cs
= acs
->csc
;
435 struct amdgpu_cs_buffer
*buffer
;
437 int idx
= amdgpu_lookup_buffer(cs
, bo
);
442 /* New buffer, check if the backing array is large enough. */
443 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
445 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
446 struct amdgpu_cs_buffer
*new_buffers
;
448 new_buffers
= REALLOC(cs
->sparse_buffers
,
449 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
450 new_max
* sizeof(*new_buffers
));
452 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
456 cs
->max_sparse_buffers
= new_max
;
457 cs
->sparse_buffers
= new_buffers
;
460 idx
= cs
->num_sparse_buffers
;
461 buffer
= &cs
->sparse_buffers
[idx
];
463 memset(buffer
, 0, sizeof(*buffer
));
464 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
465 p_atomic_inc(&bo
->num_cs_references
);
466 cs
->num_sparse_buffers
++;
468 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
469 cs
->buffer_indices_hashlist
[hash
] = idx
;
471 /* We delay adding the backing buffers until we really have to. However,
472 * we cannot delay accounting for memory use.
474 mtx_lock(&bo
->u
.sparse
.commit_lock
);
476 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
477 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
478 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
479 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
480 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
483 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
488 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs
*rcs
,
489 struct pb_buffer
*buf
,
490 enum radeon_bo_usage usage
,
491 enum radeon_bo_domain domains
,
492 enum radeon_bo_priority priority
)
494 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
495 * the buffer placement during command submission.
497 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
498 struct amdgpu_cs_context
*cs
= acs
->csc
;
499 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
500 struct amdgpu_cs_buffer
*buffer
;
503 /* Fast exit for no-op calls.
504 * This is very effective with suballocators and linear uploaders that
505 * are outside of the winsys.
507 if (bo
== cs
->last_added_bo
&&
508 (usage
& cs
->last_added_bo_usage
) == usage
&&
509 (1ull << priority
) & cs
->last_added_bo_priority_usage
)
510 return cs
->last_added_bo_index
;
514 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
518 buffer
= &cs
->slab_buffers
[index
];
519 buffer
->usage
|= usage
;
521 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
522 index
= buffer
->u
.slab
.real_idx
;
524 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
529 buffer
= &cs
->real_buffers
[index
];
531 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
535 buffer
= &cs
->sparse_buffers
[index
];
538 buffer
->u
.real
.priority_usage
|= 1llu << priority
;
539 buffer
->usage
|= usage
;
541 cs
->last_added_bo
= bo
;
542 cs
->last_added_bo_index
= index
;
543 cs
->last_added_bo_usage
= buffer
->usage
;
544 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
548 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
550 struct pb_buffer
*pb
;
552 unsigned buffer_size
;
554 /* Always create a buffer that is at least as large as the maximum seen IB
555 * size, aligned to a power of two (and multiplied by 4 to reduce internal
556 * fragmentation if chaining is not available). Limit to 512k dwords, which
557 * is the largest power of two that fits into the size field of the
558 * INDIRECT_BUFFER packet.
560 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
561 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
563 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
565 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
567 switch (ib
->ib_type
) {
568 case IB_CONST_PREAMBLE
:
569 buffer_size
= MAX2(buffer_size
, 4 * 1024);
572 buffer_size
= MAX2(buffer_size
, 16 * 1024 * 4);
575 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
578 unreachable("unhandled IB type");
581 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
582 ws
->info
.gart_page_size
,
584 RADEON_FLAG_CPU_ACCESS
);
588 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
590 pb_reference(&pb
, NULL
);
594 pb_reference(&ib
->big_ib_buffer
, pb
);
595 pb_reference(&pb
, NULL
);
597 ib
->ib_mapped
= mapped
;
598 ib
->used_ib_space
= 0;
603 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
607 /* Smaller submits means the GPU gets busy sooner and there is less
608 * waiting for buffers and fences. Proof:
609 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
612 case IB_CONST_PREAMBLE
:
614 /* There isn't really any reason to limit CE IB size beyond the natural
615 * limit implied by the main IB, except perhaps GTT size. Just return
616 * an extremely large value that we never get anywhere close to.
618 return 16 * 1024 * 1024;
620 unreachable("bad ib_type");
624 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
625 enum ib_type ib_type
)
627 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
628 /* Small IBs are better than big IBs, because the GPU goes idle quicker
629 * and there is less waiting for buffers and fences. Proof:
630 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
632 struct amdgpu_ib
*ib
= NULL
;
633 struct amdgpu_cs_ib_info
*info
= &cs
->csc
->ib
[ib_type
];
634 unsigned ib_size
= 0;
637 case IB_CONST_PREAMBLE
:
638 ib
= &cs
->const_preamble_ib
;
643 ib_size
= 8 * 1024 * 4;
647 ib_size
= 4 * 1024 * 4;
650 unreachable("unhandled IB type");
653 if (!amdgpu_cs_has_chaining(cs
)) {
654 ib_size
= MAX2(ib_size
,
655 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
656 amdgpu_ib_max_submit_dwords(ib_type
)));
659 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
661 ib
->base
.prev_dw
= 0;
662 ib
->base
.num_prev
= 0;
663 ib
->base
.current
.cdw
= 0;
664 ib
->base
.current
.buf
= NULL
;
666 /* Allocate a new buffer for IBs if the current buffer is all used. */
667 if (!ib
->big_ib_buffer
||
668 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
669 if (!amdgpu_ib_new_buffer(aws
, ib
))
673 info
->ib_mc_address
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+
676 ib
->ptr_ib_size
= &info
->size
;
678 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
679 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
681 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
683 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
684 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
688 static void amdgpu_ib_finalize(struct amdgpu_ib
*ib
)
690 *ib
->ptr_ib_size
|= ib
->base
.current
.cdw
;
691 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
692 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
695 static bool amdgpu_init_cs_context(struct amdgpu_cs_context
*cs
,
696 enum ring_type ring_type
)
702 cs
->request
.ip_type
= AMDGPU_HW_IP_DMA
;
706 cs
->request
.ip_type
= AMDGPU_HW_IP_UVD
;
710 cs
->request
.ip_type
= AMDGPU_HW_IP_VCE
;
714 cs
->request
.ip_type
= AMDGPU_HW_IP_COMPUTE
;
719 cs
->request
.ip_type
= AMDGPU_HW_IP_GFX
;
723 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
724 cs
->buffer_indices_hashlist
[i
] = -1;
726 cs
->last_added_bo
= NULL
;
728 cs
->request
.number_of_ibs
= 1;
729 cs
->request
.ibs
= &cs
->ib
[IB_MAIN
];
731 cs
->ib
[IB_CONST
].flags
= AMDGPU_IB_FLAG_CE
;
732 cs
->ib
[IB_CONST_PREAMBLE
].flags
= AMDGPU_IB_FLAG_CE
|
733 AMDGPU_IB_FLAG_PREAMBLE
;
738 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
742 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
743 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
744 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
746 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
747 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
748 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
750 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
751 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
752 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
755 cs
->num_real_buffers
= 0;
756 cs
->num_slab_buffers
= 0;
757 cs
->num_sparse_buffers
= 0;
758 amdgpu_fence_reference(&cs
->fence
, NULL
);
760 for (i
= 0; i
< ARRAY_SIZE(cs
->buffer_indices_hashlist
); i
++) {
761 cs
->buffer_indices_hashlist
[i
] = -1;
763 cs
->last_added_bo
= NULL
;
766 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
768 amdgpu_cs_context_cleanup(cs
);
770 FREE(cs
->real_buffers
);
772 FREE(cs
->slab_buffers
);
773 FREE(cs
->sparse_buffers
);
774 FREE(cs
->request
.dependencies
);
778 static struct radeon_winsys_cs
*
779 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
780 enum ring_type ring_type
,
781 void (*flush
)(void *ctx
, unsigned flags
,
782 struct pipe_fence_handle
**fence
),
785 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
786 struct amdgpu_cs
*cs
;
788 cs
= CALLOC_STRUCT(amdgpu_cs
);
793 util_queue_fence_init(&cs
->flush_completed
);
796 cs
->flush_cs
= flush
;
797 cs
->flush_data
= flush_ctx
;
798 cs
->ring_type
= ring_type
;
800 cs
->main
.ib_type
= IB_MAIN
;
801 cs
->const_ib
.ib_type
= IB_CONST
;
802 cs
->const_preamble_ib
.ib_type
= IB_CONST_PREAMBLE
;
804 if (!amdgpu_init_cs_context(&cs
->csc1
, ring_type
)) {
809 if (!amdgpu_init_cs_context(&cs
->csc2
, ring_type
)) {
810 amdgpu_destroy_cs_context(&cs
->csc1
);
815 /* Set the first submission context as current. */
819 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
820 amdgpu_destroy_cs_context(&cs
->csc2
);
821 amdgpu_destroy_cs_context(&cs
->csc1
);
826 p_atomic_inc(&ctx
->ws
->num_cs
);
827 return &cs
->main
.base
;
830 static struct radeon_winsys_cs
*
831 amdgpu_cs_add_const_ib(struct radeon_winsys_cs
*rcs
)
833 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
834 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
836 /* only one const IB can be added */
837 if (cs
->ring_type
!= RING_GFX
|| cs
->const_ib
.ib_mapped
)
840 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
))
843 cs
->csc
->request
.number_of_ibs
= 2;
844 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST
];
846 cs
->cst
->request
.number_of_ibs
= 2;
847 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST
];
849 return &cs
->const_ib
.base
;
852 static struct radeon_winsys_cs
*
853 amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs
*rcs
)
855 struct amdgpu_cs
*cs
= (struct amdgpu_cs
*)rcs
;
856 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
858 /* only one const preamble IB can be added and only when the const IB has
859 * also been mapped */
860 if (cs
->ring_type
!= RING_GFX
|| !cs
->const_ib
.ib_mapped
||
861 cs
->const_preamble_ib
.ib_mapped
)
864 if (!amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
))
867 cs
->csc
->request
.number_of_ibs
= 3;
868 cs
->csc
->request
.ibs
= &cs
->csc
->ib
[IB_CONST_PREAMBLE
];
870 cs
->cst
->request
.number_of_ibs
= 3;
871 cs
->cst
->request
.ibs
= &cs
->cst
->ib
[IB_CONST_PREAMBLE
];
873 return &cs
->const_preamble_ib
.base
;
876 static bool amdgpu_cs_validate(struct radeon_winsys_cs
*rcs
)
881 static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs
, unsigned dw
)
883 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
884 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
885 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
887 uint32_t *new_ptr_ib_size
;
889 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
891 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
894 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
896 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
899 if (!amdgpu_cs_has_chaining(cs
))
902 /* Allocate a new chunk */
903 if (rcs
->num_prev
>= rcs
->max_prev
) {
904 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
905 struct radeon_winsys_cs_chunk
*new_prev
;
907 new_prev
= REALLOC(rcs
->prev
,
908 sizeof(*new_prev
) * rcs
->max_prev
,
909 sizeof(*new_prev
) * new_max_prev
);
913 rcs
->prev
= new_prev
;
914 rcs
->max_prev
= new_max_prev
;
917 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
))
920 assert(ib
->used_ib_space
== 0);
921 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
923 /* This space was originally reserved. */
924 rcs
->current
.max_dw
+= 4;
925 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
927 /* Pad with NOPs and add INDIRECT_BUFFER packet */
928 while ((rcs
->current
.cdw
& 7) != 4)
929 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
931 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
932 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
933 radeon_emit(rcs
, va
);
934 radeon_emit(rcs
, va
>> 32);
935 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
];
936 radeon_emit(rcs
, S_3F2_CHAIN(1) | S_3F2_VALID(1));
938 assert((rcs
->current
.cdw
& 7) == 0);
939 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
941 *ib
->ptr_ib_size
|= rcs
->current
.cdw
;
942 ib
->ptr_ib_size
= new_ptr_ib_size
;
944 /* Hook up the new chunk */
945 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
946 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
947 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
950 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
951 ib
->base
.current
.cdw
= 0;
953 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
954 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
956 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
957 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
962 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs
*rcs
,
963 struct radeon_bo_list_item
*list
)
965 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
969 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
970 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
971 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
972 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
975 return cs
->num_real_buffers
;
978 DEBUG_GET_ONCE_BOOL_OPTION(all_bos
, "RADEON_ALL_BOS", false)
980 static void amdgpu_add_fence_dependency(struct amdgpu_cs
*acs
,
981 struct amdgpu_cs_buffer
*buffer
)
983 struct amdgpu_cs_context
*cs
= acs
->csc
;
984 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
985 struct amdgpu_cs_fence
*dep
;
986 unsigned new_num_fences
= 0;
988 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
989 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
992 if (bo_fence
->ctx
== acs
->ctx
&&
993 bo_fence
->fence
.ip_type
== cs
->request
.ip_type
&&
994 bo_fence
->fence
.ip_instance
== cs
->request
.ip_instance
&&
995 bo_fence
->fence
.ring
== cs
->request
.ring
)
998 if (amdgpu_fence_wait((void *)bo_fence
, 0, false))
1001 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1004 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1007 if (bo_fence
->submission_in_progress
)
1008 os_wait_until_zero(&bo_fence
->submission_in_progress
,
1009 PIPE_TIMEOUT_INFINITE
);
1011 idx
= cs
->request
.number_of_dependencies
++;
1012 if (idx
>= cs
->max_dependencies
) {
1015 cs
->max_dependencies
= idx
+ 8;
1016 size
= cs
->max_dependencies
* sizeof(struct amdgpu_cs_fence
);
1017 cs
->request
.dependencies
= realloc(cs
->request
.dependencies
, size
);
1020 dep
= &cs
->request
.dependencies
[idx
];
1021 memcpy(dep
, &bo_fence
->fence
, sizeof(*dep
));
1024 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1025 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1027 bo
->num_fences
= new_num_fences
;
1030 /* Add the given list of fences to the buffer's fence list.
1032 * Must be called with the winsys bo_fence_lock held.
1034 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1035 unsigned num_fences
,
1036 struct pipe_fence_handle
**fences
)
1038 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1039 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1040 struct pipe_fence_handle
**new_fences
=
1042 bo
->num_fences
* sizeof(*new_fences
),
1043 new_max_fences
* sizeof(*new_fences
));
1044 if (likely(new_fences
)) {
1045 bo
->fences
= new_fences
;
1046 bo
->max_fences
= new_max_fences
;
1050 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1051 if (!bo
->num_fences
)
1054 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1055 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1057 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1063 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1064 bo
->fences
[bo
->num_fences
] = NULL
;
1065 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1070 static void amdgpu_add_fence_dependencies_list(struct amdgpu_cs
*acs
,
1071 struct pipe_fence_handle
*fence
,
1072 unsigned num_buffers
,
1073 struct amdgpu_cs_buffer
*buffers
)
1075 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1076 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1077 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1079 amdgpu_add_fence_dependency(acs
, buffer
);
1080 p_atomic_inc(&bo
->num_active_ioctls
);
1081 amdgpu_add_fences(bo
, 1, &fence
);
1085 /* Since the kernel driver doesn't synchronize execution between different
1086 * rings automatically, we have to add fence dependencies manually.
1088 static void amdgpu_add_fence_dependencies(struct amdgpu_cs
*acs
)
1090 struct amdgpu_cs_context
*cs
= acs
->csc
;
1092 cs
->request
.number_of_dependencies
= 0;
1094 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1095 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1096 amdgpu_add_fence_dependencies_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1099 /* Add backing of sparse buffers to the buffer list.
1101 * This is done late, during submission, to keep the buffer list short before
1102 * submit, and to avoid managing fences for the backing buffers.
1104 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1106 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1107 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1108 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1110 mtx_lock(&bo
->u
.sparse
.commit_lock
);
1112 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1113 /* We can directly add the buffer here, because we know that each
1114 * backing buffer occurs only once.
1116 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1118 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1119 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1123 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1124 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1125 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1128 mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1134 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1136 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1137 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1138 struct amdgpu_cs_context
*cs
= acs
->cst
;
1141 cs
->request
.fence_info
.handle
= NULL
;
1142 if (amdgpu_cs_has_user_fence(cs
)) {
1143 cs
->request
.fence_info
.handle
= acs
->ctx
->user_fence_bo
;
1144 cs
->request
.fence_info
.offset
= acs
->ring_type
;
1147 /* Create the buffer list.
1148 * Use a buffer list containing all allocated buffers if requested.
1150 if (debug_get_option_all_bos()) {
1151 struct amdgpu_winsys_bo
*bo
;
1152 amdgpu_bo_handle
*handles
;
1155 mtx_lock(&ws
->global_bo_list_lock
);
1157 handles
= malloc(sizeof(handles
[0]) * ws
->num_buffers
);
1159 mtx_unlock(&ws
->global_bo_list_lock
);
1160 amdgpu_cs_context_cleanup(cs
);
1161 cs
->error_code
= -ENOMEM
;
1165 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1166 assert(num
< ws
->num_buffers
);
1167 handles
[num
++] = bo
->bo
;
1170 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1172 &cs
->request
.resources
);
1174 mtx_unlock(&ws
->global_bo_list_lock
);
1176 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1181 if (cs
->max_real_submit
< cs
->num_real_buffers
) {
1185 cs
->handles
= MALLOC(sizeof(*cs
->handles
) * cs
->num_real_buffers
);
1186 cs
->flags
= MALLOC(sizeof(*cs
->flags
) * cs
->num_real_buffers
);
1188 if (!cs
->handles
|| !cs
->flags
) {
1189 cs
->max_real_submit
= 0;
1195 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1196 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1198 assert(buffer
->u
.real
.priority_usage
!= 0);
1200 cs
->handles
[i
] = buffer
->bo
->bo
;
1201 cs
->flags
[i
] = (util_last_bit64(buffer
->u
.real
.priority_usage
) - 1) / 4;
1204 r
= amdgpu_bo_list_create(ws
->dev
, cs
->num_real_buffers
,
1205 cs
->handles
, cs
->flags
,
1206 &cs
->request
.resources
);
1211 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1212 cs
->request
.resources
= NULL
;
1213 amdgpu_fence_signalled(cs
->fence
);
1218 if (acs
->ctx
->num_rejected_cs
)
1221 r
= amdgpu_cs_submit(acs
->ctx
->ctx
, 0, &cs
->request
, 1);
1226 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1227 else if (r
== -ECANCELED
)
1228 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1230 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1231 "see dmesg for more information (%i).\n", r
);
1233 amdgpu_fence_signalled(cs
->fence
);
1235 acs
->ctx
->num_rejected_cs
++;
1236 ws
->num_total_rejected_cs
++;
1239 uint64_t *user_fence
= NULL
;
1240 if (amdgpu_cs_has_user_fence(cs
))
1241 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+
1242 cs
->request
.fence_info
.offset
;
1243 amdgpu_fence_submitted(cs
->fence
, &cs
->request
, user_fence
);
1247 if (cs
->request
.resources
)
1248 amdgpu_bo_list_destroy(cs
->request
.resources
);
1251 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1252 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1253 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1254 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1255 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1256 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1258 amdgpu_cs_context_cleanup(cs
);
1261 /* Make sure the previous submission is completed. */
1262 void amdgpu_cs_sync_flush(struct radeon_winsys_cs
*rcs
)
1264 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1266 /* Wait for any pending ioctl of this CS to complete. */
1267 util_queue_fence_wait(&cs
->flush_completed
);
1270 static int amdgpu_cs_flush(struct radeon_winsys_cs
*rcs
,
1272 struct pipe_fence_handle
**fence
)
1274 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1275 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1278 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1280 switch (cs
->ring_type
) {
1282 /* pad DMA ring to 8 DWs */
1283 if (ws
->info
.chip_class
<= SI
) {
1284 while (rcs
->current
.cdw
& 7)
1285 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1287 while (rcs
->current
.cdw
& 7)
1288 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1292 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1293 if (ws
->info
.gfx_ib_pad_with_type2
) {
1294 while (rcs
->current
.cdw
& 7)
1295 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1297 while (rcs
->current
.cdw
& 7)
1298 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1301 /* Also pad the const IB. */
1302 if (cs
->const_ib
.ib_mapped
)
1303 while (!cs
->const_ib
.base
.current
.cdw
|| (cs
->const_ib
.base
.current
.cdw
& 7))
1304 radeon_emit(&cs
->const_ib
.base
, 0xffff1000); /* type3 nop packet */
1306 if (cs
->const_preamble_ib
.ib_mapped
)
1307 while (!cs
->const_preamble_ib
.base
.current
.cdw
|| (cs
->const_preamble_ib
.base
.current
.cdw
& 7))
1308 radeon_emit(&cs
->const_preamble_ib
.base
, 0xffff1000);
1311 while (rcs
->current
.cdw
& 15)
1312 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1318 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1319 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1322 /* If the CS is not empty or overflowed.... */
1323 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1324 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1325 !debug_get_option_noop())) {
1326 struct amdgpu_cs_context
*cur
= cs
->csc
;
1329 amdgpu_ib_finalize(&cs
->main
);
1331 if (cs
->const_ib
.ib_mapped
)
1332 amdgpu_ib_finalize(&cs
->const_ib
);
1334 if (cs
->const_preamble_ib
.ib_mapped
)
1335 amdgpu_ib_finalize(&cs
->const_preamble_ib
);
1337 /* Create a fence. */
1338 amdgpu_fence_reference(&cur
->fence
, NULL
);
1339 if (cs
->next_fence
) {
1340 /* just move the reference */
1341 cur
->fence
= cs
->next_fence
;
1342 cs
->next_fence
= NULL
;
1344 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1345 cur
->request
.ip_type
,
1346 cur
->request
.ip_instance
,
1350 amdgpu_fence_reference(fence
, cur
->fence
);
1352 amdgpu_cs_sync_flush(rcs
);
1356 * This fence must be held until the submission is queued to ensure
1357 * that the order of fence dependency updates matches the order of
1360 mtx_lock(&ws
->bo_fence_lock
);
1361 amdgpu_add_fence_dependencies(cs
);
1363 /* Swap command streams. "cst" is going to be submitted. */
1368 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1369 amdgpu_cs_submit_ib
, NULL
);
1370 /* The submission has been queued, unlock the fence now. */
1371 mtx_unlock(&ws
->bo_fence_lock
);
1373 if (!(flags
& RADEON_FLUSH_ASYNC
)) {
1374 amdgpu_cs_sync_flush(rcs
);
1375 error_code
= cur
->error_code
;
1378 amdgpu_cs_context_cleanup(cs
->csc
);
1381 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1382 if (cs
->const_ib
.ib_mapped
)
1383 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST
);
1384 if (cs
->const_preamble_ib
.ib_mapped
)
1385 amdgpu_get_new_ib(&ws
->base
, cs
, IB_CONST_PREAMBLE
);
1387 cs
->main
.base
.used_gart
= 0;
1388 cs
->main
.base
.used_vram
= 0;
1390 if (cs
->ring_type
== RING_GFX
)
1392 else if (cs
->ring_type
== RING_DMA
)
1398 static void amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs
)
1400 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1402 amdgpu_cs_sync_flush(rcs
);
1403 util_queue_fence_destroy(&cs
->flush_completed
);
1404 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1405 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1406 FREE(cs
->main
.base
.prev
);
1407 pb_reference(&cs
->const_ib
.big_ib_buffer
, NULL
);
1408 FREE(cs
->const_ib
.base
.prev
);
1409 pb_reference(&cs
->const_preamble_ib
.big_ib_buffer
, NULL
);
1410 FREE(cs
->const_preamble_ib
.base
.prev
);
1411 amdgpu_destroy_cs_context(&cs
->csc1
);
1412 amdgpu_destroy_cs_context(&cs
->csc2
);
1413 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1417 static bool amdgpu_bo_is_referenced(struct radeon_winsys_cs
*rcs
,
1418 struct pb_buffer
*_buf
,
1419 enum radeon_bo_usage usage
)
1421 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1422 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1424 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1427 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1429 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1430 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1431 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1432 ws
->base
.cs_create
= amdgpu_cs_create
;
1433 ws
->base
.cs_add_const_ib
= amdgpu_cs_add_const_ib
;
1434 ws
->base
.cs_add_const_preamble_ib
= amdgpu_cs_add_const_preamble_ib
;
1435 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1436 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1437 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1438 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1439 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1440 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1441 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1442 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1443 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1444 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1445 ws
->base
.fence_reference
= amdgpu_fence_reference
;