2 * Copyright © 2008 Jérôme Glisse
3 * Copyright © 2010 Marek Olšák <maraeo@gmail.com>
4 * Copyright © 2015 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
17 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
19 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 #include "amdgpu_cs.h"
30 #include "util/os_time.h"
34 #include "amd/common/sid.h"
36 #ifndef AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
37 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
40 #ifndef AMDGPU_CHUNK_ID_BO_HANDLES
41 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
44 DEBUG_GET_ONCE_BOOL_OPTION(noop
, "RADEON_NOOP", false)
48 static struct pipe_fence_handle
*
49 amdgpu_fence_create(struct amdgpu_ctx
*ctx
, unsigned ip_type
,
50 unsigned ip_instance
, unsigned ring
)
52 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
54 fence
->reference
.count
= 1;
57 fence
->fence
.context
= ctx
->ctx
;
58 fence
->fence
.ip_type
= ip_type
;
59 fence
->fence
.ip_instance
= ip_instance
;
60 fence
->fence
.ring
= ring
;
61 util_queue_fence_init(&fence
->submitted
);
62 util_queue_fence_reset(&fence
->submitted
);
63 p_atomic_inc(&ctx
->refcount
);
64 return (struct pipe_fence_handle
*)fence
;
67 static struct pipe_fence_handle
*
68 amdgpu_fence_import_syncobj(struct radeon_winsys
*rws
, int fd
)
70 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
71 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
77 pipe_reference_init(&fence
->reference
, 1);
80 r
= amdgpu_cs_import_syncobj(ws
->dev
, fd
, &fence
->syncobj
);
86 util_queue_fence_init(&fence
->submitted
);
88 assert(amdgpu_fence_is_syncobj(fence
));
89 return (struct pipe_fence_handle
*)fence
;
92 static struct pipe_fence_handle
*
93 amdgpu_fence_import_sync_file(struct radeon_winsys
*rws
, int fd
)
95 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
96 struct amdgpu_fence
*fence
= CALLOC_STRUCT(amdgpu_fence
);
101 pipe_reference_init(&fence
->reference
, 1);
103 /* fence->ctx == NULL means that the fence is syncobj-based. */
105 /* Convert sync_file into syncobj. */
106 int r
= amdgpu_cs_create_syncobj(ws
->dev
, &fence
->syncobj
);
112 r
= amdgpu_cs_syncobj_import_sync_file(ws
->dev
, fence
->syncobj
, fd
);
114 amdgpu_cs_destroy_syncobj(ws
->dev
, fence
->syncobj
);
119 util_queue_fence_init(&fence
->submitted
);
121 return (struct pipe_fence_handle
*)fence
;
124 static int amdgpu_fence_export_sync_file(struct radeon_winsys
*rws
,
125 struct pipe_fence_handle
*pfence
)
127 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
128 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
130 if (amdgpu_fence_is_syncobj(fence
)) {
133 /* Convert syncobj into sync_file. */
134 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, fence
->syncobj
, &fd
);
138 util_queue_fence_wait(&fence
->submitted
);
140 /* Convert the amdgpu fence into a fence FD. */
142 if (amdgpu_cs_fence_to_handle(ws
->dev
, &fence
->fence
,
143 AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
,
150 static int amdgpu_export_signalled_sync_file(struct radeon_winsys
*rws
)
152 struct amdgpu_winsys
*ws
= amdgpu_winsys(rws
);
156 int r
= amdgpu_cs_create_syncobj2(ws
->dev
, DRM_SYNCOBJ_CREATE_SIGNALED
,
162 r
= amdgpu_cs_syncobj_export_sync_file(ws
->dev
, syncobj
, &fd
);
167 amdgpu_cs_destroy_syncobj(ws
->dev
, syncobj
);
171 static void amdgpu_fence_submitted(struct pipe_fence_handle
*fence
,
173 uint64_t *user_fence_cpu_address
)
175 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
177 rfence
->fence
.fence
= seq_no
;
178 rfence
->user_fence_cpu_address
= user_fence_cpu_address
;
179 util_queue_fence_signal(&rfence
->submitted
);
182 static void amdgpu_fence_signalled(struct pipe_fence_handle
*fence
)
184 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
186 rfence
->signalled
= true;
187 util_queue_fence_signal(&rfence
->submitted
);
190 bool amdgpu_fence_wait(struct pipe_fence_handle
*fence
, uint64_t timeout
,
193 struct amdgpu_fence
*rfence
= (struct amdgpu_fence
*)fence
;
196 uint64_t *user_fence_cpu
;
199 if (rfence
->signalled
)
202 /* Handle syncobjs. */
203 if (amdgpu_fence_is_syncobj(rfence
)) {
204 /* Absolute timeouts are only be used by BO fences, which aren't
205 * backed by syncobjs.
209 if (amdgpu_cs_syncobj_wait(rfence
->ws
->dev
, &rfence
->syncobj
, 1,
213 rfence
->signalled
= true;
218 abs_timeout
= timeout
;
220 abs_timeout
= os_time_get_absolute_timeout(timeout
);
222 /* The fence might not have a number assigned if its IB is being
223 * submitted in the other thread right now. Wait until the submission
225 if (!util_queue_fence_wait_timeout(&rfence
->submitted
, abs_timeout
))
228 user_fence_cpu
= rfence
->user_fence_cpu_address
;
229 if (user_fence_cpu
) {
230 if (*user_fence_cpu
>= rfence
->fence
.fence
) {
231 rfence
->signalled
= true;
235 /* No timeout, just query: no need for the ioctl. */
236 if (!absolute
&& !timeout
)
240 /* Now use the libdrm query. */
241 r
= amdgpu_cs_query_fence_status(&rfence
->fence
,
243 AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE
,
246 fprintf(stderr
, "amdgpu: amdgpu_cs_query_fence_status failed.\n");
251 /* This variable can only transition from false to true, so it doesn't
252 * matter if threads race for it. */
253 rfence
->signalled
= true;
259 static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys
*rws
,
260 struct pipe_fence_handle
*fence
,
263 return amdgpu_fence_wait(fence
, timeout
, false);
266 static struct pipe_fence_handle
*
267 amdgpu_cs_get_next_fence(struct radeon_cmdbuf
*rcs
)
269 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
270 struct pipe_fence_handle
*fence
= NULL
;
272 if (debug_get_option_noop())
275 if (cs
->next_fence
) {
276 amdgpu_fence_reference(&fence
, cs
->next_fence
);
280 fence
= amdgpu_fence_create(cs
->ctx
,
281 cs
->csc
->ib
[IB_MAIN
].ip_type
,
282 cs
->csc
->ib
[IB_MAIN
].ip_instance
,
283 cs
->csc
->ib
[IB_MAIN
].ring
);
287 amdgpu_fence_reference(&cs
->next_fence
, fence
);
293 static struct radeon_winsys_ctx
*amdgpu_ctx_create(struct radeon_winsys
*ws
)
295 struct amdgpu_ctx
*ctx
= CALLOC_STRUCT(amdgpu_ctx
);
297 struct amdgpu_bo_alloc_request alloc_buffer
= {};
298 amdgpu_bo_handle buf_handle
;
303 ctx
->ws
= amdgpu_winsys(ws
);
305 ctx
->initial_num_total_rejected_cs
= ctx
->ws
->num_total_rejected_cs
;
307 r
= amdgpu_cs_ctx_create(ctx
->ws
->dev
, &ctx
->ctx
);
309 fprintf(stderr
, "amdgpu: amdgpu_cs_ctx_create failed. (%i)\n", r
);
313 alloc_buffer
.alloc_size
= ctx
->ws
->info
.gart_page_size
;
314 alloc_buffer
.phys_alignment
= ctx
->ws
->info
.gart_page_size
;
315 alloc_buffer
.preferred_heap
= AMDGPU_GEM_DOMAIN_GTT
;
317 r
= amdgpu_bo_alloc(ctx
->ws
->dev
, &alloc_buffer
, &buf_handle
);
319 fprintf(stderr
, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r
);
320 goto error_user_fence_alloc
;
323 r
= amdgpu_bo_cpu_map(buf_handle
, (void**)&ctx
->user_fence_cpu_address_base
);
325 fprintf(stderr
, "amdgpu: amdgpu_bo_cpu_map failed. (%i)\n", r
);
326 goto error_user_fence_map
;
329 memset(ctx
->user_fence_cpu_address_base
, 0, alloc_buffer
.alloc_size
);
330 ctx
->user_fence_bo
= buf_handle
;
332 return (struct radeon_winsys_ctx
*)ctx
;
334 error_user_fence_map
:
335 amdgpu_bo_free(buf_handle
);
336 error_user_fence_alloc
:
337 amdgpu_cs_ctx_free(ctx
->ctx
);
343 static void amdgpu_ctx_destroy(struct radeon_winsys_ctx
*rwctx
)
345 amdgpu_ctx_unref((struct amdgpu_ctx
*)rwctx
);
348 static enum pipe_reset_status
349 amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx
)
351 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
352 uint32_t result
, hangs
;
355 /* Return a failure due to a rejected command submission. */
356 if (ctx
->ws
->num_total_rejected_cs
> ctx
->initial_num_total_rejected_cs
) {
357 return ctx
->num_rejected_cs
? PIPE_GUILTY_CONTEXT_RESET
:
358 PIPE_INNOCENT_CONTEXT_RESET
;
361 /* Return a failure due to a GPU hang. */
362 r
= amdgpu_cs_query_reset_state(ctx
->ctx
, &result
, &hangs
);
364 fprintf(stderr
, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r
);
365 return PIPE_NO_RESET
;
369 case AMDGPU_CTX_GUILTY_RESET
:
370 return PIPE_GUILTY_CONTEXT_RESET
;
371 case AMDGPU_CTX_INNOCENT_RESET
:
372 return PIPE_INNOCENT_CONTEXT_RESET
;
373 case AMDGPU_CTX_UNKNOWN_RESET
:
374 return PIPE_UNKNOWN_CONTEXT_RESET
;
375 case AMDGPU_CTX_NO_RESET
:
377 return PIPE_NO_RESET
;
381 /* COMMAND SUBMISSION */
383 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context
*cs
)
385 return cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD
&&
386 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCE
&&
387 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_UVD_ENC
&&
388 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_DEC
&&
389 cs
->ib
[IB_MAIN
].ip_type
!= AMDGPU_HW_IP_VCN_ENC
;
392 static bool amdgpu_cs_has_chaining(struct amdgpu_cs
*cs
)
394 return cs
->ctx
->ws
->info
.chip_class
>= CIK
&&
395 cs
->ring_type
== RING_GFX
;
398 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type
)
400 if (ring_type
== RING_GFX
)
401 return 4; /* for chaining */
406 int amdgpu_lookup_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
408 unsigned hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
409 int i
= cs
->buffer_indices_hashlist
[hash
];
410 struct amdgpu_cs_buffer
*buffers
;
414 buffers
= cs
->real_buffers
;
415 num_buffers
= cs
->num_real_buffers
;
416 } else if (!bo
->sparse
) {
417 buffers
= cs
->slab_buffers
;
418 num_buffers
= cs
->num_slab_buffers
;
420 buffers
= cs
->sparse_buffers
;
421 num_buffers
= cs
->num_sparse_buffers
;
424 /* not found or found */
425 if (i
< 0 || (i
< num_buffers
&& buffers
[i
].bo
== bo
))
428 /* Hash collision, look for the BO in the list of buffers linearly. */
429 for (i
= num_buffers
- 1; i
>= 0; i
--) {
430 if (buffers
[i
].bo
== bo
) {
431 /* Put this buffer in the hash list.
432 * This will prevent additional hash collisions if there are
433 * several consecutive lookup_buffer calls for the same buffer.
435 * Example: Assuming buffers A,B,C collide in the hash list,
436 * the following sequence of buffers:
437 * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
438 * will collide here: ^ and here: ^,
439 * meaning that we should get very few collisions in the end. */
440 cs
->buffer_indices_hashlist
[hash
] = i
;
448 amdgpu_do_add_real_buffer(struct amdgpu_cs_context
*cs
, struct amdgpu_winsys_bo
*bo
)
450 struct amdgpu_cs_buffer
*buffer
;
453 /* New buffer, check if the backing array is large enough. */
454 if (cs
->num_real_buffers
>= cs
->max_real_buffers
) {
456 MAX2(cs
->max_real_buffers
+ 16, (unsigned)(cs
->max_real_buffers
* 1.3));
457 struct amdgpu_cs_buffer
*new_buffers
;
459 new_buffers
= MALLOC(new_max
* sizeof(*new_buffers
));
462 fprintf(stderr
, "amdgpu_do_add_buffer: allocation failed\n");
467 memcpy(new_buffers
, cs
->real_buffers
, cs
->num_real_buffers
* sizeof(*new_buffers
));
469 FREE(cs
->real_buffers
);
471 cs
->max_real_buffers
= new_max
;
472 cs
->real_buffers
= new_buffers
;
475 idx
= cs
->num_real_buffers
;
476 buffer
= &cs
->real_buffers
[idx
];
478 memset(buffer
, 0, sizeof(*buffer
));
479 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
480 p_atomic_inc(&bo
->num_cs_references
);
481 cs
->num_real_buffers
++;
487 amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs
*acs
, struct amdgpu_winsys_bo
*bo
)
489 struct amdgpu_cs_context
*cs
= acs
->csc
;
491 int idx
= amdgpu_lookup_buffer(cs
, bo
);
496 idx
= amdgpu_do_add_real_buffer(cs
, bo
);
498 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
499 cs
->buffer_indices_hashlist
[hash
] = idx
;
501 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
502 acs
->main
.base
.used_vram
+= bo
->base
.size
;
503 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
504 acs
->main
.base
.used_gart
+= bo
->base
.size
;
509 static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs
*acs
,
510 struct amdgpu_winsys_bo
*bo
)
512 struct amdgpu_cs_context
*cs
= acs
->csc
;
513 struct amdgpu_cs_buffer
*buffer
;
515 int idx
= amdgpu_lookup_buffer(cs
, bo
);
521 real_idx
= amdgpu_lookup_or_add_real_buffer(acs
, bo
->u
.slab
.real
);
525 /* New buffer, check if the backing array is large enough. */
526 if (cs
->num_slab_buffers
>= cs
->max_slab_buffers
) {
528 MAX2(cs
->max_slab_buffers
+ 16, (unsigned)(cs
->max_slab_buffers
* 1.3));
529 struct amdgpu_cs_buffer
*new_buffers
;
531 new_buffers
= REALLOC(cs
->slab_buffers
,
532 cs
->max_slab_buffers
* sizeof(*new_buffers
),
533 new_max
* sizeof(*new_buffers
));
535 fprintf(stderr
, "amdgpu_lookup_or_add_slab_buffer: allocation failed\n");
539 cs
->max_slab_buffers
= new_max
;
540 cs
->slab_buffers
= new_buffers
;
543 idx
= cs
->num_slab_buffers
;
544 buffer
= &cs
->slab_buffers
[idx
];
546 memset(buffer
, 0, sizeof(*buffer
));
547 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
548 buffer
->u
.slab
.real_idx
= real_idx
;
549 p_atomic_inc(&bo
->num_cs_references
);
550 cs
->num_slab_buffers
++;
552 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
553 cs
->buffer_indices_hashlist
[hash
] = idx
;
558 static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs
*acs
,
559 struct amdgpu_winsys_bo
*bo
)
561 struct amdgpu_cs_context
*cs
= acs
->csc
;
562 struct amdgpu_cs_buffer
*buffer
;
564 int idx
= amdgpu_lookup_buffer(cs
, bo
);
569 /* New buffer, check if the backing array is large enough. */
570 if (cs
->num_sparse_buffers
>= cs
->max_sparse_buffers
) {
572 MAX2(cs
->max_sparse_buffers
+ 16, (unsigned)(cs
->max_sparse_buffers
* 1.3));
573 struct amdgpu_cs_buffer
*new_buffers
;
575 new_buffers
= REALLOC(cs
->sparse_buffers
,
576 cs
->max_sparse_buffers
* sizeof(*new_buffers
),
577 new_max
* sizeof(*new_buffers
));
579 fprintf(stderr
, "amdgpu_lookup_or_add_sparse_buffer: allocation failed\n");
583 cs
->max_sparse_buffers
= new_max
;
584 cs
->sparse_buffers
= new_buffers
;
587 idx
= cs
->num_sparse_buffers
;
588 buffer
= &cs
->sparse_buffers
[idx
];
590 memset(buffer
, 0, sizeof(*buffer
));
591 amdgpu_winsys_bo_reference(&buffer
->bo
, bo
);
592 p_atomic_inc(&bo
->num_cs_references
);
593 cs
->num_sparse_buffers
++;
595 hash
= bo
->unique_id
& (ARRAY_SIZE(cs
->buffer_indices_hashlist
)-1);
596 cs
->buffer_indices_hashlist
[hash
] = idx
;
598 /* We delay adding the backing buffers until we really have to. However,
599 * we cannot delay accounting for memory use.
601 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
603 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
604 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
605 acs
->main
.base
.used_vram
+= backing
->bo
->base
.size
;
606 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
607 acs
->main
.base
.used_gart
+= backing
->bo
->base
.size
;
610 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
615 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf
*rcs
,
616 struct pb_buffer
*buf
,
617 enum radeon_bo_usage usage
,
618 enum radeon_bo_domain domains
,
619 enum radeon_bo_priority priority
)
621 /* Don't use the "domains" parameter. Amdgpu doesn't support changing
622 * the buffer placement during command submission.
624 struct amdgpu_cs
*acs
= amdgpu_cs(rcs
);
625 struct amdgpu_cs_context
*cs
= acs
->csc
;
626 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)buf
;
627 struct amdgpu_cs_buffer
*buffer
;
630 /* Fast exit for no-op calls.
631 * This is very effective with suballocators and linear uploaders that
632 * are outside of the winsys.
634 if (bo
== cs
->last_added_bo
&&
635 (usage
& cs
->last_added_bo_usage
) == usage
&&
636 (1u << priority
) & cs
->last_added_bo_priority_usage
)
637 return cs
->last_added_bo_index
;
641 index
= amdgpu_lookup_or_add_slab_buffer(acs
, bo
);
645 buffer
= &cs
->slab_buffers
[index
];
646 buffer
->usage
|= usage
;
648 usage
&= ~RADEON_USAGE_SYNCHRONIZED
;
649 index
= buffer
->u
.slab
.real_idx
;
651 index
= amdgpu_lookup_or_add_real_buffer(acs
, bo
);
656 buffer
= &cs
->real_buffers
[index
];
658 index
= amdgpu_lookup_or_add_sparse_buffer(acs
, bo
);
662 buffer
= &cs
->sparse_buffers
[index
];
665 buffer
->u
.real
.priority_usage
|= 1u << priority
;
666 buffer
->usage
|= usage
;
668 cs
->last_added_bo
= bo
;
669 cs
->last_added_bo_index
= index
;
670 cs
->last_added_bo_usage
= buffer
->usage
;
671 cs
->last_added_bo_priority_usage
= buffer
->u
.real
.priority_usage
;
675 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
,
676 enum ring_type ring_type
)
678 struct pb_buffer
*pb
;
680 unsigned buffer_size
;
682 /* Always create a buffer that is at least as large as the maximum seen IB
683 * size, aligned to a power of two (and multiplied by 4 to reduce internal
684 * fragmentation if chaining is not available). Limit to 512k dwords, which
685 * is the largest power of two that fits into the size field of the
686 * INDIRECT_BUFFER packet.
688 if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib
)))
689 buffer_size
= 4 *util_next_power_of_two(ib
->max_ib_size
);
691 buffer_size
= 4 *util_next_power_of_two(4 * ib
->max_ib_size
);
693 buffer_size
= MIN2(buffer_size
, 4 * 512 * 1024);
695 switch (ib
->ib_type
) {
697 buffer_size
= MAX2(buffer_size
, 8 * 1024 * 4);
700 unreachable("unhandled IB type");
703 pb
= ws
->base
.buffer_create(&ws
->base
, buffer_size
,
704 ws
->info
.gart_page_size
,
706 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
707 (ring_type
== RING_GFX
||
708 ring_type
== RING_COMPUTE
||
709 ring_type
== RING_DMA
?
710 RADEON_FLAG_READ_ONLY
| RADEON_FLAG_GTT_WC
: 0));
714 mapped
= ws
->base
.buffer_map(pb
, NULL
, PIPE_TRANSFER_WRITE
);
716 pb_reference(&pb
, NULL
);
720 pb_reference(&ib
->big_ib_buffer
, pb
);
721 pb_reference(&pb
, NULL
);
723 ib
->ib_mapped
= mapped
;
724 ib
->used_ib_space
= 0;
729 static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type
)
733 /* Smaller submits means the GPU gets busy sooner and there is less
734 * waiting for buffers and fences. Proof:
735 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
739 unreachable("bad ib_type");
743 static bool amdgpu_get_new_ib(struct radeon_winsys
*ws
, struct amdgpu_cs
*cs
,
744 enum ib_type ib_type
)
746 struct amdgpu_winsys
*aws
= (struct amdgpu_winsys
*)ws
;
747 /* Small IBs are better than big IBs, because the GPU goes idle quicker
748 * and there is less waiting for buffers and fences. Proof:
749 * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
751 struct amdgpu_ib
*ib
= NULL
;
752 struct drm_amdgpu_cs_chunk_ib
*info
= &cs
->csc
->ib
[ib_type
];
753 unsigned ib_size
= 0;
758 ib_size
= 4 * 1024 * 4;
761 unreachable("unhandled IB type");
764 if (!amdgpu_cs_has_chaining(cs
)) {
765 ib_size
= MAX2(ib_size
,
766 4 * MIN2(util_next_power_of_two(ib
->max_ib_size
),
767 amdgpu_ib_max_submit_dwords(ib_type
)));
770 ib
->max_ib_size
= ib
->max_ib_size
- ib
->max_ib_size
/ 32;
772 ib
->base
.prev_dw
= 0;
773 ib
->base
.num_prev
= 0;
774 ib
->base
.current
.cdw
= 0;
775 ib
->base
.current
.buf
= NULL
;
777 /* Allocate a new buffer for IBs if the current buffer is all used. */
778 if (!ib
->big_ib_buffer
||
779 ib
->used_ib_space
+ ib_size
> ib
->big_ib_buffer
->size
) {
780 if (!amdgpu_ib_new_buffer(aws
, ib
, cs
->ring_type
))
784 info
->va_start
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
+ ib
->used_ib_space
;
786 /* ib_bytes is in dwords and the conversion to bytes will be done before
788 ib
->ptr_ib_size
= &info
->ib_bytes
;
789 ib
->ptr_ib_size_inside_ib
= false;
791 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
792 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
794 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
796 ib_size
= ib
->big_ib_buffer
->size
- ib
->used_ib_space
;
797 ib
->base
.current
.max_dw
= ib_size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
801 static void amdgpu_set_ib_size(struct amdgpu_ib
*ib
)
803 if (ib
->ptr_ib_size_inside_ib
) {
804 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
|
805 S_3F2_CHAIN(1) | S_3F2_VALID(1);
807 *ib
->ptr_ib_size
= ib
->base
.current
.cdw
;
811 static void amdgpu_ib_finalize(struct amdgpu_winsys
*ws
, struct amdgpu_ib
*ib
)
813 amdgpu_set_ib_size(ib
);
814 ib
->used_ib_space
+= ib
->base
.current
.cdw
* 4;
815 ib
->used_ib_space
= align(ib
->used_ib_space
, ws
->info
.ib_start_alignment
);
816 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, ib
->base
.prev_dw
+ ib
->base
.current
.cdw
);
819 static bool amdgpu_init_cs_context(struct amdgpu_winsys
*ws
,
820 struct amdgpu_cs_context
*cs
,
821 enum ring_type ring_type
)
825 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_DMA
;
829 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD
;
833 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_UVD_ENC
;
837 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCE
;
841 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_DEC
;
845 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_ENC
;
849 cs
->ib
[IB_MAIN
].ip_type
= AMDGPU_HW_IP_VCN_JPEG
;
854 cs
->ib
[IB_MAIN
].ip_type
= ring_type
== RING_GFX
? AMDGPU_HW_IP_GFX
:
855 AMDGPU_HW_IP_COMPUTE
;
857 /* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
858 * invalidation is the beginning of IBs (the previous commit does that),
859 * because completion of an IB doesn't care about the state of GPU caches,
860 * but the beginning of an IB does. Draw calls from multiple IBs can be
861 * executed in parallel, so draw calls from the current IB can finish after
862 * the next IB starts drawing, and so the cache flush at the end of IB
865 if (ws
->info
.drm_minor
>= 26)
866 cs
->ib
[IB_MAIN
].flags
= AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
;
873 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
874 cs
->last_added_bo
= NULL
;
878 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context
*cs
)
882 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
883 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_cs_references
);
884 amdgpu_winsys_bo_reference(&cs
->real_buffers
[i
].bo
, NULL
);
886 for (i
= 0; i
< cs
->num_slab_buffers
; i
++) {
887 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_cs_references
);
888 amdgpu_winsys_bo_reference(&cs
->slab_buffers
[i
].bo
, NULL
);
890 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++) {
891 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_cs_references
);
892 amdgpu_winsys_bo_reference(&cs
->sparse_buffers
[i
].bo
, NULL
);
894 for (i
= 0; i
< cs
->num_fence_dependencies
; i
++)
895 amdgpu_fence_reference(&cs
->fence_dependencies
[i
], NULL
);
896 for (i
= 0; i
< cs
->num_syncobj_to_signal
; i
++)
897 amdgpu_fence_reference(&cs
->syncobj_to_signal
[i
], NULL
);
899 cs
->num_real_buffers
= 0;
900 cs
->num_slab_buffers
= 0;
901 cs
->num_sparse_buffers
= 0;
902 cs
->num_fence_dependencies
= 0;
903 cs
->num_syncobj_to_signal
= 0;
904 amdgpu_fence_reference(&cs
->fence
, NULL
);
906 memset(cs
->buffer_indices_hashlist
, -1, sizeof(cs
->buffer_indices_hashlist
));
907 cs
->last_added_bo
= NULL
;
910 static void amdgpu_destroy_cs_context(struct amdgpu_cs_context
*cs
)
912 amdgpu_cs_context_cleanup(cs
);
913 FREE(cs
->real_buffers
);
914 FREE(cs
->slab_buffers
);
915 FREE(cs
->sparse_buffers
);
916 FREE(cs
->fence_dependencies
);
917 FREE(cs
->syncobj_to_signal
);
921 static struct radeon_cmdbuf
*
922 amdgpu_cs_create(struct radeon_winsys_ctx
*rwctx
,
923 enum ring_type ring_type
,
924 void (*flush
)(void *ctx
, unsigned flags
,
925 struct pipe_fence_handle
**fence
),
927 bool stop_exec_on_failure
)
929 struct amdgpu_ctx
*ctx
= (struct amdgpu_ctx
*)rwctx
;
930 struct amdgpu_cs
*cs
;
932 cs
= CALLOC_STRUCT(amdgpu_cs
);
937 util_queue_fence_init(&cs
->flush_completed
);
940 cs
->flush_cs
= flush
;
941 cs
->flush_data
= flush_ctx
;
942 cs
->ring_type
= ring_type
;
943 cs
->stop_exec_on_failure
= stop_exec_on_failure
;
945 struct amdgpu_cs_fence_info fence_info
;
946 fence_info
.handle
= cs
->ctx
->user_fence_bo
;
947 fence_info
.offset
= cs
->ring_type
;
948 amdgpu_cs_chunk_fence_info_to_data(&fence_info
, (void*)&cs
->fence_chunk
);
950 cs
->main
.ib_type
= IB_MAIN
;
952 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc1
, ring_type
)) {
957 if (!amdgpu_init_cs_context(ctx
->ws
, &cs
->csc2
, ring_type
)) {
958 amdgpu_destroy_cs_context(&cs
->csc1
);
963 /* Set the first submission context as current. */
967 if (!amdgpu_get_new_ib(&ctx
->ws
->base
, cs
, IB_MAIN
)) {
968 amdgpu_destroy_cs_context(&cs
->csc2
);
969 amdgpu_destroy_cs_context(&cs
->csc1
);
974 p_atomic_inc(&ctx
->ws
->num_cs
);
975 return &cs
->main
.base
;
978 static bool amdgpu_cs_validate(struct radeon_cmdbuf
*rcs
)
983 static bool amdgpu_cs_check_space(struct radeon_cmdbuf
*rcs
, unsigned dw
)
985 struct amdgpu_ib
*ib
= amdgpu_ib(rcs
);
986 struct amdgpu_cs
*cs
= amdgpu_cs_from_ib(ib
);
987 unsigned requested_size
= rcs
->prev_dw
+ rcs
->current
.cdw
+ dw
;
989 uint32_t *new_ptr_ib_size
;
991 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
993 if (requested_size
> amdgpu_ib_max_submit_dwords(ib
->ib_type
))
996 ib
->max_ib_size
= MAX2(ib
->max_ib_size
, requested_size
);
998 if (rcs
->current
.max_dw
- rcs
->current
.cdw
>= dw
)
1001 if (!amdgpu_cs_has_chaining(cs
))
1004 /* Allocate a new chunk */
1005 if (rcs
->num_prev
>= rcs
->max_prev
) {
1006 unsigned new_max_prev
= MAX2(1, 2 * rcs
->max_prev
);
1007 struct radeon_cmdbuf_chunk
*new_prev
;
1009 new_prev
= REALLOC(rcs
->prev
,
1010 sizeof(*new_prev
) * rcs
->max_prev
,
1011 sizeof(*new_prev
) * new_max_prev
);
1015 rcs
->prev
= new_prev
;
1016 rcs
->max_prev
= new_max_prev
;
1019 if (!amdgpu_ib_new_buffer(cs
->ctx
->ws
, ib
, cs
->ring_type
))
1022 assert(ib
->used_ib_space
== 0);
1023 va
= amdgpu_winsys_bo(ib
->big_ib_buffer
)->va
;
1025 /* This space was originally reserved. */
1026 rcs
->current
.max_dw
+= 4;
1027 assert(ib
->used_ib_space
+ 4 * rcs
->current
.max_dw
<= ib
->big_ib_buffer
->size
);
1029 /* Pad with NOPs and add INDIRECT_BUFFER packet */
1030 while ((rcs
->current
.cdw
& 7) != 4)
1031 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1033 radeon_emit(rcs
, PKT3(ib
->ib_type
== IB_MAIN
? PKT3_INDIRECT_BUFFER_CIK
1034 : PKT3_INDIRECT_BUFFER_CONST
, 2, 0));
1035 radeon_emit(rcs
, va
);
1036 radeon_emit(rcs
, va
>> 32);
1037 new_ptr_ib_size
= &rcs
->current
.buf
[rcs
->current
.cdw
++];
1039 assert((rcs
->current
.cdw
& 7) == 0);
1040 assert(rcs
->current
.cdw
<= rcs
->current
.max_dw
);
1042 amdgpu_set_ib_size(ib
);
1043 ib
->ptr_ib_size
= new_ptr_ib_size
;
1044 ib
->ptr_ib_size_inside_ib
= true;
1046 /* Hook up the new chunk */
1047 rcs
->prev
[rcs
->num_prev
].buf
= rcs
->current
.buf
;
1048 rcs
->prev
[rcs
->num_prev
].cdw
= rcs
->current
.cdw
;
1049 rcs
->prev
[rcs
->num_prev
].max_dw
= rcs
->current
.cdw
; /* no modifications */
1052 ib
->base
.prev_dw
+= ib
->base
.current
.cdw
;
1053 ib
->base
.current
.cdw
= 0;
1055 ib
->base
.current
.buf
= (uint32_t*)(ib
->ib_mapped
+ ib
->used_ib_space
);
1056 ib
->base
.current
.max_dw
= ib
->big_ib_buffer
->size
/ 4 - amdgpu_cs_epilog_dws(cs
->ring_type
);
1058 amdgpu_cs_add_buffer(&cs
->main
.base
, ib
->big_ib_buffer
,
1059 RADEON_USAGE_READ
, 0, RADEON_PRIO_IB1
);
1064 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf
*rcs
,
1065 struct radeon_bo_list_item
*list
)
1067 struct amdgpu_cs_context
*cs
= amdgpu_cs(rcs
)->csc
;
1071 for (i
= 0; i
< cs
->num_real_buffers
; i
++) {
1072 list
[i
].bo_size
= cs
->real_buffers
[i
].bo
->base
.size
;
1073 list
[i
].vm_address
= cs
->real_buffers
[i
].bo
->va
;
1074 list
[i
].priority_usage
= cs
->real_buffers
[i
].u
.real
.priority_usage
;
1077 return cs
->num_real_buffers
;
1080 static unsigned add_fence_dependency_entry(struct amdgpu_cs_context
*cs
)
1082 unsigned idx
= cs
->num_fence_dependencies
++;
1084 if (idx
>= cs
->max_fence_dependencies
) {
1086 const unsigned increment
= 8;
1088 cs
->max_fence_dependencies
= idx
+ increment
;
1089 size
= cs
->max_fence_dependencies
* sizeof(cs
->fence_dependencies
[0]);
1090 cs
->fence_dependencies
= realloc(cs
->fence_dependencies
, size
);
1091 /* Clear the newly-allocated elements. */
1092 memset(cs
->fence_dependencies
+ idx
, 0,
1093 increment
* sizeof(cs
->fence_dependencies
[0]));
1098 static bool is_noop_fence_dependency(struct amdgpu_cs
*acs
,
1099 struct amdgpu_fence
*fence
)
1101 struct amdgpu_cs_context
*cs
= acs
->csc
;
1103 if (!amdgpu_fence_is_syncobj(fence
) &&
1104 fence
->ctx
== acs
->ctx
&&
1105 fence
->fence
.ip_type
== cs
->ib
[IB_MAIN
].ip_type
&&
1106 fence
->fence
.ip_instance
== cs
->ib
[IB_MAIN
].ip_instance
&&
1107 fence
->fence
.ring
== cs
->ib
[IB_MAIN
].ring
)
1110 return amdgpu_fence_wait((void *)fence
, 0, false);
1113 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf
*rws
,
1114 struct pipe_fence_handle
*pfence
)
1116 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1117 struct amdgpu_cs_context
*cs
= acs
->csc
;
1118 struct amdgpu_fence
*fence
= (struct amdgpu_fence
*)pfence
;
1120 util_queue_fence_wait(&fence
->submitted
);
1122 if (is_noop_fence_dependency(acs
, fence
))
1125 unsigned idx
= add_fence_dependency_entry(cs
);
1126 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1127 (struct pipe_fence_handle
*)fence
);
1130 static void amdgpu_add_bo_fence_dependencies(struct amdgpu_cs
*acs
,
1131 struct amdgpu_cs_buffer
*buffer
)
1133 struct amdgpu_cs_context
*cs
= acs
->csc
;
1134 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1135 unsigned new_num_fences
= 0;
1137 for (unsigned j
= 0; j
< bo
->num_fences
; ++j
) {
1138 struct amdgpu_fence
*bo_fence
= (void *)bo
->fences
[j
];
1140 if (is_noop_fence_dependency(acs
, bo_fence
))
1143 amdgpu_fence_reference(&bo
->fences
[new_num_fences
], bo
->fences
[j
]);
1146 if (!(buffer
->usage
& RADEON_USAGE_SYNCHRONIZED
))
1149 unsigned idx
= add_fence_dependency_entry(cs
);
1150 amdgpu_fence_reference(&cs
->fence_dependencies
[idx
],
1151 (struct pipe_fence_handle
*)bo_fence
);
1154 for (unsigned j
= new_num_fences
; j
< bo
->num_fences
; ++j
)
1155 amdgpu_fence_reference(&bo
->fences
[j
], NULL
);
1157 bo
->num_fences
= new_num_fences
;
1160 /* Add the given list of fences to the buffer's fence list.
1162 * Must be called with the winsys bo_fence_lock held.
1164 void amdgpu_add_fences(struct amdgpu_winsys_bo
*bo
,
1165 unsigned num_fences
,
1166 struct pipe_fence_handle
**fences
)
1168 if (bo
->num_fences
+ num_fences
> bo
->max_fences
) {
1169 unsigned new_max_fences
= MAX2(bo
->num_fences
+ num_fences
, bo
->max_fences
* 2);
1170 struct pipe_fence_handle
**new_fences
=
1172 bo
->num_fences
* sizeof(*new_fences
),
1173 new_max_fences
* sizeof(*new_fences
));
1174 if (likely(new_fences
)) {
1175 bo
->fences
= new_fences
;
1176 bo
->max_fences
= new_max_fences
;
1180 fprintf(stderr
, "amdgpu_add_fences: allocation failure, dropping fence(s)\n");
1181 if (!bo
->num_fences
)
1184 bo
->num_fences
--; /* prefer to keep the most recent fence if possible */
1185 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], NULL
);
1187 drop
= bo
->num_fences
+ num_fences
- bo
->max_fences
;
1193 for (unsigned i
= 0; i
< num_fences
; ++i
) {
1194 bo
->fences
[bo
->num_fences
] = NULL
;
1195 amdgpu_fence_reference(&bo
->fences
[bo
->num_fences
], fences
[i
]);
1200 static void amdgpu_add_fence_dependencies_bo_list(struct amdgpu_cs
*acs
,
1201 struct pipe_fence_handle
*fence
,
1202 unsigned num_buffers
,
1203 struct amdgpu_cs_buffer
*buffers
)
1205 for (unsigned i
= 0; i
< num_buffers
; i
++) {
1206 struct amdgpu_cs_buffer
*buffer
= &buffers
[i
];
1207 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1209 amdgpu_add_bo_fence_dependencies(acs
, buffer
);
1210 p_atomic_inc(&bo
->num_active_ioctls
);
1211 amdgpu_add_fences(bo
, 1, &fence
);
1215 /* Since the kernel driver doesn't synchronize execution between different
1216 * rings automatically, we have to add fence dependencies manually.
1218 static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs
*acs
)
1220 struct amdgpu_cs_context
*cs
= acs
->csc
;
1222 cs
->num_fence_dependencies
= 0;
1224 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_real_buffers
, cs
->real_buffers
);
1225 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_slab_buffers
, cs
->slab_buffers
);
1226 amdgpu_add_fence_dependencies_bo_list(acs
, cs
->fence
, cs
->num_sparse_buffers
, cs
->sparse_buffers
);
1229 static unsigned add_syncobj_to_signal_entry(struct amdgpu_cs_context
*cs
)
1231 unsigned idx
= cs
->num_syncobj_to_signal
++;
1233 if (idx
>= cs
->max_syncobj_to_signal
) {
1235 const unsigned increment
= 8;
1237 cs
->max_syncobj_to_signal
= idx
+ increment
;
1238 size
= cs
->max_syncobj_to_signal
* sizeof(cs
->syncobj_to_signal
[0]);
1239 cs
->syncobj_to_signal
= realloc(cs
->syncobj_to_signal
, size
);
1240 /* Clear the newly-allocated elements. */
1241 memset(cs
->syncobj_to_signal
+ idx
, 0,
1242 increment
* sizeof(cs
->syncobj_to_signal
[0]));
1247 static void amdgpu_cs_add_syncobj_signal(struct radeon_cmdbuf
*rws
,
1248 struct pipe_fence_handle
*fence
)
1250 struct amdgpu_cs
*acs
= amdgpu_cs(rws
);
1251 struct amdgpu_cs_context
*cs
= acs
->csc
;
1253 assert(amdgpu_fence_is_syncobj((struct amdgpu_fence
*)fence
));
1255 unsigned idx
= add_syncobj_to_signal_entry(cs
);
1256 amdgpu_fence_reference(&cs
->syncobj_to_signal
[idx
], fence
);
1259 /* Add backing of sparse buffers to the buffer list.
1261 * This is done late, during submission, to keep the buffer list short before
1262 * submit, and to avoid managing fences for the backing buffers.
1264 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context
*cs
)
1266 for (unsigned i
= 0; i
< cs
->num_sparse_buffers
; ++i
) {
1267 struct amdgpu_cs_buffer
*buffer
= &cs
->sparse_buffers
[i
];
1268 struct amdgpu_winsys_bo
*bo
= buffer
->bo
;
1270 simple_mtx_lock(&bo
->u
.sparse
.commit_lock
);
1272 list_for_each_entry(struct amdgpu_sparse_backing
, backing
, &bo
->u
.sparse
.backing
, list
) {
1273 /* We can directly add the buffer here, because we know that each
1274 * backing buffer occurs only once.
1276 int idx
= amdgpu_do_add_real_buffer(cs
, backing
->bo
);
1278 fprintf(stderr
, "%s: failed to add buffer\n", __FUNCTION__
);
1279 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1283 cs
->real_buffers
[idx
].usage
= buffer
->usage
& ~RADEON_USAGE_SYNCHRONIZED
;
1284 cs
->real_buffers
[idx
].u
.real
.priority_usage
= buffer
->u
.real
.priority_usage
;
1285 p_atomic_inc(&backing
->bo
->num_active_ioctls
);
1288 simple_mtx_unlock(&bo
->u
.sparse
.commit_lock
);
1294 void amdgpu_cs_submit_ib(void *job
, int thread_index
)
1296 struct amdgpu_cs
*acs
= (struct amdgpu_cs
*)job
;
1297 struct amdgpu_winsys
*ws
= acs
->ctx
->ws
;
1298 struct amdgpu_cs_context
*cs
= acs
->cst
;
1300 amdgpu_bo_list_handle bo_list
= NULL
;
1301 uint64_t seq_no
= 0;
1302 bool has_user_fence
= amdgpu_cs_has_user_fence(cs
);
1303 bool use_bo_list_create
= ws
->info
.drm_minor
< 27;
1304 struct drm_amdgpu_bo_list_in bo_list_in
;
1306 /* Prepare the buffer list. */
1307 if (ws
->debug_all_bos
) {
1308 /* The buffer list contains all buffers. This is a slow path that
1309 * ensures that no buffer is missing in the BO list.
1311 struct amdgpu_winsys_bo
*bo
;
1312 amdgpu_bo_handle
*handles
;
1315 simple_mtx_lock(&ws
->global_bo_list_lock
);
1316 handles
= alloca(sizeof(handles
[0]) * ws
->num_buffers
);
1318 LIST_FOR_EACH_ENTRY(bo
, &ws
->global_bo_list
, u
.real
.global_list_item
) {
1319 assert(num
< ws
->num_buffers
);
1320 handles
[num
++] = bo
->bo
;
1323 r
= amdgpu_bo_list_create(ws
->dev
, ws
->num_buffers
,
1324 handles
, NULL
, &bo_list
);
1325 simple_mtx_unlock(&ws
->global_bo_list_lock
);
1327 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1330 } else if (!use_bo_list_create
) {
1331 /* Standard path passing the buffer list via the CS ioctl. */
1332 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1333 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1338 struct drm_amdgpu_bo_list_entry
*list
=
1339 alloca(cs
->num_real_buffers
* sizeof(struct drm_amdgpu_bo_list_entry
));
1341 unsigned num_handles
= 0;
1342 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1343 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1345 if (buffer
->bo
->is_local
)
1348 assert(buffer
->u
.real
.priority_usage
!= 0);
1350 list
[num_handles
].bo_handle
= buffer
->bo
->u
.real
.kms_handle
;
1351 list
[num_handles
].bo_priority
= (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1355 bo_list_in
.operation
= ~0;
1356 bo_list_in
.list_handle
= ~0;
1357 bo_list_in
.bo_number
= num_handles
;
1358 bo_list_in
.bo_info_size
= sizeof(struct drm_amdgpu_bo_list_entry
);
1359 bo_list_in
.bo_info_ptr
= (uint64_t)(uintptr_t)list
;
1361 /* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
1362 unsigned num_handles
;
1364 if (!amdgpu_add_sparse_backing_buffers(cs
)) {
1365 fprintf(stderr
, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
1370 amdgpu_bo_handle
*handles
= alloca(sizeof(*handles
) * cs
->num_real_buffers
);
1371 uint8_t *flags
= alloca(sizeof(*flags
) * cs
->num_real_buffers
);
1374 for (i
= 0; i
< cs
->num_real_buffers
; ++i
) {
1375 struct amdgpu_cs_buffer
*buffer
= &cs
->real_buffers
[i
];
1377 if (buffer
->bo
->is_local
)
1380 assert(buffer
->u
.real
.priority_usage
!= 0);
1382 handles
[num_handles
] = buffer
->bo
->bo
;
1383 flags
[num_handles
] = (util_last_bit(buffer
->u
.real
.priority_usage
) - 1) / 2;
1388 r
= amdgpu_bo_list_create(ws
->dev
, num_handles
,
1389 handles
, flags
, &bo_list
);
1391 fprintf(stderr
, "amdgpu: buffer list creation failed (%d)\n", r
);
1397 if (acs
->ring_type
== RING_GFX
)
1398 ws
->gfx_bo_list_counter
+= cs
->num_real_buffers
;
1400 if (acs
->stop_exec_on_failure
&& acs
->ctx
->num_rejected_cs
) {
1403 struct drm_amdgpu_cs_chunk chunks
[6];
1404 unsigned num_chunks
= 0;
1406 /* Convert from dwords to bytes. */
1407 cs
->ib
[IB_MAIN
].ib_bytes
*= 4;
1410 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_IB
;
1411 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_ib
) / 4;
1412 chunks
[num_chunks
].chunk_data
= (uintptr_t)&cs
->ib
[IB_MAIN
];
1416 if (has_user_fence
) {
1417 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_FENCE
;
1418 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_cs_chunk_fence
) / 4;
1419 chunks
[num_chunks
].chunk_data
= (uintptr_t)&acs
->fence_chunk
;
1424 unsigned num_dependencies
= cs
->num_fence_dependencies
;
1425 unsigned num_syncobj_dependencies
= 0;
1427 if (num_dependencies
) {
1428 struct drm_amdgpu_cs_chunk_dep
*dep_chunk
=
1429 alloca(num_dependencies
* sizeof(*dep_chunk
));
1432 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1433 struct amdgpu_fence
*fence
=
1434 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1436 if (amdgpu_fence_is_syncobj(fence
)) {
1437 num_syncobj_dependencies
++;
1441 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1442 amdgpu_cs_chunk_fence_to_dep(&fence
->fence
, &dep_chunk
[num
++]);
1445 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_DEPENDENCIES
;
1446 chunks
[num_chunks
].length_dw
= sizeof(dep_chunk
[0]) / 4 * num
;
1447 chunks
[num_chunks
].chunk_data
= (uintptr_t)dep_chunk
;
1451 /* Syncobj dependencies. */
1452 if (num_syncobj_dependencies
) {
1453 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1454 alloca(num_syncobj_dependencies
* sizeof(sem_chunk
[0]));
1457 for (unsigned i
= 0; i
< num_dependencies
; i
++) {
1458 struct amdgpu_fence
*fence
=
1459 (struct amdgpu_fence
*)cs
->fence_dependencies
[i
];
1461 if (!amdgpu_fence_is_syncobj(fence
))
1464 assert(util_queue_fence_is_signalled(&fence
->submitted
));
1465 sem_chunk
[num
++].handle
= fence
->syncobj
;
1468 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_IN
;
1469 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4 * num
;
1470 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1474 /* Syncobj sygnals. */
1475 if (cs
->num_syncobj_to_signal
) {
1476 struct drm_amdgpu_cs_chunk_sem
*sem_chunk
=
1477 alloca(cs
->num_syncobj_to_signal
* sizeof(sem_chunk
[0]));
1479 for (unsigned i
= 0; i
< cs
->num_syncobj_to_signal
; i
++) {
1480 struct amdgpu_fence
*fence
=
1481 (struct amdgpu_fence
*)cs
->syncobj_to_signal
[i
];
1483 assert(amdgpu_fence_is_syncobj(fence
));
1484 sem_chunk
[i
].handle
= fence
->syncobj
;
1487 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_SYNCOBJ_OUT
;
1488 chunks
[num_chunks
].length_dw
= sizeof(sem_chunk
[0]) / 4
1489 * cs
->num_syncobj_to_signal
;
1490 chunks
[num_chunks
].chunk_data
= (uintptr_t)sem_chunk
;
1495 if (!use_bo_list_create
) {
1496 chunks
[num_chunks
].chunk_id
= AMDGPU_CHUNK_ID_BO_HANDLES
;
1497 chunks
[num_chunks
].length_dw
= sizeof(struct drm_amdgpu_bo_list_in
) / 4;
1498 chunks
[num_chunks
].chunk_data
= (uintptr_t)&bo_list_in
;
1502 assert(num_chunks
<= ARRAY_SIZE(chunks
));
1504 r
= amdgpu_cs_submit_raw(ws
->dev
, acs
->ctx
->ctx
, bo_list
,
1505 num_chunks
, chunks
, &seq_no
);
1510 fprintf(stderr
, "amdgpu: Not enough memory for command submission.\n");
1511 else if (r
== -ECANCELED
)
1512 fprintf(stderr
, "amdgpu: The CS has been cancelled because the context is lost.\n");
1514 fprintf(stderr
, "amdgpu: The CS has been rejected, "
1515 "see dmesg for more information (%i).\n", r
);
1517 acs
->ctx
->num_rejected_cs
++;
1518 ws
->num_total_rejected_cs
++;
1521 uint64_t *user_fence
= NULL
;
1524 user_fence
= acs
->ctx
->user_fence_cpu_address_base
+ acs
->ring_type
;
1525 amdgpu_fence_submitted(cs
->fence
, seq_no
, user_fence
);
1530 amdgpu_bo_list_destroy(bo_list
);
1533 /* If there was an error, signal the fence, because it won't be signalled
1534 * by the hardware. */
1536 amdgpu_fence_signalled(cs
->fence
);
1540 for (i
= 0; i
< cs
->num_real_buffers
; i
++)
1541 p_atomic_dec(&cs
->real_buffers
[i
].bo
->num_active_ioctls
);
1542 for (i
= 0; i
< cs
->num_slab_buffers
; i
++)
1543 p_atomic_dec(&cs
->slab_buffers
[i
].bo
->num_active_ioctls
);
1544 for (i
= 0; i
< cs
->num_sparse_buffers
; i
++)
1545 p_atomic_dec(&cs
->sparse_buffers
[i
].bo
->num_active_ioctls
);
1547 amdgpu_cs_context_cleanup(cs
);
1550 /* Make sure the previous submission is completed. */
1551 void amdgpu_cs_sync_flush(struct radeon_cmdbuf
*rcs
)
1553 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1555 /* Wait for any pending ioctl of this CS to complete. */
1556 util_queue_fence_wait(&cs
->flush_completed
);
1559 static int amdgpu_cs_flush(struct radeon_cmdbuf
*rcs
,
1561 struct pipe_fence_handle
**fence
)
1563 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1564 struct amdgpu_winsys
*ws
= cs
->ctx
->ws
;
1567 rcs
->current
.max_dw
+= amdgpu_cs_epilog_dws(cs
->ring_type
);
1569 switch (cs
->ring_type
) {
1571 /* pad DMA ring to 8 DWs */
1572 if (ws
->info
.chip_class
<= SI
) {
1573 while (rcs
->current
.cdw
& 7)
1574 radeon_emit(rcs
, 0xf0000000); /* NOP packet */
1576 while (rcs
->current
.cdw
& 7)
1577 radeon_emit(rcs
, 0x00000000); /* NOP packet */
1582 /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
1583 if (ws
->info
.gfx_ib_pad_with_type2
) {
1584 while (rcs
->current
.cdw
& 7)
1585 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1587 while (rcs
->current
.cdw
& 7)
1588 radeon_emit(rcs
, 0xffff1000); /* type3 nop packet */
1590 if (cs
->ring_type
== RING_GFX
)
1591 ws
->gfx_ib_size_counter
+= (rcs
->prev_dw
+ rcs
->current
.cdw
) * 4;
1595 while (rcs
->current
.cdw
& 15)
1596 radeon_emit(rcs
, 0x80000000); /* type2 nop packet */
1599 if (rcs
->current
.cdw
% 2)
1601 while (rcs
->current
.cdw
& 15) {
1602 radeon_emit(rcs
, 0x60000000); /* nop packet */
1603 radeon_emit(rcs
, 0x00000000);
1607 while (rcs
->current
.cdw
& 15)
1608 radeon_emit(rcs
, 0x81ff); /* nop packet */
1614 if (rcs
->current
.cdw
> rcs
->current
.max_dw
) {
1615 fprintf(stderr
, "amdgpu: command stream overflowed\n");
1618 /* If the CS is not empty or overflowed.... */
1619 if (likely(radeon_emitted(&cs
->main
.base
, 0) &&
1620 cs
->main
.base
.current
.cdw
<= cs
->main
.base
.current
.max_dw
&&
1621 !debug_get_option_noop())) {
1622 struct amdgpu_cs_context
*cur
= cs
->csc
;
1625 amdgpu_ib_finalize(ws
, &cs
->main
);
1627 /* Create a fence. */
1628 amdgpu_fence_reference(&cur
->fence
, NULL
);
1629 if (cs
->next_fence
) {
1630 /* just move the reference */
1631 cur
->fence
= cs
->next_fence
;
1632 cs
->next_fence
= NULL
;
1634 cur
->fence
= amdgpu_fence_create(cs
->ctx
,
1635 cur
->ib
[IB_MAIN
].ip_type
,
1636 cur
->ib
[IB_MAIN
].ip_instance
,
1637 cur
->ib
[IB_MAIN
].ring
);
1640 amdgpu_fence_reference(fence
, cur
->fence
);
1642 amdgpu_cs_sync_flush(rcs
);
1646 * This fence must be held until the submission is queued to ensure
1647 * that the order of fence dependency updates matches the order of
1650 simple_mtx_lock(&ws
->bo_fence_lock
);
1651 amdgpu_add_fence_dependencies_bo_lists(cs
);
1653 /* Swap command streams. "cst" is going to be submitted. */
1658 util_queue_add_job(&ws
->cs_queue
, cs
, &cs
->flush_completed
,
1659 amdgpu_cs_submit_ib
, NULL
);
1660 /* The submission has been queued, unlock the fence now. */
1661 simple_mtx_unlock(&ws
->bo_fence_lock
);
1663 if (!(flags
& PIPE_FLUSH_ASYNC
)) {
1664 amdgpu_cs_sync_flush(rcs
);
1665 error_code
= cur
->error_code
;
1668 amdgpu_cs_context_cleanup(cs
->csc
);
1671 amdgpu_get_new_ib(&ws
->base
, cs
, IB_MAIN
);
1673 cs
->main
.base
.used_gart
= 0;
1674 cs
->main
.base
.used_vram
= 0;
1676 if (cs
->ring_type
== RING_GFX
)
1678 else if (cs
->ring_type
== RING_DMA
)
1684 static void amdgpu_cs_destroy(struct radeon_cmdbuf
*rcs
)
1686 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1688 amdgpu_cs_sync_flush(rcs
);
1689 util_queue_fence_destroy(&cs
->flush_completed
);
1690 p_atomic_dec(&cs
->ctx
->ws
->num_cs
);
1691 pb_reference(&cs
->main
.big_ib_buffer
, NULL
);
1692 FREE(cs
->main
.base
.prev
);
1693 amdgpu_destroy_cs_context(&cs
->csc1
);
1694 amdgpu_destroy_cs_context(&cs
->csc2
);
1695 amdgpu_fence_reference(&cs
->next_fence
, NULL
);
1699 static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf
*rcs
,
1700 struct pb_buffer
*_buf
,
1701 enum radeon_bo_usage usage
)
1703 struct amdgpu_cs
*cs
= amdgpu_cs(rcs
);
1704 struct amdgpu_winsys_bo
*bo
= (struct amdgpu_winsys_bo
*)_buf
;
1706 return amdgpu_bo_is_referenced_by_cs_with_usage(cs
, bo
, usage
);
1709 void amdgpu_cs_init_functions(struct amdgpu_winsys
*ws
)
1711 ws
->base
.ctx_create
= amdgpu_ctx_create
;
1712 ws
->base
.ctx_destroy
= amdgpu_ctx_destroy
;
1713 ws
->base
.ctx_query_reset_status
= amdgpu_ctx_query_reset_status
;
1714 ws
->base
.cs_create
= amdgpu_cs_create
;
1715 ws
->base
.cs_destroy
= amdgpu_cs_destroy
;
1716 ws
->base
.cs_add_buffer
= amdgpu_cs_add_buffer
;
1717 ws
->base
.cs_validate
= amdgpu_cs_validate
;
1718 ws
->base
.cs_check_space
= amdgpu_cs_check_space
;
1719 ws
->base
.cs_get_buffer_list
= amdgpu_cs_get_buffer_list
;
1720 ws
->base
.cs_flush
= amdgpu_cs_flush
;
1721 ws
->base
.cs_get_next_fence
= amdgpu_cs_get_next_fence
;
1722 ws
->base
.cs_is_buffer_referenced
= amdgpu_bo_is_referenced
;
1723 ws
->base
.cs_sync_flush
= amdgpu_cs_sync_flush
;
1724 ws
->base
.cs_add_fence_dependency
= amdgpu_cs_add_fence_dependency
;
1725 ws
->base
.cs_add_syncobj_signal
= amdgpu_cs_add_syncobj_signal
;
1726 ws
->base
.fence_wait
= amdgpu_fence_wait_rel_timeout
;
1727 ws
->base
.fence_reference
= amdgpu_fence_reference
;
1728 ws
->base
.fence_import_syncobj
= amdgpu_fence_import_syncobj
;
1729 ws
->base
.fence_import_sync_file
= amdgpu_fence_import_sync_file
;
1730 ws
->base
.fence_export_sync_file
= amdgpu_fence_export_sync_file
;
1731 ws
->base
.export_signalled_sync_file
= amdgpu_export_signalled_sync_file
;