src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright © 2009 Joakim Sindholt <opensource@zhasha.com>
   4  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   5  * Copyright © 2015 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining
   9  * a copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  18  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  19  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  20  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  * The above copyright notice and this permission notice (including the
  26  * next paragraph) shall be included in all copies or substantial portions
  27  * of the Software.
  28  */
  29
  30 #include "amdgpu_cs.h"
  31 #include "amdgpu_public.h"
  32
  33 #include "util/u_hash_table.h"
  34 #include "util/hash_table.h"
  35 #include <amdgpu_drm.h>
  36 #include <xf86drm.h>
  37 #include <stdio.h>
  38 #include <sys/stat.h>
  39 #include "amd/common/sid.h"
  40 #include "amd/common/gfx9d.h"
  41
  42 #ifndef AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
  43 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
  44 #endif
  45
  46 static struct util_hash_table *dev_tab = NULL;
  47 static simple_mtx_t dev_tab_mutex = _SIMPLE_MTX_INITIALIZER_NP;
  48
  49 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
  50
  51 /* Helper function to do the ioctls needed for setup and init. */
  52 static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
  53 {
  54    if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
  55       goto fail;
  56
  57    ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
  58    if (!ws->addrlib) {
  59       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
  60       goto fail;
  61    }
  62
  63    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
  64    ws->debug_all_bos = debug_get_option_all_bos();
  65    ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL;
  66    ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL;
  67
  68    return true;
  69
  70 fail:
  71    amdgpu_device_deinitialize(ws->dev);
  72    ws->dev = NULL;
  73    return false;
  74 }
  75
  76 static void do_winsys_deinit(struct amdgpu_winsys *ws)
  77 {
  78    AddrDestroy(ws->addrlib);
  79    amdgpu_device_deinitialize(ws->dev);
  80 }
  81
  82 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
  83 {
  84    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
  85
  86    if (ws->reserve_vmid)
  87       amdgpu_vm_unreserve_vmid(ws->dev, 0);
  88
  89    if (util_queue_is_initialized(&ws->cs_queue))
  90       util_queue_destroy(&ws->cs_queue);
  91
  92    simple_mtx_destroy(&ws->bo_fence_lock);
  93    pb_slabs_deinit(&ws->bo_slabs);
  94    pb_cache_deinit(&ws->bo_cache);
  95    util_hash_table_destroy(ws->bo_export_table);
  96    simple_mtx_destroy(&ws->global_bo_list_lock);
  97    simple_mtx_destroy(&ws->bo_export_table_lock);
  98    do_winsys_deinit(ws);
  99    FREE(rws);
 100 }
 101
 102 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
 103                                      struct radeon_info *info)
 104 {
 105    *info = ((struct amdgpu_winsys *)rws)->info;
 106 }
 107
 108 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
 109                                       enum radeon_feature_id fid,
 110                                       bool enable)
 111 {
 112    return false;
 113 }
 114
 115 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
 116                                    enum radeon_value_id value)
 117 {
 118    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 119    struct amdgpu_heap_info heap;
 120    uint64_t retval = 0;
 121
 122    switch (value) {
 123    case RADEON_REQUESTED_VRAM_MEMORY:
 124       return ws->allocated_vram;
 125    case RADEON_REQUESTED_GTT_MEMORY:
 126       return ws->allocated_gtt;
 127    case RADEON_MAPPED_VRAM:
 128       return ws->mapped_vram;
 129    case RADEON_MAPPED_GTT:
 130       return ws->mapped_gtt;
 131    case RADEON_BUFFER_WAIT_TIME_NS:
 132       return ws->buffer_wait_time;
 133    case RADEON_NUM_MAPPED_BUFFERS:
 134       return ws->num_mapped_buffers;
 135    case RADEON_TIMESTAMP:
 136       amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
 137       return retval;
 138    case RADEON_NUM_GFX_IBS:
 139       return ws->num_gfx_IBs;
 140    case RADEON_NUM_SDMA_IBS:
 141       return ws->num_sdma_IBs;
 142    case RADEON_GFX_BO_LIST_COUNTER:
 143       return ws->gfx_bo_list_counter;
 144    case RADEON_GFX_IB_SIZE_COUNTER:
 145       return ws->gfx_ib_size_counter;
 146    case RADEON_NUM_BYTES_MOVED:
 147       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
 148       return retval;
 149    case RADEON_NUM_EVICTIONS:
 150       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
 151       return retval;
 152    case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 153       amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
 154       return retval;
 155    case RADEON_VRAM_USAGE:
 156       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
 157       return heap.heap_usage;
 158    case RADEON_VRAM_VIS_USAGE:
 159       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
 160                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
 161       return heap.heap_usage;
 162    case RADEON_GTT_USAGE:
 163       amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
 164       return heap.heap_usage;
 165    case RADEON_GPU_TEMPERATURE:
 166       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
 167       return retval;
 168    case RADEON_CURRENT_SCLK:
 169       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
 170       return retval;
 171    case RADEON_CURRENT_MCLK:
 172       amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
 173       return retval;
 174    case RADEON_GPU_RESET_COUNTER:
 175       assert(0);
 176       return 0;
 177    case RADEON_CS_THREAD_TIME:
 178       return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 179    }
 180    return 0;
 181 }
 182
 183 static bool amdgpu_read_registers(struct radeon_winsys *rws,
 184                                   unsigned reg_offset,
 185                                   unsigned num_registers, uint32_t *out)
 186 {
 187    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 188
 189    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
 190                                    0xffffffff, 0, out) == 0;
 191 }
 192
 193 static unsigned hash_pointer(void *key)
 194 {
 195    return _mesa_hash_pointer(key);
 196 }
 197
 198 static int compare_pointers(void *key1, void *key2)
 199 {
 200    return key1 != key2;
 201 }
 202
 203 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 204 {
 205    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
 206    bool destroy;
 207
 208    /* When the reference counter drops to zero, remove the device pointer
 209     * from the table.
 210     * This must happen while the mutex is locked, so that
 211     * amdgpu_winsys_create in another thread doesn't get the winsys
 212     * from the table when the counter drops to 0. */
 213    simple_mtx_lock(&dev_tab_mutex);
 214
 215    destroy = pipe_reference(&ws->reference, NULL);
 216    if (destroy && dev_tab) {
 217       util_hash_table_remove(dev_tab, ws->dev);
 218       if (util_hash_table_count(dev_tab) == 0) {
 219          util_hash_table_destroy(dev_tab);
 220          dev_tab = NULL;
 221       }
 222    }
 223
 224    simple_mtx_unlock(&dev_tab_mutex);
 225    return destroy;
 226 }
 227
 228 static const char* amdgpu_get_chip_name(struct radeon_winsys *ws)
 229 {
 230    amdgpu_device_handle dev = ((struct amdgpu_winsys *)ws)->dev;
 231    return amdgpu_get_marketing_name(dev);
 232 }
 233
 234
 235 PUBLIC struct radeon_winsys *
 236 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 237                      radeon_screen_create_t screen_create)
 238 {
 239    struct amdgpu_winsys *ws;
 240    drmVersionPtr version = drmGetVersion(fd);
 241    amdgpu_device_handle dev;
 242    uint32_t drm_major, drm_minor, r;
 243
 244    /* The DRM driver version of amdgpu is 3.x.x. */
 245    if (version->version_major != 3) {
 246       drmFreeVersion(version);
 247       return NULL;
 248    }
 249    drmFreeVersion(version);
 250
 251    /* Look up the winsys from the dev table. */
 252    simple_mtx_lock(&dev_tab_mutex);
 253    if (!dev_tab)
 254       dev_tab = util_hash_table_create(hash_pointer, compare_pointers);
 255
 256    /* Initialize the amdgpu device. This should always return the same pointer
 257     * for the same fd. */
 258    r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
 259    if (r) {
 260       simple_mtx_unlock(&dev_tab_mutex);
 261       fprintf(stderr, "amdgpu: amdgpu_device_initialize failed.\n");
 262       return NULL;
 263    }
 264
 265    /* Lookup a winsys if we have already created one for this device. */
 266    ws = util_hash_table_get(dev_tab, dev);
 267    if (ws) {
 268       pipe_reference(NULL, &ws->reference);
 269       simple_mtx_unlock(&dev_tab_mutex);
 270       return &ws->base;
 271    }
 272
 273    /* Create a new winsys. */
 274    ws = CALLOC_STRUCT(amdgpu_winsys);
 275    if (!ws)
 276       goto fail;
 277
 278    ws->dev = dev;
 279    ws->info.drm_major = drm_major;
 280    ws->info.drm_minor = drm_minor;
 281
 282    if (!do_winsys_init(ws, fd))
 283       goto fail_alloc;
 284
 285    /* Create managers. */
 286    pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 287                  500000, ws->check_vm ? 1.0f : 2.0f, 0,
 288                  (ws->info.vram_size + ws->info.gart_size) / 8,
 289                  amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
 290
 291    if (!pb_slabs_init(&ws->bo_slabs,
 292                       AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
 293                       RADEON_MAX_SLAB_HEAPS,
 294                       ws,
 295                       amdgpu_bo_can_reclaim_slab,
 296                       amdgpu_bo_slab_alloc,
 297                       amdgpu_bo_slab_free))
 298       goto fail_cache;
 299
 300    ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
 301
 302    /* init reference */
 303    pipe_reference_init(&ws->reference, 1);
 304
 305    /* Set functions. */
 306    ws->base.unref = amdgpu_winsys_unref;
 307    ws->base.destroy = amdgpu_winsys_destroy;
 308    ws->base.query_info = amdgpu_winsys_query_info;
 309    ws->base.cs_request_feature = amdgpu_cs_request_feature;
 310    ws->base.query_value = amdgpu_query_value;
 311    ws->base.read_registers = amdgpu_read_registers;
 312    ws->base.get_chip_name = amdgpu_get_chip_name;
 313
 314    amdgpu_bo_init_functions(ws);
 315    amdgpu_cs_init_functions(ws);
 316    amdgpu_surface_init_functions(ws);
 317
 318    LIST_INITHEAD(&ws->global_bo_list);
 319    ws->bo_export_table = util_hash_table_create(hash_pointer, compare_pointers);
 320
 321    (void) simple_mtx_init(&ws->global_bo_list_lock, mtx_plain);
 322    (void) simple_mtx_init(&ws->bo_fence_lock, mtx_plain);
 323    (void) simple_mtx_init(&ws->bo_export_table_lock, mtx_plain);
 324
 325    if (!util_queue_init(&ws->cs_queue, "cs", 8, 1,
 326                         UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
 327       amdgpu_winsys_destroy(&ws->base);
 328       simple_mtx_unlock(&dev_tab_mutex);
 329       return NULL;
 330    }
 331
 332    /* Create the screen at the end. The winsys must be initialized
 333     * completely.
 334     *
 335     * Alternatively, we could create the screen based on "ws->gen"
 336     * and link all drivers into one binary blob. */
 337    ws->base.screen = screen_create(&ws->base, config);
 338    if (!ws->base.screen) {
 339       amdgpu_winsys_destroy(&ws->base);
 340       simple_mtx_unlock(&dev_tab_mutex);
 341       return NULL;
 342    }
 343
 344    util_hash_table_set(dev_tab, dev, ws);
 345
 346    if (ws->reserve_vmid) {
 347            r = amdgpu_vm_reserve_vmid(dev, 0);
 348            if (r) {
 349                 fprintf(stderr, "amdgpu: amdgpu_vm_reserve_vmid failed. (%i)\n", r);
 350                 goto fail_cache;
 351            }
 352    }
 353
 354    /* We must unlock the mutex once the winsys is fully initialized, so that
 355     * other threads attempting to create the winsys from the same fd will
 356     * get a fully initialized winsys and not just half-way initialized. */
 357    simple_mtx_unlock(&dev_tab_mutex);
 358
 359    return &ws->base;
 360
 361 fail_cache:
 362    pb_cache_deinit(&ws->bo_cache);
 363    do_winsys_deinit(ws);
 364 fail_alloc:
 365    FREE(ws);
 366 fail:
 367    simple_mtx_unlock(&dev_tab_mutex);
 368    return NULL;
 369 }