src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #ifndef AMDGPU_WINSYS_H
  29 #define AMDGPU_WINSYS_H
  30
  31 #include "pipebuffer/pb_cache.h"
  32 #include "pipebuffer/pb_slab.h"
  33 #include "gallium/drivers/radeon/radeon_winsys.h"
  34 #include "addrlib/inc/addrinterface.h"
  35 #include "util/simple_mtx.h"
  36 #include "util/u_queue.h"
  37 #include <amdgpu.h>
  38
  39 struct amdgpu_cs;
  40
  41 #define NUM_SLAB_ALLOCATORS 3
  42
  43 struct amdgpu_winsys {
  44    struct radeon_winsys base;
  45    struct pipe_reference reference;
  46    struct pb_cache bo_cache;
  47
  48    /* Each slab buffer can only contain suballocations of equal sizes, so we
  49     * need to layer the allocators, so that we don't waste too much memory.
  50     */
  51    struct pb_slabs bo_slabs[NUM_SLAB_ALLOCATORS];
  52
  53    amdgpu_device_handle dev;
  54
  55    simple_mtx_t bo_fence_lock;
  56
  57    int num_cs; /* The number of command streams created. */
  58    unsigned num_total_rejected_cs;
  59    uint32_t surf_index_color;
  60    uint32_t surf_index_fmask;
  61    uint32_t next_bo_unique_id;
  62    uint64_t allocated_vram;
  63    uint64_t allocated_gtt;
  64    uint64_t mapped_vram;
  65    uint64_t mapped_gtt;
  66    uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
  67    uint64_t num_gfx_IBs;
  68    uint64_t num_sdma_IBs;
  69    uint64_t num_mapped_buffers;
  70    uint64_t gfx_bo_list_counter;
  71    uint64_t gfx_ib_size_counter;
  72
  73    struct radeon_info info;
  74
  75    /* multithreaded IB submission */
  76    struct util_queue cs_queue;
  77
  78    struct amdgpu_gpu_info amdinfo;
  79    ADDR_HANDLE addrlib;
  80
  81    bool check_vm;
  82    bool debug_all_bos;
  83    bool reserve_vmid;
  84    bool zero_all_vram_allocs;
  85
  86    /* List of all allocated buffers */
  87    simple_mtx_t global_bo_list_lock;
  88    struct list_head global_bo_list;
  89    unsigned num_buffers;
  90
  91    /* For returning the same amdgpu_winsys_bo instance for exported
  92     * and re-imported buffers. */
  93    struct util_hash_table *bo_export_table;
  94    simple_mtx_t bo_export_table_lock;
  95 };
  96
  97 static inline struct amdgpu_winsys *
  98 amdgpu_winsys(struct radeon_winsys *base)
  99 {
 100    return (struct amdgpu_winsys*)base;
 101 }
 102
 103 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
 104
 105 #endif