Merge branch 'mesa_7_7_branch'
[mesa.git] / src / gallium / winsys / drm / radeon / core / radeon_buffer.h
1 /*
2 * Copyright © 2008 Jérôme Glisse
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 * Authors:
28 * Jérôme Glisse <glisse@freedesktop.org>
29 */
30 #ifndef RADEON_BUFFER_H
31 #define RADEON_BUFFER_H
32
33 #include <stdio.h>
34
35 #include "pipe/internal/p_winsys_screen.h"
36 #include "pipe/p_defines.h"
37 #include "pipe/p_inlines.h"
38
39 #include "pipebuffer/pb_buffer.h"
40
41 #include "util/u_memory.h"
42
43 #include "radeon_bo.h"
44 #include "radeon_cs.h"
45
46 #include "radeon_drm.h"
47
48 #include "radeon_winsys.h"
49
50 struct radeon_pipe_buffer {
51 struct pipe_buffer base;
52 /* Pointer to GPU-backed BO. */
53 struct radeon_bo *bo;
54 /* Pointer to fallback PB buffer. */
55 struct pb_buffer *pb;
56 boolean flinked;
57 uint32_t flink;
58 };
59
60 #define RADEON_MAX_BOS 24
61
62 struct radeon_winsys_priv {
63 /* DRM FD */
64 int fd;
65
66 /* Radeon BO manager. */
67 struct radeon_bo_manager* bom;
68
69 /* Radeon CS manager. */
70 struct radeon_cs_manager* csm;
71
72 /* Current CS. */
73 struct radeon_cs* cs;
74
75 /* Flush CB */
76 void (*flush_cb)(void *);
77 void *flush_data;
78 };
79
80 struct radeon_winsys* radeon_pipe_winsys(int fb);
81 #if 0
82 struct pipe_surface *radeon_surface_from_handle(struct radeon_context *radeon_context,
83 uint32_t handle,
84 enum pipe_format format,
85 int w, int h, int pitch);
86 #endif
87 #endif