draw: corrections to allow for different cliptest cases
[mesa.git] / src / gallium / winsys / r600 / drm / eg_states.h
1 /*
2 * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17 #ifndef EG_STATES_H
18 #define EG_STATES_H
19
20 static const struct radeon_register EG_names_CONFIG[] = {
21 {0x00008C00, 0, 0, "SQ_CONFIG"},
22 {0x00009100, 0, 0, "SPI_CONFIG_CNTL"},
23 {0x0000913C, 0, 0, "SPI_CONFIG_CNTL_1"},
24 {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
25 {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
26 {0x00008C0C, 0, 0, "SQ_GPR_RESOURCE_MGMT_3"},
27 {0x00008C18, 0, 0, "SQ_THREAD_RESOURCE_MGMT_1"},
28 {0x00008C1C, 0, 0, "SQ_THREAD_RESOURCE_MGMT_2"},
29 {0x00008C20, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
30 {0x00008C24, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
31 {0x00008C28, 0, 0, "SQ_STACK_RESOURCE_MGMT_3"},
32 {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
33 {0x00008A14, 0, 0, "PA_CL_ENHANCE"},
34 {0x00028838, 0, 0, "SQ_DYN_GPR_RESOURCE_LIMIT_1"},
35 {0x000288EC, 0, 0, "SQ_LDS_ALLOC_PS"},
36 {0x00028350, 0, 0, "SX_MISC"},
37 {0x00028900, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
38 {0x00028904, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
39 {0x00028908, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
40 {0x0002890C, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
41 {0x00028910, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
42 {0x00028914, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
43 {0x0002891C, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
44 {0x00028920, 0, 0, "SQ_GS_VERT_ITEMSIZE_1"},
45 {0x00028924, 0, 0, "SQ_GS_VERT_ITEMSIZE_2"},
46 {0x00028928, 0, 0, "SQ_GS_VERT_ITEMSIZE_3"},
47 {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
48 {0x00028A14, 0, 0, "VGT_HOS_CNTL"},
49 {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
50 {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
51 {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
52 {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
53 {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
54 {0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
55 {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
56 {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
57 {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
58 {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
59 {0x00028A40, 0, 0, "VGT_GS_MODE"},
60 {0x00028A48, 0, 0, "PA_SC_MODE_CNTL_0"},
61 {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL_1"},
62 {0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
63 {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
64 {0x00028B54, 0, 0, "VGT_SHADER_STAGES_EN"},
65 {0x00028B94, 0, 0, "VGT_STRMOUT_CONFIG"},
66 {0x00028B98, 0, 0, "VGT_STRMOUT_BUFFER_CONFIG"},
67 };
68
69 static const struct radeon_register EG_names_CB_CNTL[] = {
70 {0x00028238, 0, 0, "CB_TARGET_MASK"},
71 {0x0002823C, 0, 0, "CB_SHADER_MASK"},
72 {0x00028808, 0, 0, "CB_COLOR_CONTROL"},
73 {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
74 {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
75 {0x00028C3C, 0, 0, "PA_SC_AA_MASK"},
76 };
77
78 static const struct radeon_register EG_names_RASTERIZER[] = {
79 {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
80 {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
81 {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
82 {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
83 {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
84 {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
85 {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
86 {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
87 {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
88 {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
89 {0x00028C08, 0, 0, "PA_SU_VTX_CNTL"},
90 {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
91 {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
92 {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
93 {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
94 {0x00028B78, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
95 {0x00028B7C, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
96 {0x00028B80, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
97 {0x00028B84, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
98 {0x00028B88, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
99 {0x00028B8C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
100 };
101
102 /* Viewport states are same as r600 */
103 static const struct radeon_register EG_names_VIEWPORT[] = {
104 {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
105 {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
106 {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
107 {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
108 {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
109 {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
110 {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
111 {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
112 {0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
113 };
114
115 /* scissor is same as R600 */
116 static const struct radeon_register EG_names_SCISSOR[] = {
117 {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
118 {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
119 {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
120 {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
121 {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
122 {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
123 {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
124 {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
125 {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
126 {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
127 {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
128 {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
129 {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
130 {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
131 {0x00028230, 0, 0, "PA_SC_EDGERULE"},
132 {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
133 {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
134 {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
135 {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
136 {0x00028234, 0, 0, "PA_SU_HARDWARE_SCREEN_OFFSET"},
137 };
138
139 /* same as r700 i.e. no blend control */
140 static const struct radeon_register EG_names_BLEND[] = {
141 {0x00028414, 0, 0, "CB_BLEND_RED"},
142 {0x00028418, 0, 0, "CB_BLEND_GREEN"},
143 {0x0002841C, 0, 0, "CB_BLEND_BLUE"},
144 {0x00028420, 0, 0, "CB_BLEND_ALPHA"},
145 {0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
146 {0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
147 {0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
148 {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
149 {0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
150 {0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
151 {0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
152 {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
153 };
154
155 /* different */
156 static const struct radeon_register EG_names_DSA[] = {
157 {0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
158 {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
159 {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
160 {0x00028430, 0, 0, "DB_STENCILREFMASK"},
161 {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
162 {0x00028438, 0, 0, "SX_ALPHA_REF"},
163 {0x000286DC, 0, 0, "SPI_FOG_CNTL"},
164 {0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
165 {0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
166 {0x00028000, 0, 0, "DB_RENDER_CONTROL"},
167 {0x00028004, 0, 0, "DB_COUNT_CONTROL"},
168 {0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"},
169 {0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"},
170 {0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"},
171 {0x00028AC4, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
172 {0x00028AC8, 0, 0, "DB_PRELOAD_CONTROL"},
173 {0x00028B70, 0, 0, "DB_ALPHA_TO_MASK"},
174 };
175
176 /* different */
177 static const struct radeon_register EG_names_VS_SHADER[] = {
178 {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
179 {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
180 {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
181 {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
182 {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
183 {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
184 {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
185 {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
186 {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
187 {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
188 {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
189 {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
190 {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
191 {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
192 {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
193 {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
194 {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
195 {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
196 {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
197 {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
198 {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
199 {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
200 {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
201 {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
202 {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
203 {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
204 {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
205 {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
206 {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
207 {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
208 {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
209 {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
210 {0x0002861C, 0, 0, "SPI_VS_OUT_ID_0"}, // all diff belwo
211 {0x00028620, 0, 0, "SPI_VS_OUT_ID_1"},
212 {0x00028624, 0, 0, "SPI_VS_OUT_ID_2"},
213 {0x00028628, 0, 0, "SPI_VS_OUT_ID_3"},
214 {0x0002862C, 0, 0, "SPI_VS_OUT_ID_4"},
215 {0x00028630, 0, 0, "SPI_VS_OUT_ID_5"},
216 {0x00028634, 0, 0, "SPI_VS_OUT_ID_6"},
217 {0x00028638, 0, 0, "SPI_VS_OUT_ID_7"},
218 {0x0002863C, 0, 0, "SPI_VS_OUT_ID_8"},
219 {0x00028640, 0, 0, "SPI_VS_OUT_ID_9"},
220 {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
221 {0x0002885C, 1, 0, "SQ_PGM_START_VS"},
222 {0x00028860, 0, 0, "SQ_PGM_RESOURCES_VS"},
223 {0x00028864, 0, 0, "SQ_PGM_RESOURCES_2_VS"},
224 {0x000288A4, 1, 1, "SQ_PGM_START_FS"},
225 {0x000288A8, 0, 0, "SQ_PGM_RESOURCES_FS"},
226 };
227
228 static const struct radeon_register EG_names_PS_SHADER[] = {
229 {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
230 {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
231 {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
232 {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
233 {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
234 {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
235 {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
236 {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
237 {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
238 {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
239 {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
240 {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
241 {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
242 {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
243 {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
244 {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
245 {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
246 {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
247 {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
248 {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
249 {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
250 {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
251 {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
252 {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
253 {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
254 {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
255 {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
256 {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
257 {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
258 {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
259 {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
260 {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
261 {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
262 {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
263 {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
264 {0x000286D8, 0, 0, "SPI_INPUT_Z"},
265 {0x000286E0, 0, 0, "SPI_BARYC_CNTL"},
266 {0x000286E4, 0, 0, "SPI_PS_IN_CONTROL_2"},
267 {0x000286E8, 0, 0, "SPI_COMPUTE_INPUT_CNTL"},
268 {0x00028840, 1, 0, "SQ_PGM_START_PS"}, // diff
269 {0x00028844, 0, 0, "SQ_PGM_RESOURCES_PS"}, // diff
270 {0x00028848, 0, 0, "SQ_PGM_RESOURCES_2_PS"}, // diff
271 {0x0002884C, 0, 0, "SQ_PGM_EXPORTS_PS"}, // diff
272 };
273
274 /* different */
275 static const struct radeon_register EG_names_UCP[] = {
276 {0x000285BC, 0, 0, "PA_CL_UCP0_X"},
277 {0x000285C0, 0, 0, "PA_CL_UCP0_Y"},
278 {0x000285C4, 0, 0, "PA_CL_UCP0_Z"},
279 {0x000285C8, 0, 0, "PA_CL_UCP0_W"},
280 {0x000285CC, 0, 0, "PA_CL_UCP1_X"},
281 {0x000285D0, 0, 0, "PA_CL_UCP1_Y"},
282 {0x000285D4, 0, 0, "PA_CL_UCP1_Z"},
283 {0x000285D8, 0, 0, "PA_CL_UCP1_W"},
284 {0x000285DC, 0, 0, "PA_CL_UCP2_X"},
285 {0x000285E0, 0, 0, "PA_CL_UCP2_Y"},
286 {0x000285E4, 0, 0, "PA_CL_UCP2_Z"},
287 {0x000285E8, 0, 0, "PA_CL_UCP2_W"},
288 {0x000285EC, 0, 0, "PA_CL_UCP3_X"},
289 {0x000285F0, 0, 0, "PA_CL_UCP3_Y"},
290 {0x000285F4, 0, 0, "PA_CL_UCP3_Z"},
291 {0x000285F8, 0, 0, "PA_CL_UCP3_W"},
292 {0x000285FC, 0, 0, "PA_CL_UCP4_X"},
293 {0x00028600, 0, 0, "PA_CL_UCP4_Y"},
294 {0x00028604, 0, 0, "PA_CL_UCP4_Z"},
295 {0x00028608, 0, 0, "PA_CL_UCP4_W"},
296 {0x0002860C, 0, 0, "PA_CL_UCP5_X"},
297 {0x00028610, 0, 0, "PA_CL_UCP5_Y"},
298 {0x00028614, 0, 0, "PA_CL_UCP5_Z"},
299 {0x00028618, 0, 0, "PA_CL_UCP5_W"},
300 };
301
302 static const struct radeon_register EG_names_VS_CBUF[] = {
303 {0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"},
304 {0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"},
305 };
306
307 static const struct radeon_register EG_names_PS_CBUF[] = {
308 {0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"},
309 {0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"},
310 };
311
312 static const struct radeon_register EG_names_PS_RESOURCE[] = {
313 {0x00030000, 0, 0, "RESOURCE0_WORD0"},
314 {0x00030004, 0, 0, "RESOURCE0_WORD1"},
315 {0x00030008, 0, 0, "RESOURCE0_WORD2"},
316 {0x0003000C, 0, 0, "RESOURCE0_WORD3"},
317 {0x00030010, 0, 0, "RESOURCE0_WORD4"},
318 {0x00030014, 0, 0, "RESOURCE0_WORD5"},
319 {0x00030018, 0, 0, "RESOURCE0_WORD6"},
320 {0x0003001c, 0, 0, "RESOURCE0_WORD7"},
321 };
322
323 static const struct radeon_register EG_names_VS_RESOURCE[] = {
324 {0x00031600, 0, 0, "RESOURCE160_WORD0"},
325 {0x00031604, 0, 0, "RESOURCE160_WORD1"},
326 {0x00031608, 0, 0, "RESOURCE160_WORD2"},
327 {0x0003160C, 0, 0, "RESOURCE160_WORD3"},
328 {0x00031610, 0, 0, "RESOURCE160_WORD4"},
329 {0x00031614, 0, 0, "RESOURCE160_WORD5"},
330 {0x00031618, 0, 0, "RESOURCE160_WORD6"},
331 {0x0003161c, 0, 0, "RESOURCE160_WORD7"},
332 };
333
334 static const struct radeon_register EG_names_FS_RESOURCE[] = {
335 {0x0003A300, 0, 0, "RESOURCE320_WORD0"},
336 {0x0003A304, 0, 0, "RESOURCE320_WORD1"},
337 {0x0003A308, 0, 0, "RESOURCE320_WORD2"},
338 {0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
339 {0x0003A310, 0, 0, "RESOURCE320_WORD4"},
340 {0x0003A314, 0, 0, "RESOURCE320_WORD5"},
341 {0x0003A318, 0, 0, "RESOURCE320_WORD6"},
342 {0x0003A31C, 0, 0, "RESOURCE320_WORD7"},
343 };
344
345 static const struct radeon_register EG_names_GS_RESOURCE[] = {
346 {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
347 {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
348 {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
349 {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
350 {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
351 {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
352 {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
353 {0x0003A4DC, 0, 0, "RESOURCE336_WORD7"},
354 };
355
356 static const struct radeon_register EG_names_PS_SAMPLER[] = {
357 {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
358 {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
359 {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
360 };
361
362 static const struct radeon_register EG_names_VS_SAMPLER[] = {
363 {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
364 {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
365 {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
366 };
367
368 static const struct radeon_register EG_names_GS_SAMPLER[] = {
369 {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
370 {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
371 {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
372 };
373
374 static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = {
375 {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_INDEX"},
376 {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
377 {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
378 {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
379 {0x0000A410, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
380 };
381
382 static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = {
383 {0x0000A414, 0, 0, "TD_VS_SAMPLER0_BORDER_INDEX"},
384 {0x0000A418, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
385 {0x0000A41C, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
386 {0x0000A420, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
387 {0x0000A424, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
388 };
389
390 static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = {
391 {0x0000A428, 0, 0, "TD_GS_SAMPLER0_BORDER_INDEX"},
392 {0x0000A42C, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
393 {0x0000A430, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
394 {0x0000A434, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
395 {0x0000A438, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
396 };
397
398 static const struct radeon_register EG_names_CB[] = {
399 {0x00028C60, 1, 0, "CB_COLOR0_BASE"},
400 {0x00028C64, 0, 0, "CB_COLOR0_PITCH"},
401 {0x00028C68, 0, 0, "CB_COLOR0_SLICE"},
402 {0x00028C6C, 0, 0, "CB_COLOR0_VIEW"},
403 {0x00028C70, 1, 0, "CB_COLOR0_INFO"},
404 {0x00028C74, 0, 0, "CB_COLOR0_ATTRIB"},
405 {0x00028C78, 0, 0, "CB_COLOR0_DIM"},
406 };
407
408 /* different - TODO */
409 static const struct radeon_register EG_names_DB[] = {
410 {0x00028014, 1, 0, "DB_HTILE_DATA_BASE"},
411 {0x00028040, 1, 0, "DB_Z_INFO"},
412 {0x00028044, 0, 0, "DB_STENCIL_INFO"},
413 {0x00028058, 0, 0, "DB_DEPTH_SIZE"},
414 {0x0002805C, 0, 0, "DB_DEPTH_SLICE"},
415 {0x00028008, 0, 0, "DB_DEPTH_VIEW"},
416 {0x00028ABC, 0, 0, "DB_HTILE_SURFACE"},
417 {0x00028048, 1, 0, "DB_Z_READ_BASE"},
418 {0x0002804C, 1, 0, "DB_STENCIL_READ_BASE"},
419 {0x00028050, 1, 0, "DB_Z_WRITE_BASE"},
420 {0x00028054, 1, 0, "DB_STENCIL_WRITE_BASE"},
421 };
422
423 static const struct radeon_register EG_names_VGT[] = {
424 {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, //s
425 {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, //s
426 {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, //s
427 {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, //s
428 {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, //s
429 {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, //s
430 {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, //s
431 {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, //s
432 {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, //s
433 {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, //s
434 };
435
436 static const struct radeon_register EG_names_DRAW[] = {
437 {0x00008970, 0, 0, "VGT_NUM_INDICES"},
438 {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, //same
439 {0x000287E8, 1, 0, "VGT_DMA_BASE"}, //same
440 {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, //same
441 };
442
443 static const struct radeon_register EG_names_VGT_EVENT[] = {
444 {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, //done
445 };
446
447 static const struct radeon_register EG_names_CB_FLUSH[] = {
448 };
449
450 static const struct radeon_register EG_names_DB_FLUSH[] = {
451 };
452
453 #endif