src/gallium/winsys/r600/drm/r600_bo.c

   1 /*
   2  * Copyright 2010 Dave Airlie
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Dave Airlie
  25  */
  26 #include <pipe/p_compiler.h>
  27 #include <pipe/p_screen.h>
  28 #include <pipebuffer/pb_bufmgr.h>
  29 #include "state_tracker/drm_driver.h"
  30 #include "r600_priv.h"
  31 #include "r600d.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34
  35 struct r600_bo *r600_bo(struct radeon *radeon,
  36                         unsigned size, unsigned alignment,
  37                         unsigned binding, unsigned usage)
  38 {
  39         struct r600_bo *bo;
  40         struct radeon_bo *rbo;
  41         uint32_t initial_domain;
  42
  43         if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
  44                 bo = r600_bomgr_bo_create(radeon->bomgr, size, alignment, *radeon->cfence);
  45                 if (bo) {
  46                         return bo;
  47                 }
  48         }
  49
  50         if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
  51                 initial_domain = RADEON_GEM_DOMAIN_GTT;
  52         } else {
  53                 switch(usage) {
  54                 case PIPE_USAGE_DYNAMIC:
  55                 case PIPE_USAGE_STREAM:
  56                 case PIPE_USAGE_STAGING:
  57                         initial_domain = RADEON_GEM_DOMAIN_GTT;
  58                         break;
  59                 case PIPE_USAGE_DEFAULT:
  60                 case PIPE_USAGE_STATIC:
  61                 case PIPE_USAGE_IMMUTABLE:
  62                 default:
  63                         initial_domain = RADEON_GEM_DOMAIN_VRAM;
  64                         break;
  65                 }
  66         }
  67         rbo = radeon_bo(radeon, 0, size, alignment, initial_domain);
  68         if (rbo == NULL) {
  69                 return NULL;
  70         }
  71
  72         bo = calloc(1, sizeof(struct r600_bo));
  73         bo->size = size;
  74         bo->alignment = alignment;
  75         bo->bo = rbo;
  76         if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
  77                 r600_bomgr_bo_init(radeon->bomgr, bo);
  78         }
  79
  80         /* Staging resources particpate in transfers and blits only
  81          * and are used for uploads and downloads from regular
  82          * resources.  We generate them internally for some transfers.
  83          */
  84         if (usage == PIPE_USAGE_STAGING)
  85                 bo->domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT;
  86         else
  87                 bo->domains = (RADEON_GEM_DOMAIN_CPU |
  88                                 RADEON_GEM_DOMAIN_GTT |
  89                                 RADEON_GEM_DOMAIN_VRAM);
  90
  91         pipe_reference_init(&bo->reference, 1);
  92         return bo;
  93 }
  94
  95 struct r600_bo *r600_bo_handle(struct radeon *radeon,
  96                                unsigned handle, unsigned *array_mode)
  97 {
  98         struct r600_bo *bo = calloc(1, sizeof(struct r600_bo));
  99         struct radeon_bo *rbo;
 100
 101         rbo = bo->bo = radeon_bo(radeon, handle, 0, 0, 0);
 102         if (rbo == NULL) {
 103                 free(bo);
 104                 return NULL;
 105         }
 106         bo->size = rbo->size;
 107         bo->domains = (RADEON_GEM_DOMAIN_CPU |
 108                         RADEON_GEM_DOMAIN_GTT |
 109                         RADEON_GEM_DOMAIN_VRAM);
 110
 111         pipe_reference_init(&bo->reference, 1);
 112
 113         radeon_bo_get_tiling_flags(radeon, rbo, &bo->tiling_flags, &bo->kernel_pitch);
 114         if (array_mode) {
 115                 if (bo->tiling_flags) {
 116                         if (bo->tiling_flags & RADEON_TILING_MACRO)
 117                                 *array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
 118                         else if (bo->tiling_flags & RADEON_TILING_MICRO)
 119                                 *array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
 120                 } else {
 121                         *array_mode = 0;
 122                 }
 123         }
 124         return bo;
 125 }
 126
 127 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx)
 128 {
 129         struct pipe_context *pctx = ctx;
 130
 131         if (usage & PB_USAGE_UNSYNCHRONIZED) {
 132                 radeon_bo_map(radeon, bo->bo);
 133                 return (uint8_t *) bo->bo->data + bo->offset;
 134         }
 135
 136         if (p_atomic_read(&bo->bo->reference.count) > 1) {
 137                 if (usage & PB_USAGE_DONTBLOCK) {
 138                         return NULL;
 139                 }
 140                 if (ctx) {
 141                         pctx->flush(pctx, NULL);
 142                 }
 143         }
 144
 145         if (usage & PB_USAGE_DONTBLOCK) {
 146                 uint32_t domain;
 147
 148                 if (radeon_bo_busy(radeon, bo->bo, &domain))
 149                         return NULL;
 150                 if (radeon_bo_map(radeon, bo->bo)) {
 151                         return NULL;
 152                 }
 153                 goto out;
 154         }
 155
 156         radeon_bo_map(radeon, bo->bo);
 157         if (radeon_bo_wait(radeon, bo->bo)) {
 158                 radeon_bo_unmap(radeon, bo->bo);
 159                 return NULL;
 160         }
 161
 162 out:
 163         return (uint8_t *) bo->bo->data + bo->offset;
 164 }
 165
 166 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo)
 167 {
 168         radeon_bo_unmap(radeon, bo->bo);
 169 }
 170
 171 void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo)
 172 {
 173         if (bo->manager_id) {
 174                 if (!r600_bomgr_bo_destroy(radeon->bomgr, bo)) {
 175                         /* destroy is delayed by buffer manager */
 176                         return;
 177                 }
 178         }
 179         radeon_bo_reference(radeon, &bo->bo, NULL);
 180         free(bo);
 181 }
 182
 183 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *bo,
 184                                 unsigned stride, struct winsys_handle *whandle)
 185 {
 186         whandle->stride = stride;
 187         switch(whandle->type) {
 188         case DRM_API_HANDLE_TYPE_KMS:
 189                 whandle->handle = bo->bo->handle;
 190                 break;
 191         case DRM_API_HANDLE_TYPE_SHARED:
 192                 if (radeon_bo_get_name(radeon, bo->bo, &whandle->handle))
 193                         return FALSE;
 194                 break;
 195         default:
 196                 return FALSE;
 197         }
 198
 199         return TRUE;
 200 }