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Merge branch 'llvm-cliptest-viewport'
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include "xf86drm.h"
32 #include "r600.h"
33 #include "r600d.h"
34 #include "radeon_drm.h"
35 #include "bof.h"
36 #include "pipe/p_compiler.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include <pipebuffer/pb_bufmgr.h>
40 #include "r600_priv.h"
41
42 #define GROUP_FORCE_NEW_BLOCK 0
43
44 int r600_context_init_fence(struct r600_context *ctx)
45 {
46 ctx->fence = 1;
47 ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0);
48 if (ctx->fence_bo == NULL) {
49 return -ENOMEM;
50 }
51 ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL);
52 *ctx->cfence = 0;
53 LIST_INITHEAD(&ctx->fenced_bo);
54 return 0;
55 }
56
57 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
58 {
59 for (int i = 0; i < ctx->creloc; i++) {
60 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
61 LIST_DELINIT(&ctx->bo[i]->fencedlist);
62 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
63 ctx->bo[i]->fence = ctx->fence;
64 ctx->bo[i]->ctx = ctx;
65 }
66 }
67
68 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
69 {
70 struct radeon_bo *bo = NULL;
71 struct radeon_bo *tmp;
72
73 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
74 if (bo->fence <= *ctx->cfence) {
75 LIST_DELINIT(&bo->fencedlist);
76 bo->fence = 0;
77 } else {
78 bo->fence = fence;
79 }
80 }
81 }
82
83 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
84 {
85 struct r600_block *block;
86 struct r600_range *range;
87 int offset;
88
89 for (unsigned i = 0, n = 0; i < nreg; i += n) {
90 u32 j;
91
92 /* ignore new block balise */
93 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
94 n = 1;
95 continue;
96 }
97
98 /* register that need relocation are in their own group */
99 /* find number of consecutive registers */
100 n = 0;
101 offset = reg[i].offset;
102 while (reg[i + n].offset == offset) {
103 n++;
104 offset += 4;
105 if ((n + i) >= nreg)
106 break;
107 if (n >= (R600_BLOCK_MAX_REG - 2))
108 break;
109 }
110
111 /* allocate new block */
112 block = calloc(1, sizeof(struct r600_block));
113 if (block == NULL) {
114 return -ENOMEM;
115 }
116 ctx->nblocks++;
117 for (int j = 0; j < n; j++) {
118 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
119 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
120 }
121
122 /* initialize block */
123 block->start_offset = reg[i].offset;
124 block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n);
125 block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
126 block->reg = &block->pm4[block->pm4_ndwords];
127 block->pm4_ndwords += n;
128 block->nreg = n;
129 LIST_INITHEAD(&block->list);
130
131 for (j = 0; j < n; j++) {
132 if (reg[i+j].need_bo) {
133 block->nbo++;
134 assert(block->nbo < R600_BLOCK_MAX_BO);
135 block->pm4_bo_index[j] = block->nbo;
136 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
137 block->pm4[block->pm4_ndwords++] = 0x00000000;
138 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
139 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
140 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
141 }
142 }
143 for (j = 0; j < n; j++) {
144 if (reg[i+j].flush_flags) {
145 block->pm4_flush_ndwords += 7;
146 }
147 }
148 /* check that we stay in limit */
149 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
150 }
151 return 0;
152 }
153
154 /* R600/R700 configuration */
155 static const struct r600_reg r600_config_reg_list[] = {
156 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
157 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
158 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
159 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
160 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
161 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
162 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
163 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
164 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
165 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
166 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
167 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
168 };
169
170 static const struct r600_reg r600_ctl_const_list[] = {
171 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
172 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
173 };
174
175 static const struct r600_reg r600_context_reg_list[] = {
176 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
177 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
178 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
179 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
180 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
181 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
182 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
183 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
184 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
185 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
186 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
187 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
188 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
189 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
190 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
191 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
192 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
193 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
194 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
195 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
196 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
197 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
198 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
199 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
200 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
201 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
202 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
203 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
204 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
205 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
206 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
207 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
208 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0, 0},
209 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
210 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF},
211 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
212 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
213 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
214 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0, 0},
215 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
216 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0, 0},
217 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
218 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
219 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0, 0},
220 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
221 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF},
222 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
223 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
224 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
225 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0, 0},
226 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
227 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0, 0},
228 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
229 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
230 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0, 0},
231 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
232 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF},
233 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
234 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
235 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
236 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0, 0},
237 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
238 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0, 0},
239 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
240 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
241 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0, 0},
242 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
243 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF},
244 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
245 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
246 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
247 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0, 0},
248 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
249 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0, 0},
250 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
251 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
252 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0, 0},
253 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
254 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF},
255 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
256 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
257 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
258 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0, 0},
259 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
260 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0, 0},
261 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
262 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
263 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0, 0},
264 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
265 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF},
266 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
267 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
268 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
269 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0, 0},
270 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
271 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0, 0},
272 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
273 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0, 0},
274 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF},
275 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
276 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
277 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
278 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0, 0},
279 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
280 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0, 0},
281 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
282 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
283 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0, 0},
284 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
285 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF},
286 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
287 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
288 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0, 0},
289 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0, 0},
290 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
291 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
292 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
293 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
294 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
295 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0},
296 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0},
297 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
298 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
299 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
300 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
301 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
302 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
303 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
304 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
305 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
306 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
307 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
308 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
309 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
310 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
311 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
312 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
313 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
314 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
315 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
316 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
317 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
318 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
319 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
320 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
321 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
322 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
323 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
324 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
325 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
326 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
327 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
328 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
329 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
330 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
331 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
332 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
333 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
334 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
335 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
336 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
337 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
338 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0, 0},
339 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
340 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
341 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
342 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0, 0},
343 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
344 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
345 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
346 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
347 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
348 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
349 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
350 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
351 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
352 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
353 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
354 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
355 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
356 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
357 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
358 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
359 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
360 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
361 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
362 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
363 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
364 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
365 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
366 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
367 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
368 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
369 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
370 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
371 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
372 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
373 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
374 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
375 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
376 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
377 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
378 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
379 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
380 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
381 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
382 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
383 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
384 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
385 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
386 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
387 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
388 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
389 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
390 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
391 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
392 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
393 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
394 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
395 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
396 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
397 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
398 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
399 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
400 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
401 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
402 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
403 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
404 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
405 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
406 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
407 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
408 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
409 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
410 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
411 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
412 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
413 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
414 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
415 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
416 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
417 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
418 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
419 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
420 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
421 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
422 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
423 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
424 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
425 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
426 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
427 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
428 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
429 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
430 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
431 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
432 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
433 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
434 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
435 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
436 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
437 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
438 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
439 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
440 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
441 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
442 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
443 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
444 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
445 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
446 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
447 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
448 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
449 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
450 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
451 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
452 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
453 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
454 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
455 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
456 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
457 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
458 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
459 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
460 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
461 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
462 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
463 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
464 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
465 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
466 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
467 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
468 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
469 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
470 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
471 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
472 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
473 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
474 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
475 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
476 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
477 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
478 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
479 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
480 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
481 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
482 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
483 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
484 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
485 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
486 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
487 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
488 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
489 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
490 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
491 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
492 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
493 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
494 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
495 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
496 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
497 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
498 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
499 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
500 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
501 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
502 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
503 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
504 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
505 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
506 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
507 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
508 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
509 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
510 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
511 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
512 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
513 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
514 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
515 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
516 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
517 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
518 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
519 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
520 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
521 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
522 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
523 };
524
525 /* SHADER RESOURCE R600/R700 */
526 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
527 {
528 struct r600_reg r600_shader_resource[] = {
529 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
530 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
531 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
532 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
533 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
534 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
535 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
536 };
537 unsigned nreg = Elements(r600_shader_resource);
538
539 for (int i = 0; i < nreg; i++) {
540 r600_shader_resource[i].offset += offset;
541 }
542 return r600_context_add_block(ctx, r600_shader_resource, nreg);
543 }
544
545 /* SHADER SAMPLER R600/R700 */
546 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
547 {
548 struct r600_reg r600_shader_sampler[] = {
549 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
550 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
551 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
552 };
553 unsigned nreg = Elements(r600_shader_sampler);
554
555 for (int i = 0; i < nreg; i++) {
556 r600_shader_sampler[i].offset += offset;
557 }
558 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
559 }
560
561 /* SHADER SAMPLER BORDER R600/R700 */
562 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
563 {
564 struct r600_reg r600_shader_sampler_border[] = {
565 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
566 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
567 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
568 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
569 };
570 unsigned nreg = Elements(r600_shader_sampler_border);
571
572 for (int i = 0; i < nreg; i++) {
573 r600_shader_sampler_border[i].offset += offset;
574 }
575 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
576 }
577
578 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
579 {
580 unsigned nreg = 32;
581 struct r600_reg r600_loop_consts[32];
582 int i;
583
584 for (i = 0; i < nreg; i++) {
585 r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
586 r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
587 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
588 r600_loop_consts[i].need_bo = 0;
589 r600_loop_consts[i].flush_flags = 0;
590 r600_loop_consts[i].flush_mask = 0;
591 }
592 return r600_context_add_block(ctx, r600_loop_consts, nreg);
593 }
594
595 /* initialize */
596 void r600_context_fini(struct r600_context *ctx)
597 {
598 struct r600_block *block;
599 struct r600_range *range;
600
601 for (int i = 0; i < 256; i++) {
602 for (int j = 0; j < (1 << ctx->hash_shift); j++) {
603 block = ctx->range[i].blocks[j];
604 if (block) {
605 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
606 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
607 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
608 }
609 free(block);
610 }
611 }
612 free(ctx->range[i].blocks);
613 }
614 free(ctx->reloc);
615 free(ctx->pm4);
616 if (ctx->fence_bo) {
617 r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL);
618 }
619 memset(ctx, 0, sizeof(struct r600_context));
620 }
621
622 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
623 {
624 int r;
625
626 memset(ctx, 0, sizeof(struct r600_context));
627 ctx->radeon = radeon;
628 LIST_INITHEAD(&ctx->query_list);
629
630 /* initialize hash */
631 ctx->hash_size = 19;
632 ctx->hash_shift = 11;
633 for (int i = 0; i < 256; i++) {
634 ctx->range[i].start_offset = i << ctx->hash_shift;
635 ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
636 ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
637 if (ctx->range[i].blocks == NULL) {
638 return -ENOMEM;
639 }
640 }
641
642 /* add blocks */
643 r = r600_context_add_block(ctx, r600_config_reg_list,
644 Elements(r600_config_reg_list));
645 if (r)
646 goto out_err;
647 r = r600_context_add_block(ctx, r600_context_reg_list,
648 Elements(r600_context_reg_list));
649 if (r)
650 goto out_err;
651 r = r600_context_add_block(ctx, r600_ctl_const_list,
652 Elements(r600_ctl_const_list));
653 if (r)
654 goto out_err;
655
656 /* PS SAMPLER BORDER */
657 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
658 r = r600_state_sampler_border_init(ctx, offset);
659 if (r)
660 goto out_err;
661 }
662
663 /* VS SAMPLER BORDER */
664 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
665 r = r600_state_sampler_border_init(ctx, offset);
666 if (r)
667 goto out_err;
668 }
669 /* PS SAMPLER */
670 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
671 r = r600_state_sampler_init(ctx, offset);
672 if (r)
673 goto out_err;
674 }
675 /* VS SAMPLER */
676 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
677 r = r600_state_sampler_init(ctx, offset);
678 if (r)
679 goto out_err;
680 }
681 /* PS RESOURCE */
682 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
683 r = r600_state_resource_init(ctx, offset);
684 if (r)
685 goto out_err;
686 }
687 /* VS RESOURCE */
688 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
689 r = r600_state_resource_init(ctx, offset);
690 if (r)
691 goto out_err;
692 }
693
694 /* PS loop const */
695 r600_loop_const_init(ctx, 0);
696 /* VS loop const */
697 r600_loop_const_init(ctx, 32);
698
699 /* setup block table */
700 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
701 for (int i = 0, c = 0; i < 256; i++) {
702 for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
703 if (ctx->range[i].blocks[j]) {
704 add = 1;
705 for (int k = 0; k < c; k++) {
706 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
707 add = 0;
708 break;
709 }
710 }
711 if (add) {
712 assert(c < ctx->nblocks);
713 ctx->blocks[c++] = ctx->range[i].blocks[j];
714 j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
715 }
716 }
717 }
718 }
719
720 /* allocate cs variables */
721 ctx->nreloc = RADEON_CTX_MAX_PM4;
722 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
723 if (ctx->reloc == NULL) {
724 r = -ENOMEM;
725 goto out_err;
726 }
727 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
728 if (ctx->bo == NULL) {
729 r = -ENOMEM;
730 goto out_err;
731 }
732 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
733 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
734 if (ctx->pm4 == NULL) {
735 r = -ENOMEM;
736 goto out_err;
737 }
738 /* save 16dwords space for fence mecanism */
739 ctx->pm4_ndwords -= 16;
740
741 r = r600_context_init_fence(ctx);
742 if (r) {
743 goto out_err;
744 }
745
746 /* init dirty list */
747 LIST_INITHEAD(&ctx->dirty);
748 return 0;
749 out_err:
750 r600_context_fini(ctx);
751 return r;
752 }
753
754 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
755 unsigned flush_mask, struct r600_bo *rbo)
756 {
757 struct radeon_bo *bo;
758
759 bo = r600_bo_get_bo(rbo);
760 /* if bo has already been flush */
761 if (!(bo->last_flush ^ flush_flags)) {
762 bo->last_flush &= flush_mask;
763 return;
764 }
765 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
766 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
767 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
768 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
769 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
770 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
771 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
772 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
773 }
774
775 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
776 {
777 struct radeon_bo *bo;
778
779 bo = r600_bo_get_bo(rbo);
780 assert(bo != NULL);
781 if (bo->reloc) {
782 *pm4 = bo->reloc_id;
783 return;
784 }
785 bo->reloc = &ctx->reloc[ctx->creloc];
786 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
787 ctx->reloc[ctx->creloc].handle = bo->handle;
788 ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
789 ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
790 ctx->reloc[ctx->creloc].flags = 0;
791 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
792 ctx->creloc++;
793 /* set PKT3 to point to proper reloc */
794 *pm4 = bo->reloc_id;
795 }
796
797 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
798 {
799 struct r600_range *range;
800 struct r600_block *block;
801
802 for (int i = 0; i < state->nregs; i++) {
803 unsigned id;
804
805 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
806 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
807 id = (state->regs[i].offset - block->start_offset) >> 2;
808 block->reg[id] &= ~state->regs[i].mask;
809 block->reg[id] |= state->regs[i].value;
810 if (block->pm4_bo_index[id]) {
811 /* find relocation */
812 id = block->pm4_bo_index[id];
813 r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
814 }
815 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
816 block->status |= R600_BLOCK_STATUS_ENABLED;
817 block->status |= R600_BLOCK_STATUS_DIRTY;
818 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
819 LIST_ADDTAIL(&block->list,&ctx->dirty);
820 }
821 }
822 }
823
824 static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
825 {
826 struct r600_range *range;
827 struct r600_block *block;
828
829 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
830 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
831 if (state == NULL) {
832 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
833 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
834 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
835 LIST_DELINIT(&block->list);
836 return;
837 }
838 block->reg[0] = state->regs[0].value;
839 block->reg[1] = state->regs[1].value;
840 block->reg[2] = state->regs[2].value;
841 block->reg[3] = state->regs[3].value;
842 block->reg[4] = state->regs[4].value;
843 block->reg[5] = state->regs[5].value;
844 block->reg[6] = state->regs[6].value;
845 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
846 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
847 if (state->regs[0].bo) {
848 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
849 * we have single case btw VERTEX & TEXTURE resource
850 */
851 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
852 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
853 } else {
854 /* TEXTURE RESOURCE */
855 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
856 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
857 }
858 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
859 block->status |= R600_BLOCK_STATUS_ENABLED;
860 block->status |= R600_BLOCK_STATUS_DIRTY;
861 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
862 LIST_ADDTAIL(&block->list,&ctx->dirty);
863 }
864 }
865
866 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
867 {
868 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
869
870 r600_context_pipe_state_set_resource(ctx, state, offset);
871 }
872
873 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
874 {
875 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
876
877 r600_context_pipe_state_set_resource(ctx, state, offset);
878 }
879
880 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
881 {
882 struct r600_range *range;
883 struct r600_block *block;
884
885 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
886 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
887 if (state == NULL) {
888 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
889 LIST_DELINIT(&block->list);
890 return;
891 }
892 block->reg[0] = state->regs[0].value;
893 block->reg[1] = state->regs[1].value;
894 block->reg[2] = state->regs[2].value;
895 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
896 block->status |= R600_BLOCK_STATUS_ENABLED;
897 block->status |= R600_BLOCK_STATUS_DIRTY;
898 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
899 LIST_ADDTAIL(&block->list,&ctx->dirty);
900 }
901 }
902
903 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
904 {
905 struct r600_range *range;
906 struct r600_block *block;
907
908 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
909 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
910 if (state == NULL) {
911 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
912 LIST_DELINIT(&block->list);
913 return;
914 }
915 if (state->nregs <= 3) {
916 return;
917 }
918 block->reg[0] = state->regs[3].value;
919 block->reg[1] = state->regs[4].value;
920 block->reg[2] = state->regs[5].value;
921 block->reg[3] = state->regs[6].value;
922 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
923 block->status |= R600_BLOCK_STATUS_ENABLED;
924 block->status |= R600_BLOCK_STATUS_DIRTY;
925 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
926 LIST_ADDTAIL(&block->list,&ctx->dirty);
927 }
928 }
929
930 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
931 {
932 unsigned offset;
933
934 offset = 0x0003C000 + id * 0xc;
935 r600_context_pipe_state_set_sampler(ctx, state, offset);
936 offset = 0x0000A400 + id * 0x10;
937 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
938 }
939
940 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
941 {
942 unsigned offset;
943
944 offset = 0x0003C0D8 + id * 0xc;
945 r600_context_pipe_state_set_sampler(ctx, state, offset);
946 offset = 0x0000A600 + id * 0x10;
947 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
948 }
949
950 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
951 {
952 struct r600_range *range;
953 struct r600_block *block;
954 unsigned id;
955
956 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
957 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
958 offset -= block->start_offset;
959 id = block->pm4_bo_index[offset >> 2];
960 if (block->reloc[id].bo) {
961 return block->reloc[id].bo;
962 }
963 return NULL;
964 }
965
966 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
967 {
968 struct r600_bo *cb[8];
969 struct r600_bo *db;
970 unsigned ndwords = 9;
971 struct r600_block *dirty_block = NULL;
972 struct r600_block *next_block;
973
974 if (draw->indices) {
975 ndwords = 13;
976 /* make sure there is enough relocation space before scheduling draw */
977 if (ctx->creloc >= (ctx->nreloc - 1)) {
978 r600_context_flush(ctx);
979 }
980 }
981
982 /* find number of color buffer */
983 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
984 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
985 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
986 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
987 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
988 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
989 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
990 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
991 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
992 for (int i = 0; i < 8; i++) {
993 if (cb[i]) {
994 ndwords += 7;
995 }
996 }
997 if (db)
998 ndwords += 7;
999
1000 /* queries need some special values */
1001 if (ctx->num_query_running) {
1002 if (ctx->radeon->family >= CHIP_RV770) {
1003 r600_context_reg(ctx,
1004 R_028D0C_DB_RENDER_CONTROL,
1005 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1006 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1007 }
1008 r600_context_reg(ctx,
1009 R_028D10_DB_RENDER_OVERRIDE,
1010 S_028D10_NOOP_CULL_DISABLE(1),
1011 S_028D10_NOOP_CULL_DISABLE(1));
1012 }
1013
1014 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1015 /* need to flush */
1016 r600_context_flush(ctx);
1017 }
1018 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1019 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1020 R600_ERR("context is too big to be scheduled\n");
1021 return;
1022 }
1023
1024 /* enough room to copy packet */
1025 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) {
1026 r600_context_block_emit_dirty(ctx, dirty_block);
1027 }
1028
1029 /* draw packet */
1030 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
1031 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1032 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
1033 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1034 if (draw->indices) {
1035 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
1036 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1037 ctx->pm4[ctx->pm4_cdwords++] = 0;
1038 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1039 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1040 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1041 ctx->pm4[ctx->pm4_cdwords++] = 0;
1042 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1043 } else {
1044 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
1045 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1046 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1047 }
1048 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
1049 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
1050
1051 /* flush color buffer */
1052 for (int i = 0; i < 8; i++) {
1053 if (cb[i]) {
1054 r600_context_bo_flush(ctx,
1055 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1056 S_0085F0_CB_ACTION_ENA(1),
1057 0, cb[i]);
1058 }
1059 }
1060 if (db) {
1061 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1062 }
1063
1064 /* all dirty state have been scheduled in current cs */
1065 ctx->pm4_dirty_cdwords = 0;
1066 }
1067
1068 void r600_context_flush(struct r600_context *ctx)
1069 {
1070 struct drm_radeon_cs drmib;
1071 struct drm_radeon_cs_chunk chunks[2];
1072 uint64_t chunk_array[2];
1073 unsigned fence;
1074 int r;
1075
1076 if (!ctx->pm4_cdwords)
1077 return;
1078
1079 /* suspend queries */
1080 r600_context_queries_suspend(ctx);
1081
1082 radeon_bo_pbmgr_flush_maps(ctx->radeon->kman);
1083
1084 /* emit fence */
1085 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4);
1086 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT | (5 << 8);
1087 ctx->pm4[ctx->pm4_cdwords++] = 0;
1088 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1089 ctx->pm4[ctx->pm4_cdwords++] = ctx->fence;
1090 ctx->pm4[ctx->pm4_cdwords++] = 0;
1091 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1092 ctx->pm4[ctx->pm4_cdwords++] = 0;
1093 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->fence_bo);
1094
1095 #if 1
1096 /* emit cs */
1097 drmib.num_chunks = 2;
1098 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1099 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1100 chunks[0].length_dw = ctx->pm4_cdwords;
1101 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1102 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1103 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1104 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1105 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1106 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1107 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1108 sizeof(struct drm_radeon_cs));
1109 #endif
1110
1111 r600_context_update_fenced_list(ctx);
1112
1113 fence = ctx->fence + 1;
1114 if (fence < ctx->fence) {
1115 /* wrap around */
1116 fence = 1;
1117 r600_context_fence_wraparound(ctx, fence);
1118 }
1119 ctx->fence = fence;
1120
1121 /* restart */
1122 for (int i = 0; i < ctx->creloc; i++) {
1123 ctx->bo[i]->reloc = NULL;
1124 ctx->bo[i]->last_flush = 0;
1125 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1126 }
1127 ctx->creloc = 0;
1128 ctx->pm4_dirty_cdwords = 0;
1129 ctx->pm4_cdwords = 0;
1130
1131 /* resume queries */
1132 r600_context_queries_resume(ctx);
1133
1134 /* set all valid group as dirty so they get reemited on
1135 * next draw command
1136 */
1137 for (int i = 0; i < ctx->nblocks; i++) {
1138 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1139 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1140 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1141 }
1142 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1143 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1144 }
1145 }
1146 }
1147
1148 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1149 {
1150 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1151 unsigned i;
1152
1153 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1154 root = bof_object();
1155 if (root == NULL)
1156 goto out_err;
1157 device_id = bof_int32(ctx->radeon->device);
1158 if (device_id == NULL)
1159 goto out_err;
1160 if (bof_object_set(root, "device_id", device_id))
1161 goto out_err;
1162 bof_decref(device_id);
1163 device_id = NULL;
1164 /* dump relocs */
1165 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1166 if (blob == NULL)
1167 goto out_err;
1168 if (bof_object_set(root, "reloc", blob))
1169 goto out_err;
1170 bof_decref(blob);
1171 blob = NULL;
1172 /* dump cs */
1173 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1174 if (blob == NULL)
1175 goto out_err;
1176 if (bof_object_set(root, "pm4", blob))
1177 goto out_err;
1178 bof_decref(blob);
1179 blob = NULL;
1180 /* dump bo */
1181 array = bof_array();
1182 if (array == NULL)
1183 goto out_err;
1184 for (i = 0; i < ctx->creloc; i++) {
1185 struct radeon_bo *rbo = ctx->bo[i];
1186 bo = bof_object();
1187 if (bo == NULL)
1188 goto out_err;
1189 size = bof_int32(rbo->size);
1190 if (size == NULL)
1191 goto out_err;
1192 if (bof_object_set(bo, "size", size))
1193 goto out_err;
1194 bof_decref(size);
1195 size = NULL;
1196 handle = bof_int32(rbo->handle);
1197 if (handle == NULL)
1198 goto out_err;
1199 if (bof_object_set(bo, "handle", handle))
1200 goto out_err;
1201 bof_decref(handle);
1202 handle = NULL;
1203 radeon_bo_map(ctx->radeon, rbo);
1204 blob = bof_blob(rbo->size, rbo->data);
1205 radeon_bo_unmap(ctx->radeon, rbo);
1206 if (blob == NULL)
1207 goto out_err;
1208 if (bof_object_set(bo, "data", blob))
1209 goto out_err;
1210 bof_decref(blob);
1211 blob = NULL;
1212 if (bof_array_append(array, bo))
1213 goto out_err;
1214 bof_decref(bo);
1215 bo = NULL;
1216 }
1217 if (bof_object_set(root, "bo", array))
1218 goto out_err;
1219 bof_dump_file(root, file);
1220 out_err:
1221 bof_decref(blob);
1222 bof_decref(array);
1223 bof_decref(bo);
1224 bof_decref(size);
1225 bof_decref(handle);
1226 bof_decref(device_id);
1227 bof_decref(root);
1228 }
1229
1230 static void r600_query_result(struct r600_context *ctx, struct r600_query *query)
1231 {
1232 u64 start, end;
1233 u32 *results;
1234 int i;
1235
1236 results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL);
1237 for (i = 0; i < query->num_results; i += 4) {
1238 start = (u64)results[i] | (u64)results[i + 1] << 32;
1239 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1240 if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
1241 query->result += end - start;
1242 }
1243 }
1244 r600_bo_unmap(ctx->radeon, query->buffer);
1245 query->num_results = 0;
1246 }
1247
1248 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1249 {
1250 /* query request needs 6 dwords for begin + 6 dwords for end */
1251 if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1252 /* need to flush */
1253 r600_context_flush(ctx);
1254 }
1255
1256 /* if query buffer is full force a flush */
1257 if (query->num_results >= ((query->buffer_size >> 2) - 2)) {
1258 r600_context_flush(ctx);
1259 r600_query_result(ctx, query);
1260 }
1261
1262 /* emit begin query */
1263 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1264 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
1265 ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer);
1266 ctx->pm4[ctx->pm4_cdwords++] = 0;
1267 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1268 ctx->pm4[ctx->pm4_cdwords++] = 0;
1269 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1270
1271 query->state |= R600_QUERY_STATE_STARTED;
1272 query->state ^= R600_QUERY_STATE_ENDED;
1273 ctx->num_query_running++;
1274 }
1275
1276 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1277 {
1278 /* emit begin query */
1279 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1280 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
1281 ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer);
1282 ctx->pm4[ctx->pm4_cdwords++] = 0;
1283 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1284 ctx->pm4[ctx->pm4_cdwords++] = 0;
1285 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1286
1287 query->num_results += 16;
1288 query->state ^= R600_QUERY_STATE_STARTED;
1289 query->state |= R600_QUERY_STATE_ENDED;
1290 ctx->num_query_running--;
1291 }
1292
1293 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1294 {
1295 struct r600_query *query;
1296
1297 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
1298 return NULL;
1299
1300 query = calloc(1, sizeof(struct r600_query));
1301 if (query == NULL)
1302 return NULL;
1303
1304 query->type = query_type;
1305 query->buffer_size = 4096;
1306
1307 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0);
1308 if (!query->buffer) {
1309 free(query);
1310 return NULL;
1311 }
1312
1313 LIST_ADDTAIL(&query->list, &ctx->query_list);
1314
1315 return query;
1316 }
1317
1318 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1319 {
1320 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1321 LIST_DELINIT(&query->list);
1322 free(query);
1323 }
1324
1325 boolean r600_context_query_result(struct r600_context *ctx,
1326 struct r600_query *query,
1327 boolean wait, void *vresult)
1328 {
1329 uint64_t *result = (uint64_t*)vresult;
1330
1331 if (query->num_results) {
1332 r600_context_flush(ctx);
1333 }
1334 r600_query_result(ctx, query);
1335 *result = query->result;
1336 query->result = 0;
1337 return TRUE;
1338 }
1339
1340 void r600_context_queries_suspend(struct r600_context *ctx)
1341 {
1342 struct r600_query *query;
1343
1344 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1345 if (query->state & R600_QUERY_STATE_STARTED) {
1346 r600_query_end(ctx, query);
1347 query->state |= R600_QUERY_STATE_SUSPENDED;
1348 }
1349 }
1350 }
1351
1352 void r600_context_queries_resume(struct r600_context *ctx)
1353 {
1354 struct r600_query *query;
1355
1356 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1357 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1358 r600_query_begin(ctx, query);
1359 query->state ^= R600_QUERY_STATE_SUSPENDED;
1360 }
1361 }
1362 }