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r600g: use backend mask for occlusion queries
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include <pipe/p_compiler.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include <pipebuffer/pb_bufmgr.h>
35 #include "xf86drm.h"
36 #include "radeon_drm.h"
37 #include "r600_priv.h"
38 #include "r600d.h"
39
40 #define GROUP_FORCE_NEW_BLOCK 0
41
42 /* Get backends mask */
43 void r600_get_backend_mask(struct r600_context *ctx)
44 {
45 struct r600_bo * buffer;
46 u32 * results;
47 unsigned num_backends = r600_get_num_backends(ctx->radeon);
48 unsigned i, mask = 0;
49
50 /* if backend_map query is supported by the kernel */
51 if (ctx->radeon->backend_map_valid) {
52 unsigned num_tile_pipes = r600_get_num_tile_pipes(ctx->radeon);
53 unsigned backend_map = r600_get_backend_map(ctx->radeon);
54 unsigned item_width, item_mask;
55
56 if (ctx->radeon->chip_class >= EVERGREEN) {
57 item_width = 4;
58 item_mask = 0x7;
59 } else {
60 item_width = 2;
61 item_mask = 0x3;
62 }
63
64 while(num_tile_pipes--) {
65 i = backend_map & item_mask;
66 mask |= (1<<i);
67 backend_map >>= item_width;
68 }
69 if (mask != 0) {
70 ctx->backend_mask = mask;
71 return;
72 }
73 }
74
75 /* otherwise backup path for older kernels */
76
77 /* create buffer for event data */
78 buffer = r600_bo(ctx->radeon, ctx->max_db*16, 1, 0,
79 PIPE_USAGE_STAGING);
80 if (!buffer)
81 goto err;
82
83 /* initialize buffer with zeroes */
84 results = r600_bo_map(ctx->radeon, buffer, PB_USAGE_CPU_WRITE, NULL);
85 if (results) {
86 memset(results, 0, ctx->max_db * 4 * 4);
87 r600_bo_unmap(ctx->radeon, buffer);
88
89 /* emit EVENT_WRITE for ZPASS_DONE */
90 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
91 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
92 ctx->pm4[ctx->pm4_cdwords++] = 0;
93 ctx->pm4[ctx->pm4_cdwords++] = 0;
94
95 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
96 ctx->pm4[ctx->pm4_cdwords++] = 0;
97 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], buffer);
98
99 /* execute */
100 r600_context_flush(ctx);
101
102 /* analyze results */
103 results = r600_bo_map(ctx->radeon, buffer, PB_USAGE_CPU_READ, NULL);
104 if (results) {
105 for(i = 0; i < ctx->max_db; i++) {
106 /* at least highest bit will be set if backend is used */
107 if (results[i*4 + 1])
108 mask |= (1<<i);
109 }
110 r600_bo_unmap(ctx->radeon, buffer);
111 }
112 }
113
114 r600_bo_reference(ctx->radeon, &buffer, NULL);
115
116 if (mask != 0) {
117 ctx->backend_mask = mask;
118 return;
119 }
120
121 err:
122 /* fallback to old method - set num_backends lower bits to 1 */
123 ctx->backend_mask = (~((u32)0))>>(32-num_backends);
124 return;
125 }
126
127 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
128 {
129 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
130 return;
131
132 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
133 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
134
135 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
136 }
137
138 void r600_init_cs(struct r600_context *ctx)
139 {
140 /* R6xx requires this packet at the start of each command buffer */
141 if (ctx->radeon->family < CHIP_RV770) {
142 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
143 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
144 }
145 /* All asics require this one */
146 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
147 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
148 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
149
150 ctx->init_dwords = ctx->pm4_cdwords;
151 }
152
153 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
154 {
155 for (int i = 0; i < ctx->creloc; i++) {
156 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
157 LIST_DELINIT(&ctx->bo[i]->fencedlist);
158 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
159 ctx->bo[i]->fence = ctx->radeon->fence;
160 ctx->bo[i]->ctx = ctx;
161 }
162 }
163
164 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
165 {
166 struct radeon_bo *bo = NULL;
167 struct radeon_bo *tmp;
168
169 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
170 if (bo->fence <= *ctx->radeon->cfence) {
171 LIST_DELINIT(&bo->fencedlist);
172 bo->fence = 0;
173 } else {
174 bo->fence = fence;
175 }
176 }
177 }
178
179 static void r600_init_block(struct r600_context *ctx,
180 struct r600_block *block,
181 const struct r600_reg *reg, int index, int nreg,
182 unsigned opcode, unsigned offset_base)
183 {
184 int i = index;
185 int j, n = nreg;
186
187 /* initialize block */
188 if (opcode == PKT3_SET_RESOURCE) {
189 block->flags = BLOCK_FLAG_RESOURCE;
190 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
191 } else {
192 block->flags = 0;
193 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
194 }
195 block->start_offset = reg[i].offset;
196 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
197 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
198 block->reg = &block->pm4[block->pm4_ndwords];
199 block->pm4_ndwords += n;
200 block->nreg = n;
201 block->nreg_dirty = n;
202 LIST_INITHEAD(&block->list);
203 LIST_INITHEAD(&block->enable_list);
204
205 for (j = 0; j < n; j++) {
206 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
207 block->flags |= REG_FLAG_DIRTY_ALWAYS;
208 }
209 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
210 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
211 block->status |= R600_BLOCK_STATUS_ENABLED;
212 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
213 LIST_ADDTAIL(&block->list,&ctx->dirty);
214 }
215 }
216 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
217 block->flags |= REG_FLAG_FLUSH_CHANGE;
218 }
219
220 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
221 block->nbo++;
222 assert(block->nbo < R600_BLOCK_MAX_BO);
223 block->pm4_bo_index[j] = block->nbo;
224 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
225 block->pm4[block->pm4_ndwords++] = 0x00000000;
226 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
227 block->reloc[block->nbo].flush_flags = 0;
228 block->reloc[block->nbo].flush_mask = 0;
229 } else {
230 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
231 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
232 }
233 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
234 }
235 if ((ctx->radeon->family > CHIP_R600) &&
236 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
237 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
238 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
239 }
240 }
241 for (j = 0; j < n; j++) {
242 if (reg[i+j].flush_flags) {
243 block->pm4_flush_ndwords += 7;
244 }
245 }
246 /* check that we stay in limit */
247 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
248 }
249
250 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
251 unsigned opcode, unsigned offset_base)
252 {
253 struct r600_block *block;
254 struct r600_range *range;
255 int offset;
256
257 for (unsigned i = 0, n = 0; i < nreg; i += n) {
258 /* ignore new block balise */
259 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
260 n = 1;
261 continue;
262 }
263
264 /* ignore regs not on R600 on R600 */
265 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
266 n = 1;
267 continue;
268 }
269
270 /* register that need relocation are in their own group */
271 /* find number of consecutive registers */
272 n = 0;
273 offset = reg[i].offset;
274 while (reg[i + n].offset == offset) {
275 n++;
276 offset += 4;
277 if ((n + i) >= nreg)
278 break;
279 if (n >= (R600_BLOCK_MAX_REG - 2))
280 break;
281 }
282
283 /* allocate new block */
284 block = calloc(1, sizeof(struct r600_block));
285 if (block == NULL) {
286 return -ENOMEM;
287 }
288 ctx->nblocks++;
289 for (int j = 0; j < n; j++) {
290 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
291 /* create block table if it doesn't exist */
292 if (!range->blocks)
293 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
294 if (!range->blocks)
295 return -1;
296
297 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
298 }
299
300 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
301
302 }
303 return 0;
304 }
305
306 /* R600/R700 configuration */
307 static const struct r600_reg r600_config_reg_list[] = {
308 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
309 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
310 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
311 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
312 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
313 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
314 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
315 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
316 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
317 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
318 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
319 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
320 };
321
322 static const struct r600_reg r600_ctl_const_list[] = {
323 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
324 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
325 };
326
327 static const struct r600_reg r600_context_reg_list[] = {
328 {R_028350_SX_MISC, 0, 0, 0},
329 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
330 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
331 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
332 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
333 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
334 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
335 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
336 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
337 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
338 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
339 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
340 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
341 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
342 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
343 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
344 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
345 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
346 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
347 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
348 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
349 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
350 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
351 {R_028A40_VGT_GS_MODE, 0, 0, 0},
352 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
353 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
354 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
355 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
356 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
357 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
358 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
359 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
360 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
361 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
362 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
363 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
364 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
365 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
366 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
367 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
368 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
369 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
370 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
371 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
373 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
374 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
375 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
376 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
377 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
378 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
379 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
380 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
381 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
382 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
383 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
384 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
385 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
386 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
387 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
388 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
389 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
390 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
391 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
392 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
393 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
394 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
395 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
396 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
397 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
398 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
399 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
400 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
401 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
402 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
403 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
404 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
405 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
406 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
407 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
408 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
409 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
410 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
411 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
412 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
413 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
414 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
415 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
416 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
417 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
418 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
419 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
420 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
421 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
422 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
423 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
424 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
425 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
426 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
427 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
428 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
429 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
430 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
431 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
432 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
433 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
434 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
435 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
436 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
437 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
438 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
439 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
440 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
441 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
442 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
443 {R_028120_CB_CLEAR_RED, 0, 0, 0},
444 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
445 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
446 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
447 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
448 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
449 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
450 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
451 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
452 {R_028238_CB_TARGET_MASK, 0, 0, 0},
453 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
454 {R_028414_CB_BLEND_RED, 0, 0, 0},
455 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
456 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
457 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
458 {R_028424_CB_FOG_RED, 0, 0, 0},
459 {R_028428_CB_FOG_GREEN, 0, 0, 0},
460 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
461 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
462 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
463 {R_028438_SX_ALPHA_REF, 0, 0, 0},
464 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
465 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
466 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
467 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
468 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
469 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
470 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
471 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
472 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
473 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
474 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
475 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
476 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
477 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
478 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
479 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
480 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
481 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
482 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
483 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
484 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
485 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
486 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
487 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
488 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
489 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
490 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
491 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
492 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
493 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
494 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
495 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
496 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
497 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
498 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
499 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
500 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
501 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
502 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
503 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
504 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
505 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
506 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
507 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
508 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
509 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
510 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
511 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
512 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
513 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
514 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
515 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
516 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
517 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
518 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
519 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
520 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
521 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
522 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
523 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
524 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
525 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
526 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
527 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
528 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
529 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
530 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
531 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
532 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
533 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
534 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
535 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
536 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
537 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
538 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
539 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
540 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
541 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
542 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
543 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
544 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
545 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
546 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
547 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
548 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
549 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
550 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
551 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
552 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
553 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
554 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
555 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
556 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
557 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
558 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
559 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
560 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
561 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
562 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
563 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
564 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
565 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
566 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
567 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
568 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
569 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
570 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
571 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
572 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
573 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
574 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
575 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
576 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
577 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
578 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
579 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
580 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
581 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
582 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
583 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
584 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
585 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
586 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
587 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
588 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
589 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
590 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
591 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
592 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
593 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
594 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
595 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
596 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
597 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
598 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
599 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
600 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
601 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
602 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
603 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
604 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
605 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
606 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
607 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
608 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
609 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
610 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
611 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
612 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
613 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
614 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
615 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
616 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
617 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
618 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
619 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
620 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
621 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
622 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
623 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
624 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
625 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
626 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
627 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
628 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
629 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
630 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
631 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
632 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
633 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
634 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
635 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
636 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
637 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
638 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
639 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
640 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
641 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
642 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
643 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
644 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
645 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
646 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
647 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
648 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
649 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
650 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
651 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
652 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
653 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
654 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
655 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
656 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
657 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
658 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
659 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
660 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
661 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
662 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
663 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
664 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
665 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
666 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
667 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
668 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
669 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
670 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
671 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
672 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
673 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
674 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
675 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
676 };
677
678 /* SHADER RESOURCE R600/R700 */
679 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
680 {
681 int i;
682 struct r600_block *block;
683 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
684 if (range->blocks == NULL)
685 return -ENOMEM;
686
687 reg[0].offset += offset;
688 for (i = 0; i < nblocks; i++) {
689 block = calloc(1, sizeof(struct r600_block));
690 if (block == NULL) {
691 return -ENOMEM;
692 }
693 ctx->nblocks++;
694 range->blocks[i] = block;
695 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
696
697 reg[0].offset += stride;
698 }
699 return 0;
700 }
701
702
703 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
704 {
705 struct r600_reg r600_shader_resource[] = {
706 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
707 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
708 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
709 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
710 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
711 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
712 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
713 };
714 unsigned nreg = Elements(r600_shader_resource);
715
716 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
717 }
718
719 /* SHADER SAMPLER R600/R700 */
720 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
721 {
722 struct r600_reg r600_shader_sampler[] = {
723 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
724 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
725 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
726 };
727 unsigned nreg = Elements(r600_shader_sampler);
728
729 for (int i = 0; i < nreg; i++) {
730 r600_shader_sampler[i].offset += offset;
731 }
732 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
733 }
734
735 /* SHADER SAMPLER BORDER R600/R700 */
736 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
737 {
738 struct r600_reg r600_shader_sampler_border[] = {
739 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
740 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
741 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
742 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
743 };
744 unsigned nreg = Elements(r600_shader_sampler_border);
745
746 for (int i = 0; i < nreg; i++) {
747 r600_shader_sampler_border[i].offset += offset;
748 }
749 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
750 }
751
752 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
753 {
754 unsigned nreg = 32;
755 struct r600_reg r600_loop_consts[32];
756 int i;
757
758 for (i = 0; i < nreg; i++) {
759 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
760 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
761 r600_loop_consts[i].flush_flags = 0;
762 r600_loop_consts[i].flush_mask = 0;
763 }
764 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
765 }
766
767 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
768 {
769 struct radeon_bo *bo, *tmp;
770
771 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
772 LIST_DELINIT(&bo->fencedlist);
773 bo->fence = 0;
774 bo->ctx = NULL;
775 }
776 }
777
778 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
779 {
780 struct r600_block *block;
781 int i;
782 for (i = 0; i < nblocks; i++) {
783 block = range->blocks[i];
784 if (block) {
785 for (int k = 1; k <= block->nbo; k++)
786 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
787 free(block);
788 }
789 }
790 free(range->blocks);
791
792 }
793
794 /* initialize */
795 void r600_context_fini(struct r600_context *ctx)
796 {
797 struct r600_block *block;
798 struct r600_range *range;
799
800 for (int i = 0; i < NUM_RANGES; i++) {
801 if (!ctx->range[i].blocks)
802 continue;
803 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
804 block = ctx->range[i].blocks[j];
805 if (block) {
806 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
807 range = &ctx->range[CTX_RANGE_ID(offset)];
808 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
809 }
810 for (int k = 1; k <= block->nbo; k++) {
811 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
812 }
813 free(block);
814 }
815 }
816 free(ctx->range[i].blocks);
817 }
818 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
819 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
820 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
821 free(ctx->range);
822 free(ctx->blocks);
823 free(ctx->reloc);
824 free(ctx->bo);
825 free(ctx->pm4);
826
827 r600_context_clear_fenced_bo(ctx);
828 memset(ctx, 0, sizeof(struct r600_context));
829 }
830
831 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
832 {
833 int c = *index;
834 for (int j = 0; j < num_blocks; j++) {
835 if (!range->blocks[j])
836 continue;
837
838 ctx->blocks[c++] = range->blocks[j];
839 }
840 *index = c;
841 }
842
843 int r600_setup_block_table(struct r600_context *ctx)
844 {
845 /* setup block table */
846 int c = 0;
847 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
848 if (!ctx->blocks)
849 return -ENOMEM;
850 for (int i = 0; i < NUM_RANGES; i++) {
851 if (!ctx->range[i].blocks)
852 continue;
853 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
854 if (!ctx->range[i].blocks[j])
855 continue;
856
857 add = 1;
858 for (int k = 0; k < c; k++) {
859 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
860 add = 0;
861 break;
862 }
863 }
864 if (add) {
865 assert(c < ctx->nblocks);
866 ctx->blocks[c++] = ctx->range[i].blocks[j];
867 j += (ctx->range[i].blocks[j]->nreg) - 1;
868 }
869 }
870 }
871
872 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
873 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
874 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
875 return 0;
876 }
877
878 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
879 {
880 int r;
881
882 memset(ctx, 0, sizeof(struct r600_context));
883 ctx->radeon = radeon;
884 LIST_INITHEAD(&ctx->query_list);
885
886 /* init dirty list */
887 LIST_INITHEAD(&ctx->dirty);
888 LIST_INITHEAD(&ctx->resource_dirty);
889 LIST_INITHEAD(&ctx->enable_list);
890
891 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
892 if (!ctx->range) {
893 r = -ENOMEM;
894 goto out_err;
895 }
896
897 /* add blocks */
898 r = r600_context_add_block(ctx, r600_config_reg_list,
899 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
900 if (r)
901 goto out_err;
902 r = r600_context_add_block(ctx, r600_context_reg_list,
903 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
904 if (r)
905 goto out_err;
906 r = r600_context_add_block(ctx, r600_ctl_const_list,
907 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
908 if (r)
909 goto out_err;
910
911 /* PS SAMPLER BORDER */
912 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
913 r = r600_state_sampler_border_init(ctx, offset);
914 if (r)
915 goto out_err;
916 }
917
918 /* VS SAMPLER BORDER */
919 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
920 r = r600_state_sampler_border_init(ctx, offset);
921 if (r)
922 goto out_err;
923 }
924 /* PS SAMPLER */
925 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
926 r = r600_state_sampler_init(ctx, offset);
927 if (r)
928 goto out_err;
929 }
930 /* VS SAMPLER */
931 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
932 r = r600_state_sampler_init(ctx, offset);
933 if (r)
934 goto out_err;
935 }
936
937 ctx->num_ps_resources = 160;
938 ctx->num_vs_resources = 160;
939 ctx->num_fs_resources = 16;
940 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
941 if (r)
942 goto out_err;
943 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
944 if (r)
945 goto out_err;
946 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
947 if (r)
948 goto out_err;
949
950 /* PS loop const */
951 r600_loop_const_init(ctx, 0);
952 /* VS loop const */
953 r600_loop_const_init(ctx, 32);
954
955 r = r600_setup_block_table(ctx);
956 if (r)
957 goto out_err;
958
959 /* allocate cs variables */
960 ctx->nreloc = RADEON_CTX_MAX_PM4;
961 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
962 if (ctx->reloc == NULL) {
963 r = -ENOMEM;
964 goto out_err;
965 }
966 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
967 if (ctx->bo == NULL) {
968 r = -ENOMEM;
969 goto out_err;
970 }
971 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
972 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
973 if (ctx->pm4 == NULL) {
974 r = -ENOMEM;
975 goto out_err;
976 }
977
978 r600_init_cs(ctx);
979 /* save 16dwords space for fence mecanism */
980 ctx->pm4_ndwords -= 16;
981
982 LIST_INITHEAD(&ctx->fenced_bo);
983
984 ctx->max_db = 4;
985
986 r600_get_backend_mask(ctx);
987
988 return 0;
989 out_err:
990 r600_context_fini(ctx);
991 return r;
992 }
993
994 /* Flushes all surfaces */
995 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
996 {
997 unsigned ndwords = 5;
998
999 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1000 /* need to flush */
1001 r600_context_flush(ctx);
1002 }
1003
1004 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
1005 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
1006 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
1007 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
1008 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
1009 }
1010
1011 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
1012 unsigned flush_mask, struct r600_bo *rbo)
1013 {
1014 struct radeon_bo *bo;
1015
1016 bo = rbo->bo;
1017 /* if bo has already been flushed */
1018 if (!(~bo->last_flush & flush_flags)) {
1019 bo->last_flush &= flush_mask;
1020 return;
1021 }
1022
1023 if ((ctx->radeon->family < CHIP_RV770) &&
1024 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
1025 G_0085F0_DB_ACTION_ENA(flush_flags))) {
1026 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
1027 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
1028 if ((bo->binding & BO_BOUND_TEXTURE) &&
1029 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
1030 if ((ctx->radeon->family == CHIP_RV670) ||
1031 (ctx->radeon->family == CHIP_RS780) ||
1032 (ctx->radeon->family == CHIP_RS880)) {
1033 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
1034 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
1035 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
1036 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
1037 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
1038 }
1039 }
1040
1041 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
1042 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
1043 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1044 }
1045 } else {
1046 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
1047 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
1048 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
1049 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
1050 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
1051 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1052 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
1053 }
1054 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
1055 }
1056
1057 void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo)
1058 {
1059 struct radeon_bo *bo = rbo->bo;
1060 bo->reloc = &ctx->reloc[ctx->creloc];
1061 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
1062 ctx->reloc[ctx->creloc].handle = bo->handle;
1063 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
1064 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
1065 ctx->reloc[ctx->creloc].flags = 0;
1066 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
1067 rbo->fence = ctx->radeon->fence;
1068 ctx->creloc++;
1069 }
1070
1071 void r600_context_reg(struct r600_context *ctx,
1072 unsigned offset, unsigned value,
1073 unsigned mask)
1074 {
1075 struct r600_range *range;
1076 struct r600_block *block;
1077 unsigned id;
1078 unsigned new_val;
1079 int dirty;
1080
1081 range = &ctx->range[CTX_RANGE_ID(offset)];
1082 block = range->blocks[CTX_BLOCK_ID(offset)];
1083 id = (offset - block->start_offset) >> 2;
1084
1085 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1086
1087 new_val = block->reg[id];
1088 new_val &= ~mask;
1089 new_val |= value;
1090 if (new_val != block->reg[id]) {
1091 dirty |= R600_BLOCK_STATUS_DIRTY;
1092 block->reg[id] = new_val;
1093 }
1094 if (dirty)
1095 r600_context_dirty_block(ctx, block, dirty, id);
1096 }
1097
1098 void r600_context_dirty_block(struct r600_context *ctx,
1099 struct r600_block *block,
1100 int dirty, int index)
1101 {
1102 if ((index + 1) > block->nreg_dirty)
1103 block->nreg_dirty = index + 1;
1104
1105 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1106 block->status |= R600_BLOCK_STATUS_DIRTY;
1107 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1108 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1109 block->status |= R600_BLOCK_STATUS_ENABLED;
1110 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1111 }
1112 LIST_ADDTAIL(&block->list,&ctx->dirty);
1113
1114 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1115 r600_context_ps_partial_flush(ctx);
1116 }
1117 }
1118 }
1119
1120 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1121 {
1122 struct r600_block *block;
1123 unsigned new_val;
1124 int dirty;
1125 for (int i = 0; i < state->nregs; i++) {
1126 unsigned id, reloc_id;
1127 struct r600_pipe_reg *reg = &state->regs[i];
1128
1129 block = reg->block;
1130 id = reg->id;
1131
1132 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1133
1134 new_val = block->reg[id];
1135 new_val &= ~reg->mask;
1136 new_val |= reg->value;
1137 if (new_val != block->reg[id]) {
1138 block->reg[id] = new_val;
1139 dirty |= R600_BLOCK_STATUS_DIRTY;
1140 }
1141 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1142 dirty |= R600_BLOCK_STATUS_DIRTY;
1143 if (block->pm4_bo_index[id]) {
1144 /* find relocation */
1145 reloc_id = block->pm4_bo_index[id];
1146 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
1147 reg->bo->fence = ctx->radeon->fence;
1148 /* always force dirty for relocs for now */
1149 dirty |= R600_BLOCK_STATUS_DIRTY;
1150 }
1151
1152 if (dirty)
1153 r600_context_dirty_block(ctx, block, dirty, id);
1154 }
1155 }
1156
1157 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1158 struct r600_block *block,
1159 int dirty, int index)
1160 {
1161 block->nreg_dirty = index + 1;
1162
1163 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1164 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1165 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1166 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1167 block->status |= R600_BLOCK_STATUS_ENABLED;
1168 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1169 }
1170 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1171 }
1172 }
1173
1174 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1175 {
1176 int dirty;
1177 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
1178 boolean is_vertex;
1179
1180 if (state == NULL) {
1181 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1182 if (block->reloc[1].bo)
1183 block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
1184
1185 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
1186 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1187 LIST_DELINIT(&block->list);
1188 LIST_DELINIT(&block->enable_list);
1189 return;
1190 }
1191
1192 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1193 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1194
1195 if (memcmp(block->reg, state->val, num_regs*4)) {
1196 memcpy(block->reg, state->val, num_regs * 4);
1197 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1198 }
1199
1200 /* if no BOs on block, force dirty */
1201 if (!block->reloc[1].bo || !block->reloc[2].bo)
1202 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1203
1204 if (!dirty) {
1205 if (is_vertex) {
1206 if (block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle)
1207 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1208 } else {
1209 if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1210 (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
1211 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1212 }
1213 }
1214 if (!dirty) {
1215 if (is_vertex)
1216 state->bo[0]->fence = ctx->radeon->fence;
1217 else {
1218 state->bo[0]->fence = ctx->radeon->fence;
1219 state->bo[1]->fence = ctx->radeon->fence;
1220 }
1221 } else {
1222 if (is_vertex) {
1223 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1224 * we have single case btw VERTEX & TEXTURE resource
1225 */
1226 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1227 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1228 state->bo[0]->fence = ctx->radeon->fence;
1229 } else {
1230 /* TEXTURE RESOURCE */
1231 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1232 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
1233 state->bo[0]->fence = ctx->radeon->fence;
1234 state->bo[1]->fence = ctx->radeon->fence;
1235 state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
1236 }
1237 }
1238 if (dirty) {
1239 if (is_vertex)
1240 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1241 else
1242 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1243
1244 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1245 }
1246 }
1247
1248 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1249 {
1250 struct r600_block *block = ctx->ps_resources.blocks[rid];
1251
1252 r600_context_pipe_state_set_resource(ctx, state, block);
1253 }
1254
1255 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1256 {
1257 struct r600_block *block = ctx->vs_resources.blocks[rid];
1258
1259 r600_context_pipe_state_set_resource(ctx, state, block);
1260 }
1261
1262 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1263 {
1264 struct r600_block *block = ctx->fs_resources.blocks[rid];
1265
1266 r600_context_pipe_state_set_resource(ctx, state, block);
1267 }
1268
1269 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1270 {
1271 struct r600_range *range;
1272 struct r600_block *block;
1273 int i;
1274 int dirty;
1275
1276 range = &ctx->range[CTX_RANGE_ID(offset)];
1277 block = range->blocks[CTX_BLOCK_ID(offset)];
1278 if (state == NULL) {
1279 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1280 LIST_DELINIT(&block->list);
1281 LIST_DELINIT(&block->enable_list);
1282 return;
1283 }
1284 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1285 for (i = 0; i < 3; i++) {
1286 if (block->reg[i] != state->regs[i].value) {
1287 block->reg[i] = state->regs[i].value;
1288 dirty |= R600_BLOCK_STATUS_DIRTY;
1289 }
1290 }
1291
1292 if (dirty)
1293 r600_context_dirty_block(ctx, block, dirty, 2);
1294 }
1295
1296
1297 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1298 {
1299 struct r600_range *range;
1300 struct r600_block *block;
1301 int i;
1302 int dirty;
1303
1304 range = &ctx->range[CTX_RANGE_ID(offset)];
1305 block = range->blocks[CTX_BLOCK_ID(offset)];
1306 if (state == NULL) {
1307 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1308 LIST_DELINIT(&block->list);
1309 LIST_DELINIT(&block->enable_list);
1310 return;
1311 }
1312 if (state->nregs <= 3) {
1313 return;
1314 }
1315 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1316 for (i = 0; i < 4; i++) {
1317 if (block->reg[i] != state->regs[i + 3].value) {
1318 block->reg[i] = state->regs[i + 3].value;
1319 dirty |= R600_BLOCK_STATUS_DIRTY;
1320 }
1321 }
1322
1323 /* We have to flush the shaders before we change the border color
1324 * registers, or previous draw commands that haven't completed yet
1325 * will end up using the new border color. */
1326 if (dirty & R600_BLOCK_STATUS_DIRTY)
1327 r600_context_ps_partial_flush(ctx);
1328 if (dirty)
1329 r600_context_dirty_block(ctx, block, dirty, 3);
1330 }
1331
1332 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1333 {
1334 unsigned offset;
1335
1336 offset = 0x0003C000 + id * 0xc;
1337 r600_context_pipe_state_set_sampler(ctx, state, offset);
1338 offset = 0x0000A400 + id * 0x10;
1339 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1340 }
1341
1342 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1343 {
1344 unsigned offset;
1345
1346 offset = 0x0003C0D8 + id * 0xc;
1347 r600_context_pipe_state_set_sampler(ctx, state, offset);
1348 offset = 0x0000A600 + id * 0x10;
1349 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1350 }
1351
1352 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1353 {
1354 struct r600_range *range;
1355 struct r600_block *block;
1356 unsigned id;
1357
1358 range = &ctx->range[CTX_RANGE_ID(offset)];
1359 block = range->blocks[CTX_BLOCK_ID(offset)];
1360 offset -= block->start_offset;
1361 id = block->pm4_bo_index[offset >> 2];
1362 if (block->reloc[id].bo) {
1363 return block->reloc[id].bo;
1364 }
1365 return NULL;
1366 }
1367
1368 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1369 {
1370 int id;
1371 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1372 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1373 int new_dwords = 0;
1374 int nbo = block->nbo;
1375
1376 if (block->nreg_dirty == 0 && optional) {
1377 goto out;
1378 }
1379
1380 if (nbo) {
1381 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1382
1383 for (int j = 0; j < block->nreg; j++) {
1384 if (block->pm4_bo_index[j]) {
1385 /* find relocation */
1386 id = block->pm4_bo_index[j];
1387 r600_context_bo_reloc(ctx,
1388 &block->pm4[block->reloc[id].bo_pm4_index],
1389 block->reloc[id].bo);
1390 r600_context_bo_flush(ctx,
1391 block->reloc[id].flush_flags,
1392 block->reloc[id].flush_mask,
1393 block->reloc[id].bo);
1394 nbo--;
1395 if (nbo == 0)
1396 break;
1397 }
1398 }
1399 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1400 }
1401
1402 optional &= (block->nreg_dirty != block->nreg);
1403 if (optional) {
1404 new_dwords = block->nreg_dirty;
1405 start_dword = ctx->pm4_cdwords;
1406 cp_dwords = new_dwords + 2;
1407 }
1408 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1409 ctx->pm4_cdwords += cp_dwords;
1410
1411 if (optional) {
1412 uint32_t newword;
1413
1414 newword = ctx->pm4[start_dword];
1415 newword &= PKT_COUNT_C;
1416 newword |= PKT_COUNT_S(new_dwords);
1417 ctx->pm4[start_dword] = newword;
1418 }
1419 out:
1420 block->status ^= R600_BLOCK_STATUS_DIRTY;
1421 block->nreg_dirty = 0;
1422 LIST_DELINIT(&block->list);
1423 }
1424
1425 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1426 {
1427 int id;
1428 int cp_dwords = block->pm4_ndwords;
1429 int nbo = block->nbo;
1430
1431 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1432
1433 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1434 nbo = 1;
1435 cp_dwords -= 2; /* don't copy the second NOP */
1436 }
1437
1438 for (int j = 0; j < nbo; j++) {
1439 if (block->pm4_bo_index[j]) {
1440 /* find relocation */
1441 id = block->pm4_bo_index[j];
1442 r600_context_bo_reloc(ctx,
1443 &block->pm4[block->reloc[id].bo_pm4_index],
1444 block->reloc[id].bo);
1445 r600_context_bo_flush(ctx,
1446 block->reloc[id].flush_flags,
1447 block->reloc[id].flush_mask,
1448 block->reloc[id].bo);
1449 }
1450 }
1451 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1452
1453 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1454 ctx->pm4_cdwords += cp_dwords;
1455
1456 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1457 block->nreg_dirty = 0;
1458 LIST_DELINIT(&block->list);
1459 }
1460
1461 void r600_context_flush_dest_caches(struct r600_context *ctx)
1462 {
1463 struct r600_bo *cb[8];
1464 struct r600_bo *db;
1465 int i;
1466
1467 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1468 return;
1469
1470 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1471 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1472 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1473 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1474 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1475 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1476 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1477 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1478 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1479
1480 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1481 /* flush the color buffers */
1482 for (i = 0; i < 8; i++) {
1483 if (!cb[i])
1484 continue;
1485
1486 r600_context_bo_flush(ctx,
1487 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1488 S_0085F0_CB_ACTION_ENA(1),
1489 0, cb[i]);
1490 }
1491 if (db) {
1492 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1493 }
1494 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1495 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1496 }
1497
1498 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1499 {
1500 unsigned ndwords = 7;
1501 struct r600_block *dirty_block = NULL;
1502 struct r600_block *next_block;
1503 uint32_t *pm4;
1504
1505 if (draw->indices) {
1506 ndwords = 11;
1507 /* make sure there is enough relocation space before scheduling draw */
1508 if (ctx->creloc >= (ctx->nreloc - 1)) {
1509 r600_context_flush(ctx);
1510 }
1511 }
1512
1513 /* queries need some special values */
1514 if (ctx->num_query_running) {
1515 if (ctx->radeon->family >= CHIP_RV770) {
1516 r600_context_reg(ctx,
1517 R_028D0C_DB_RENDER_CONTROL,
1518 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1519 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1520 }
1521 r600_context_reg(ctx,
1522 R_028D10_DB_RENDER_OVERRIDE,
1523 S_028D10_NOOP_CULL_DISABLE(1),
1524 S_028D10_NOOP_CULL_DISABLE(1));
1525 }
1526
1527 /* update the max dword count to make sure we have enough space
1528 * reserved for flushing the destination caches */
1529 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1530
1531 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1532 /* need to flush */
1533 r600_context_flush(ctx);
1534 }
1535 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1536 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1537 R600_ERR("context is too big to be scheduled\n");
1538 return;
1539 }
1540 /* enough room to copy packet */
1541 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1542 r600_context_block_emit_dirty(ctx, dirty_block);
1543 }
1544
1545 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1546 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1547 }
1548
1549 /* draw packet */
1550 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1551
1552 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1553 pm4[1] = draw->vgt_index_type;
1554 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1555 pm4[3] = draw->vgt_num_instances;
1556 if (draw->indices) {
1557 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1558 pm4[5] = draw->indices_bo_offset;
1559 pm4[6] = 0;
1560 pm4[7] = draw->vgt_num_indices;
1561 pm4[8] = draw->vgt_draw_initiator;
1562 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1563 pm4[10] = 0;
1564 r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
1565 } else {
1566 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1567 pm4[5] = draw->vgt_num_indices;
1568 pm4[6] = draw->vgt_draw_initiator;
1569 }
1570 ctx->pm4_cdwords += ndwords;
1571
1572 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1573
1574 /* all dirty state have been scheduled in current cs */
1575 ctx->pm4_dirty_cdwords = 0;
1576 }
1577
1578 void r600_context_flush(struct r600_context *ctx)
1579 {
1580 struct drm_radeon_cs drmib = {};
1581 struct drm_radeon_cs_chunk chunks[2];
1582 uint64_t chunk_array[2];
1583 unsigned fence;
1584 int r;
1585 struct r600_block *enable_block = NULL;
1586
1587 if (ctx->pm4_cdwords == ctx->init_dwords)
1588 return;
1589
1590 /* suspend queries */
1591 r600_context_queries_suspend(ctx);
1592
1593 if (ctx->radeon->chip_class >= EVERGREEN)
1594 evergreen_context_flush_dest_caches(ctx);
1595 else
1596 r600_context_flush_dest_caches(ctx);
1597
1598 /* partial flush is needed to avoid lockups on some chips with user fences */
1599 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1600 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1601 /* emit fence */
1602 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1603 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1604 ctx->pm4[ctx->pm4_cdwords++] = 0;
1605 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1606 ctx->pm4[ctx->pm4_cdwords++] = ctx->radeon->fence;
1607 ctx->pm4[ctx->pm4_cdwords++] = 0;
1608 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1609 ctx->pm4[ctx->pm4_cdwords++] = 0;
1610 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->radeon->fence_bo);
1611
1612 #if 1
1613 /* emit cs */
1614 drmib.num_chunks = 2;
1615 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1616 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1617 chunks[0].length_dw = ctx->pm4_cdwords;
1618 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1619 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1620 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1621 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1622 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1623 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1624 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1625 sizeof(struct drm_radeon_cs));
1626 if (r) {
1627 fprintf(stderr, "radeon: The kernel rejected CS, "
1628 "see dmesg for more information.\n");
1629 }
1630 #else
1631 *ctx->radeon->cfence = ctx->radeon->fence;
1632 #endif
1633
1634 r600_context_update_fenced_list(ctx);
1635
1636 fence = ctx->radeon->fence + 1;
1637 if (fence < ctx->radeon->fence) {
1638 /* wrap around */
1639 fence = 1;
1640 r600_context_fence_wraparound(ctx, fence);
1641 }
1642 ctx->radeon->fence = fence;
1643
1644 /* restart */
1645 for (int i = 0; i < ctx->creloc; i++) {
1646 ctx->bo[i]->reloc = NULL;
1647 ctx->bo[i]->last_flush = 0;
1648 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1649 }
1650 ctx->creloc = 0;
1651 ctx->pm4_dirty_cdwords = 0;
1652 ctx->pm4_cdwords = 0;
1653 ctx->flags = 0;
1654
1655 r600_init_cs(ctx);
1656
1657 /* resume queries */
1658 r600_context_queries_resume(ctx, TRUE);
1659
1660 /* set all valid group as dirty so they get reemited on
1661 * next draw command
1662 */
1663 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1664 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1665 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1666 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1667 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1668 }
1669 } else {
1670 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1671 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1672 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1673 }
1674 }
1675 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1676 enable_block->pm4_flush_ndwords;
1677 enable_block->nreg_dirty = enable_block->nreg;
1678 }
1679 }
1680
1681 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1682 {
1683 unsigned ndwords = 10;
1684
1685 if (((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) ||
1686 (ctx->creloc >= (ctx->nreloc - 1))) {
1687 /* need to flush */
1688 r600_context_flush(ctx);
1689 }
1690
1691 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1692 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1693 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1694 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1695 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1696 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1697 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1698 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1699 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1700 ctx->pm4[ctx->pm4_cdwords++] = 0;
1701 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], fence_bo);
1702 }
1703
1704 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1705 {
1706 unsigned results_base = query->results_start;
1707 u64 start, end;
1708 u32 *results, *current_result;
1709
1710 if (wait)
1711 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_READ, NULL);
1712 else
1713 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_DONTBLOCK | PIPE_TRANSFER_READ, NULL);
1714 if (!results)
1715 return FALSE;
1716
1717
1718 /* count all results across all data blocks */
1719 while (results_base != query->results_end) {
1720 current_result = (u32*)((char*)results + results_base);
1721
1722 start = (u64)current_result[0] | (u64)current_result[1] << 32;
1723 end = (u64)current_result[2] | (u64)current_result[3] << 32;
1724 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1725 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1726 query->result += end - start;
1727 }
1728
1729 results_base += 4 * 4;
1730 if (results_base >= query->buffer_size)
1731 results_base = 0;
1732 }
1733
1734 query->results_start = query->results_end;
1735 r600_bo_unmap(ctx->radeon, query->buffer);
1736 return TRUE;
1737 }
1738
1739 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1740 {
1741 unsigned required_space, new_results_end;
1742
1743 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1744 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1745 required_space = 16;
1746 else
1747 required_space = 12;
1748
1749 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1750 /* need to flush */
1751 r600_context_flush(ctx);
1752 }
1753
1754 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1755 /* Count queries emitted without flushes, and flush if more than
1756 * half of buffer used, to avoid overwriting results which may be
1757 * still in use. */
1758 if (query->state & R600_QUERY_STATE_FLUSHED) {
1759 query->queries_emitted = 1;
1760 } else {
1761 if (++query->queries_emitted > query->buffer_size / query->result_size / 2)
1762 r600_context_flush(ctx);
1763 }
1764 }
1765
1766 new_results_end = query->results_end + query->result_size;
1767 if (new_results_end >= query->buffer_size)
1768 new_results_end = 0;
1769
1770 /* collect current results if query buffer is full */
1771 if (new_results_end == query->results_start) {
1772 if (!(query->state & R600_QUERY_STATE_FLUSHED))
1773 r600_context_flush(ctx);
1774 r600_query_result(ctx, query, TRUE);
1775 }
1776
1777 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1778 u32 *results;
1779 int i;
1780
1781 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_WRITE, NULL);
1782 if (results) {
1783 results = (u32*)((char*)results + query->results_end);
1784 memset(results, 0, query->result_size);
1785
1786 /* Set top bits for unused backends */
1787 for (i = 0; i < ctx->max_db; i++) {
1788 if (!(ctx->backend_mask & (1<<i))) {
1789 results[(i * 4)+1] = 0x80000000;
1790 results[(i * 4)+3] = 0x80000000;
1791 }
1792 }
1793 r600_bo_unmap(ctx->radeon, query->buffer);
1794 }
1795 }
1796
1797 /* emit begin query */
1798 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1799 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1800 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1801 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1802 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1803 ctx->pm4[ctx->pm4_cdwords++] = 0;
1804 ctx->pm4[ctx->pm4_cdwords++] = 0;
1805 } else {
1806 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1807 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1808 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1809 ctx->pm4[ctx->pm4_cdwords++] = 0;
1810 }
1811 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1812 ctx->pm4[ctx->pm4_cdwords++] = 0;
1813 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1814
1815 query->state |= R600_QUERY_STATE_STARTED;
1816 query->state ^= R600_QUERY_STATE_ENDED;
1817 ctx->num_query_running++;
1818 }
1819
1820 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1821 {
1822 /* emit end query */
1823 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1824 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1825 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1826 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
1827 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1828 ctx->pm4[ctx->pm4_cdwords++] = 0;
1829 ctx->pm4[ctx->pm4_cdwords++] = 0;
1830 } else {
1831 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1832 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1833 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
1834 ctx->pm4[ctx->pm4_cdwords++] = 0;
1835 }
1836 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1837 ctx->pm4[ctx->pm4_cdwords++] = 0;
1838 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1839
1840 query->results_end += query->result_size;
1841 if (query->results_end >= query->buffer_size)
1842 query->results_end = 0;
1843
1844 query->state ^= R600_QUERY_STATE_STARTED;
1845 query->state |= R600_QUERY_STATE_ENDED;
1846 query->state &= ~R600_QUERY_STATE_FLUSHED;
1847
1848 ctx->num_query_running--;
1849 }
1850
1851 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1852 int flag_wait)
1853 {
1854 if (operation == PREDICATION_OP_CLEAR) {
1855 if (ctx->pm4_cdwords + 3 > ctx->pm4_ndwords)
1856 r600_context_flush(ctx);
1857
1858 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1859 ctx->pm4[ctx->pm4_cdwords++] = 0;
1860 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1861 } else {
1862 unsigned results_base = query->results_start;
1863 unsigned count;
1864 u32 op;
1865
1866 /* find count of the query data blocks */
1867 count = query->buffer_size + query->results_end - query->results_start;
1868 if (count >= query->buffer_size) count-=query->buffer_size;
1869 count /= query->result_size;
1870
1871 if (ctx->pm4_cdwords + 5 * count > ctx->pm4_ndwords)
1872 r600_context_flush(ctx);
1873
1874 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
1875 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
1876
1877 /* emit predicate packets for all data blocks */
1878 while (results_base != query->results_end) {
1879 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1880 ctx->pm4[ctx->pm4_cdwords++] = results_base;
1881 ctx->pm4[ctx->pm4_cdwords++] = op;
1882 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1883 ctx->pm4[ctx->pm4_cdwords++] = 0;
1884 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1885 results_base += query->result_size;
1886 if (results_base >= query->buffer_size)
1887 results_base = 0;
1888 /* set CONTINUE bit for all packets except the first */
1889 op |= PREDICATION_CONTINUE;
1890 }
1891 }
1892 }
1893
1894 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1895 {
1896 struct r600_query *query;
1897
1898 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1899 return NULL;
1900
1901 query = calloc(1, sizeof(struct r600_query));
1902 if (query == NULL)
1903 return NULL;
1904
1905 query->type = query_type;
1906 query->buffer_size = 4096;
1907
1908 if (query_type == PIPE_QUERY_OCCLUSION_COUNTER)
1909 query->result_size = 4 * 4 * ctx->max_db;
1910 else
1911 query->result_size = 4 * 4;
1912
1913 /* adjust buffer size to simplify offsets wrapping math */
1914 query->buffer_size -= query->buffer_size % query->result_size;
1915
1916 /* As of GL4, query buffers are normally read by the CPU after
1917 * being written by the gpu, hence staging is probably a good
1918 * usage pattern.
1919 */
1920 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1921 PIPE_USAGE_STAGING);
1922 if (!query->buffer) {
1923 free(query);
1924 return NULL;
1925 }
1926
1927 LIST_ADDTAIL(&query->list, &ctx->query_list);
1928
1929 return query;
1930 }
1931
1932 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1933 {
1934 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1935 LIST_DELINIT(&query->list);
1936 free(query);
1937 }
1938
1939 boolean r600_context_query_result(struct r600_context *ctx,
1940 struct r600_query *query,
1941 boolean wait, void *vresult)
1942 {
1943 uint64_t *result = (uint64_t*)vresult;
1944
1945 if (!(query->state & R600_QUERY_STATE_FLUSHED)) {
1946 r600_context_flush(ctx);
1947 }
1948 if (!r600_query_result(ctx, query, wait))
1949 return FALSE;
1950 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1951 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1952 else
1953 *result = query->result;
1954 query->result = 0;
1955 return TRUE;
1956 }
1957
1958 void r600_context_queries_suspend(struct r600_context *ctx)
1959 {
1960 struct r600_query *query;
1961
1962 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1963 if (query->state & R600_QUERY_STATE_STARTED) {
1964 r600_query_end(ctx, query);
1965 query->state |= R600_QUERY_STATE_SUSPENDED;
1966 }
1967 }
1968 }
1969
1970 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed)
1971 {
1972 struct r600_query *query;
1973
1974 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1975 if (flushed)
1976 query->state |= R600_QUERY_STATE_FLUSHED;
1977
1978 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1979 r600_query_begin(ctx, query);
1980 query->state ^= R600_QUERY_STATE_SUSPENDED;
1981 }
1982 }
1983 }