2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "radeon_drm.h"
36 #include "pipe/p_compiler.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include <pipebuffer/pb_bufmgr.h>
40 #include "r600_priv.h"
42 #define GROUP_FORCE_NEW_BLOCK 0
44 int r600_context_add_block(struct r600_context
*ctx
, const struct r600_reg
*reg
, unsigned nreg
)
46 struct r600_block
*block
;
47 struct r600_range
*range
;
50 for (unsigned i
= 0, n
= 0; i
< nreg
; i
+= n
) {
53 /* ignore new block balise */
54 if (reg
[i
].offset
== GROUP_FORCE_NEW_BLOCK
) {
59 /* register that need relocation are in their own group */
60 /* find number of consecutive registers */
62 offset
= reg
[i
].offset
;
63 while (reg
[i
+ n
].offset
== offset
) {
68 if (n
>= (R600_BLOCK_MAX_REG
- 2))
72 /* allocate new block */
73 block
= calloc(1, sizeof(struct r600_block
));
78 for (int j
= 0; j
< n
; j
++) {
79 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, reg
[i
+ j
].offset
)];
80 range
->blocks
[CTX_BLOCK_ID(ctx
, reg
[i
+ j
].offset
)] = block
;
83 /* initialize block */
84 block
->start_offset
= reg
[i
].offset
;
85 block
->pm4
[block
->pm4_ndwords
++] = PKT3(reg
[i
].opcode
, n
);
86 block
->pm4
[block
->pm4_ndwords
++] = (block
->start_offset
- reg
[i
].offset_base
) >> 2;
87 block
->reg
= &block
->pm4
[block
->pm4_ndwords
];
88 block
->pm4_ndwords
+= n
;
90 for (j
= 0; j
< n
; j
++) {
91 if (reg
[i
+j
].need_bo
) {
93 assert(block
->nbo
< R600_BLOCK_MAX_BO
);
94 block
->pm4_bo_index
[j
] = block
->nbo
;
95 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_NOP
, 0);
96 block
->pm4
[block
->pm4_ndwords
++] = 0x00000000;
97 block
->reloc
[block
->nbo
].bo_pm4_index
[block
->reloc
[block
->nbo
].nreloc
++] = block
->pm4_ndwords
- 1;
100 for (j
= 0; j
< n
; j
++) {
101 if (reg
[i
+j
].flush_flags
) {
104 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3);
105 block
->pm4
[block
->pm4_ndwords
++] = reg
[i
+j
].flush_flags
;
106 block
->pm4
[block
->pm4_ndwords
++] = 0xFFFFFFFF;
107 block
->pm4
[block
->pm4_ndwords
++] = 0x00000000;
108 block
->pm4
[block
->pm4_ndwords
++] = 0x0000000A;
109 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_NOP
, 0);
110 block
->pm4
[block
->pm4_ndwords
++] = 0x00000000;
111 id
= block
->pm4_bo_index
[j
];
112 block
->reloc
[id
].bo_pm4_index
[block
->reloc
[id
].nreloc
++] = block
->pm4_ndwords
- 1;
115 /* check that we stay in limit */
116 assert(block
->pm4_ndwords
< R600_BLOCK_MAX_REG
);
121 /* R600/R700 configuration */
122 static const struct r600_reg r600_config_reg_list
[] = {
123 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008958_VGT_PRIMITIVE_TYPE
, 0, 0},
124 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C00_SQ_CONFIG
, 0, 0},
125 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, 0, 0},
126 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 0, 0},
127 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C0C_SQ_THREAD_RESOURCE_MGMT
, 0, 0},
128 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C10_SQ_STACK_RESOURCE_MGMT_1
, 0, 0},
129 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008C14_SQ_STACK_RESOURCE_MGMT_2
, 0, 0},
130 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0, 0},
131 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_009508_TA_CNTL_AUX
, 0, 0},
132 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_009714_VC_ENHANCE
, 0, 0},
133 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_009830_DB_DEBUG
, 0, 0},
134 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_009838_DB_WATERMARKS
, 0, 0},
137 static const struct r600_reg r600_ctl_const_list
[] = {
138 {PKT3_SET_CTL_CONST
, R600_CTL_CONST_OFFSET
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0, 0},
139 {PKT3_SET_CTL_CONST
, R600_CTL_CONST_OFFSET
, R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0},
142 static const struct r600_reg r600_context_reg_list
[] = {
143 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028350_SX_MISC
, 0, 0},
144 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286C8_SPI_THREAD_GROUPING
, 0, 0},
145 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0, 0},
146 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0, 0},
147 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0, 0},
148 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0, 0},
149 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0, 0},
150 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0, 0},
151 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0, 0},
152 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0, 0},
153 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0, 0},
154 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0, 0},
155 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A14_VGT_HOS_CNTL
, 0, 0},
156 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0, 0},
157 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0, 0},
158 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0, 0},
159 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0, 0},
160 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A28_VGT_GROUP_FIRST_DECR
, 0, 0},
161 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A2C_VGT_GROUP_DECR
, 0, 0},
162 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0, 0},
163 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0, 0},
164 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0, 0},
165 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0, 0},
166 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A40_VGT_GS_MODE
, 0, 0},
167 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A4C_PA_SC_MODE_CNTL
, 0, 0},
168 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028AB0_VGT_STRMOUT_EN
, 0, 0},
169 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028AB4_VGT_REUSE_OFF
, 0, 0},
170 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028AB8_VGT_VTX_CNT_EN
, 0, 0},
171 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0, 0},
172 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028028_DB_STENCIL_CLEAR
, 0, 0},
173 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02802C_DB_DEPTH_CLEAR
, 0, 0},
174 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
175 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028040_CB_COLOR0_BASE
, 1, 0},
176 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
177 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280A0_CB_COLOR0_INFO
, 1, 0},
178 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028060_CB_COLOR0_SIZE
, 0, 0},
179 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028080_CB_COLOR0_VIEW
, 0, 0},
180 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
181 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280E0_CB_COLOR0_FRAG
, 1, 0},
182 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
183 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280C0_CB_COLOR0_TILE
, 1, 0},
184 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028100_CB_COLOR0_MASK
, 0, 0},
185 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
186 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028044_CB_COLOR1_BASE
, 1, 0},
187 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
188 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280A4_CB_COLOR1_INFO
, 1, 0},
189 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028064_CB_COLOR1_SIZE
, 0, 0},
190 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028084_CB_COLOR1_VIEW
, 0, 0},
191 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
192 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280E4_CB_COLOR1_FRAG
, 1, 0},
193 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
194 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280C4_CB_COLOR1_TILE
, 1, 0},
195 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028104_CB_COLOR1_MASK
, 0, 0},
196 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
197 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028048_CB_COLOR2_BASE
, 1, 0},
198 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
199 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280A8_CB_COLOR2_INFO
, 1, 0},
200 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028068_CB_COLOR2_SIZE
, 0, 0},
201 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028088_CB_COLOR2_VIEW
, 0, 0},
202 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
203 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280E8_CB_COLOR2_FRAG
, 1, 0},
204 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
205 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280C8_CB_COLOR2_TILE
, 1, 0},
206 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028108_CB_COLOR2_MASK
, 0, 0},
207 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
208 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02804C_CB_COLOR3_BASE
, 1, 0},
209 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
210 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280AC_CB_COLOR3_INFO
, 1, 0},
211 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02806C_CB_COLOR3_SIZE
, 0, 0},
212 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02808C_CB_COLOR3_VIEW
, 0, 0},
213 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
214 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280EC_CB_COLOR3_FRAG
, 1, 0},
215 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
216 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280CC_CB_COLOR3_TILE
, 1, 0},
217 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02810C_CB_COLOR3_MASK
, 0, 0},
218 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
219 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028050_CB_COLOR4_BASE
, 1, 0},
220 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
221 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280B0_CB_COLOR4_INFO
, 1, 0},
222 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028070_CB_COLOR4_SIZE
, 0, 0},
223 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028090_CB_COLOR4_VIEW
, 0, 0},
224 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
225 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280F0_CB_COLOR4_FRAG
, 1, 0},
226 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
227 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280D0_CB_COLOR4_TILE
, 1, 0},
228 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028110_CB_COLOR4_MASK
, 0, 0},
229 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
230 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028054_CB_COLOR5_BASE
, 1, 0},
231 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
232 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280B4_CB_COLOR5_INFO
, 1, 0},
233 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028074_CB_COLOR5_SIZE
, 0, 0},
234 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028094_CB_COLOR5_VIEW
, 0, 0},
235 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
236 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280F4_CB_COLOR5_FRAG
, 1, 0},
237 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
238 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280D4_CB_COLOR5_TILE
, 1, 0},
239 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028114_CB_COLOR5_MASK
, 0, 0},
240 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028058_CB_COLOR6_BASE
, 1, 0},
241 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280B8_CB_COLOR6_INFO
, 1, 0},
242 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028078_CB_COLOR6_SIZE
, 0, 0},
243 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028098_CB_COLOR6_VIEW
, 0, 0},
244 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
245 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280F8_CB_COLOR6_FRAG
, 1, 0},
246 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
247 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280D8_CB_COLOR6_TILE
, 1, 0},
248 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028118_CB_COLOR6_MASK
, 0, 0},
249 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
250 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02805C_CB_COLOR7_BASE
, 1, 0},
251 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
252 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280BC_CB_COLOR7_INFO
, 1, 0},
253 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02807C_CB_COLOR7_SIZE
, 0, 0},
254 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02809C_CB_COLOR7_VIEW
, 0, 0},
255 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280FC_CB_COLOR7_FRAG
, 1, 0},
256 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0280DC_CB_COLOR7_TILE
, 1, 0},
257 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02811C_CB_COLOR7_MASK
, 0, 0},
258 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028120_CB_CLEAR_RED
, 0, 0},
259 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028124_CB_CLEAR_GREEN
, 0, 0},
260 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028128_CB_CLEAR_BLUE
, 0, 0},
261 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02812C_CB_CLEAR_ALPHA
, 0, 0},
262 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 0, 0},
263 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 0, 0},
264 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028940_ALU_CONST_CACHE_PS_0
, 1, S_0085F0_SH_ACTION_ENA(1)},
265 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028980_ALU_CONST_CACHE_VS_0
, 1, S_0085F0_SH_ACTION_ENA(1)},
266 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02823C_CB_SHADER_MASK
, 0, 0},
267 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028238_CB_TARGET_MASK
, 0, 0},
268 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028410_SX_ALPHA_TEST_CONTROL
, 0, 0},
269 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028414_CB_BLEND_RED
, 0, 0},
270 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028418_CB_BLEND_GREEN
, 0, 0},
271 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02841C_CB_BLEND_BLUE
, 0, 0},
272 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028420_CB_BLEND_ALPHA
, 0, 0},
273 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028424_CB_FOG_RED
, 0, 0},
274 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028428_CB_FOG_GREEN
, 0, 0},
275 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02842C_CB_FOG_BLUE
, 0, 0},
276 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028430_DB_STENCILREFMASK
, 0, 0},
277 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028434_DB_STENCILREFMASK_BF
, 0, 0},
278 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028438_SX_ALPHA_REF
, 0, 0},
279 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286DC_SPI_FOG_CNTL
, 0, 0},
280 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286E0_SPI_FOG_FUNC_SCALE
, 0, 0},
281 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286E4_SPI_FOG_FUNC_BIAS
, 0, 0},
282 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028780_CB_BLEND0_CONTROL
, 0, 0},
283 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028784_CB_BLEND1_CONTROL
, 0, 0},
284 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028788_CB_BLEND2_CONTROL
, 0, 0},
285 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02878C_CB_BLEND3_CONTROL
, 0, 0},
286 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028790_CB_BLEND4_CONTROL
, 0, 0},
287 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028794_CB_BLEND5_CONTROL
, 0, 0},
288 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028798_CB_BLEND6_CONTROL
, 0, 0},
289 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02879C_CB_BLEND7_CONTROL
, 0, 0},
290 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0287A0_CB_SHADER_CONTROL
, 0, 0},
291 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028800_DB_DEPTH_CONTROL
, 0, 0},
292 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028804_CB_BLEND_CONTROL
, 0, 0},
293 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028808_CB_COLOR_CONTROL
, 0, 0},
294 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02880C_DB_SHADER_CONTROL
, 0, 0},
295 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C04_PA_SC_AA_CONFIG
, 0, 0},
296 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 0, 0},
297 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
, 0, 0},
298 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C30_CB_CLRCMP_CONTROL
, 0, 0},
299 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C34_CB_CLRCMP_SRC
, 0, 0},
300 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C38_CB_CLRCMP_DST
, 0, 0},
301 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C3C_CB_CLRCMP_MSK
, 0, 0},
302 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C48_PA_SC_AA_MASK
, 0, 0},
303 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0, 0},
304 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D44_DB_ALPHA_TO_MASK
, 0, 0},
305 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02800C_DB_DEPTH_BASE
, 1, 0},
306 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028000_DB_DEPTH_SIZE
, 0, 0},
307 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028004_DB_DEPTH_VIEW
, 0, 0},
308 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
309 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028010_DB_DEPTH_INFO
, 1, 0},
310 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D0C_DB_RENDER_CONTROL
, 0, 0},
311 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D10_DB_RENDER_OVERRIDE
, 0, 0},
312 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D24_DB_HTILE_SURFACE
, 0, 0},
313 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D30_DB_PRELOAD_CONTROL
, 0, 0},
314 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028D34_DB_PREFETCH_LIMIT
, 0, 0},
315 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0, 0},
316 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028034_PA_SC_SCREEN_SCISSOR_BR
, 0, 0},
317 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028200_PA_SC_WINDOW_OFFSET
, 0, 0},
318 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0},
319 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0},
320 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02820C_PA_SC_CLIPRECT_RULE
, 0, 0},
321 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028210_PA_SC_CLIPRECT_0_TL
, 0, 0},
322 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028214_PA_SC_CLIPRECT_0_BR
, 0, 0},
323 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028218_PA_SC_CLIPRECT_1_TL
, 0, 0},
324 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02821C_PA_SC_CLIPRECT_1_BR
, 0, 0},
325 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028220_PA_SC_CLIPRECT_2_TL
, 0, 0},
326 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028224_PA_SC_CLIPRECT_2_BR
, 0, 0},
327 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028228_PA_SC_CLIPRECT_3_TL
, 0, 0},
328 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02822C_PA_SC_CLIPRECT_3_BR
, 0, 0},
329 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028230_PA_SC_EDGERULE
, 0, 0},
330 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 0, 0},
331 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028244_PA_SC_GENERIC_SCISSOR_BR
, 0, 0},
332 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0},
333 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0},
334 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0, 0},
335 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0, 0},
336 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02843C_PA_CL_VPORT_XSCALE_0
, 0, 0},
337 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028440_PA_CL_VPORT_XOFFSET_0
, 0, 0},
338 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028444_PA_CL_VPORT_YSCALE_0
, 0, 0},
339 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028448_PA_CL_VPORT_YOFFSET_0
, 0, 0},
340 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02844C_PA_CL_VPORT_ZSCALE_0
, 0, 0},
341 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028450_PA_CL_VPORT_ZOFFSET_0
, 0, 0},
342 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0},
343 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028810_PA_CL_CLIP_CNTL
, 0, 0},
344 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028814_PA_SU_SC_MODE_CNTL
, 0, 0},
345 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028818_PA_CL_VTE_CNTL
, 0, 0},
346 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02881C_PA_CL_VS_OUT_CNTL
, 0, 0},
347 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028820_PA_CL_NANINF_CNTL
, 0, 0},
348 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A00_PA_SU_POINT_SIZE
, 0, 0},
349 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A04_PA_SU_POINT_MINMAX
, 0, 0},
350 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A08_PA_SU_LINE_CNTL
, 0, 0},
351 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A0C_PA_SC_LINE_STIPPLE
, 0, 0},
352 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0, 0},
353 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C00_PA_SC_LINE_CNTL
, 0, 0},
354 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0, 0},
355 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0, 0},
356 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0, 0},
357 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0, 0},
358 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0},
359 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0, 0},
360 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0},
361 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0},
362 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0},
363 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0},
364 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E20_PA_CL_UCP0_X
, 0, 0},
365 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E24_PA_CL_UCP0_Y
, 0, 0},
366 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E28_PA_CL_UCP0_Z
, 0, 0},
367 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E2C_PA_CL_UCP0_W
, 0, 0},
368 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E30_PA_CL_UCP1_X
, 0, 0},
369 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E34_PA_CL_UCP1_Y
, 0, 0},
370 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E38_PA_CL_UCP1_Z
, 0, 0},
371 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E3C_PA_CL_UCP1_W
, 0, 0},
372 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E40_PA_CL_UCP2_X
, 0, 0},
373 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E44_PA_CL_UCP2_Y
, 0, 0},
374 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E48_PA_CL_UCP2_Z
, 0, 0},
375 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E4C_PA_CL_UCP2_W
, 0, 0},
376 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E50_PA_CL_UCP3_X
, 0, 0},
377 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E54_PA_CL_UCP3_Y
, 0, 0},
378 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E58_PA_CL_UCP3_Z
, 0, 0},
379 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E5C_PA_CL_UCP3_W
, 0, 0},
380 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E60_PA_CL_UCP4_X
, 0, 0},
381 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E64_PA_CL_UCP4_Y
, 0, 0},
382 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E68_PA_CL_UCP4_Z
, 0, 0},
383 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E6C_PA_CL_UCP4_W
, 0, 0},
384 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E70_PA_CL_UCP5_X
, 0, 0},
385 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E74_PA_CL_UCP5_Y
, 0, 0},
386 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E78_PA_CL_UCP5_Z
, 0, 0},
387 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028E7C_PA_CL_UCP5_W
, 0, 0},
388 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028380_SQ_VTX_SEMANTIC_0
, 0, 0},
389 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028384_SQ_VTX_SEMANTIC_1
, 0, 0},
390 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028388_SQ_VTX_SEMANTIC_2
, 0, 0},
391 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02838C_SQ_VTX_SEMANTIC_3
, 0, 0},
392 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028390_SQ_VTX_SEMANTIC_4
, 0, 0},
393 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028394_SQ_VTX_SEMANTIC_5
, 0, 0},
394 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028398_SQ_VTX_SEMANTIC_6
, 0, 0},
395 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02839C_SQ_VTX_SEMANTIC_7
, 0, 0},
396 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283A0_SQ_VTX_SEMANTIC_8
, 0, 0},
397 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283A4_SQ_VTX_SEMANTIC_9
, 0, 0},
398 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283A8_SQ_VTX_SEMANTIC_10
, 0, 0},
399 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283AC_SQ_VTX_SEMANTIC_11
, 0, 0},
400 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283B0_SQ_VTX_SEMANTIC_12
, 0, 0},
401 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283B4_SQ_VTX_SEMANTIC_13
, 0, 0},
402 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283B8_SQ_VTX_SEMANTIC_14
, 0, 0},
403 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283BC_SQ_VTX_SEMANTIC_15
, 0, 0},
404 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283C0_SQ_VTX_SEMANTIC_16
, 0, 0},
405 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283C4_SQ_VTX_SEMANTIC_17
, 0, 0},
406 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283C8_SQ_VTX_SEMANTIC_18
, 0, 0},
407 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283CC_SQ_VTX_SEMANTIC_19
, 0, 0},
408 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283D0_SQ_VTX_SEMANTIC_20
, 0, 0},
409 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283D4_SQ_VTX_SEMANTIC_21
, 0, 0},
410 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283D8_SQ_VTX_SEMANTIC_22
, 0, 0},
411 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283DC_SQ_VTX_SEMANTIC_23
, 0, 0},
412 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283E0_SQ_VTX_SEMANTIC_24
, 0, 0},
413 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283E4_SQ_VTX_SEMANTIC_25
, 0, 0},
414 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283E8_SQ_VTX_SEMANTIC_26
, 0, 0},
415 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283EC_SQ_VTX_SEMANTIC_27
, 0, 0},
416 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283F0_SQ_VTX_SEMANTIC_28
, 0, 0},
417 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283F4_SQ_VTX_SEMANTIC_29
, 0, 0},
418 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283F8_SQ_VTX_SEMANTIC_30
, 0, 0},
419 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0283FC_SQ_VTX_SEMANTIC_31
, 0, 0},
420 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028614_SPI_VS_OUT_ID_0
, 0, 0},
421 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028618_SPI_VS_OUT_ID_1
, 0, 0},
422 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02861C_SPI_VS_OUT_ID_2
, 0, 0},
423 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028620_SPI_VS_OUT_ID_3
, 0, 0},
424 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028624_SPI_VS_OUT_ID_4
, 0, 0},
425 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028628_SPI_VS_OUT_ID_5
, 0, 0},
426 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02862C_SPI_VS_OUT_ID_6
, 0, 0},
427 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028630_SPI_VS_OUT_ID_7
, 0, 0},
428 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028634_SPI_VS_OUT_ID_8
, 0, 0},
429 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028638_SPI_VS_OUT_ID_9
, 0, 0},
430 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0},
431 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
432 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028858_SQ_PGM_START_VS
, 1, S_0085F0_SH_ACTION_ENA(1)},
433 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
434 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028868_SQ_PGM_RESOURCES_VS
, 0, 0},
435 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
436 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028894_SQ_PGM_START_FS
, 1, S_0085F0_SH_ACTION_ENA(1)},
437 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
438 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0, 0},
439 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288D0_SQ_PGM_CF_OFFSET_VS
, 0, 0},
440 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0, 0},
441 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0},
442 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0},
443 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0},
444 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0},
445 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0},
446 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0},
447 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0},
448 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0},
449 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0},
450 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0},
451 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0},
452 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0},
453 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0},
454 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0},
455 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0},
456 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0},
457 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0},
458 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0},
459 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0},
460 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0},
461 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0},
462 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0},
463 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0},
464 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0},
465 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0},
466 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0},
467 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0},
468 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0},
469 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0},
470 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0},
471 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0},
472 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0},
473 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0},
474 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0},
475 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0286D8_SPI_INPUT_Z
, 0, 0},
476 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
477 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028840_SQ_PGM_START_PS
, 1, S_0085F0_SH_ACTION_ENA(1)},
478 {0, 0, GROUP_FORCE_NEW_BLOCK
, 0, 0},
479 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028850_SQ_PGM_RESOURCES_PS
, 0, 0},
480 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028854_SQ_PGM_EXPORTS_PS
, 0, 0},
481 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 0, 0},
482 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028400_VGT_MAX_VTX_INDX
, 0, 0},
483 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028404_VGT_MIN_VTX_INDX
, 0, 0},
484 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028408_VGT_INDX_OFFSET
, 0, 0},
485 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0},
486 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A84_VGT_PRIMITIVEID_EN
, 0, 0},
487 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0, 0},
488 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0, 0},
489 {PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0, 0},
492 /* SHADER RESOURCE R600/R700 */
493 static int r600_state_resource_init(struct r600_context
*ctx
, u32 offset
)
495 struct r600_reg r600_shader_resource
[] = {
496 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038000_RESOURCE0_WORD0
, 0, 0},
497 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038004_RESOURCE0_WORD1
, 0, 0},
498 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038008_RESOURCE0_WORD2
, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
499 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_03800C_RESOURCE0_WORD3
, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
500 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038010_RESOURCE0_WORD4
, 0, 0},
501 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038014_RESOURCE0_WORD5
, 0, 0},
502 {PKT3_SET_RESOURCE
, R600_RESOURCE_OFFSET
, R_038018_RESOURCE0_WORD6
, 0, 0},
504 unsigned nreg
= Elements(r600_shader_resource
);
506 for (int i
= 0; i
< nreg
; i
++) {
507 r600_shader_resource
[i
].offset
+= offset
;
509 return r600_context_add_block(ctx
, r600_shader_resource
, nreg
);
512 /* SHADER SAMPLER R600/R700 */
513 static int r600_state_sampler_init(struct r600_context
*ctx
, u32 offset
)
515 struct r600_reg r600_shader_sampler
[] = {
516 {PKT3_SET_SAMPLER
, R600_SAMPLER_OFFSET
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
, 0, 0},
517 {PKT3_SET_SAMPLER
, R600_SAMPLER_OFFSET
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
, 0, 0},
518 {PKT3_SET_SAMPLER
, R600_SAMPLER_OFFSET
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, 0, 0},
520 unsigned nreg
= Elements(r600_shader_sampler
);
522 for (int i
= 0; i
< nreg
; i
++) {
523 r600_shader_sampler
[i
].offset
+= offset
;
525 return r600_context_add_block(ctx
, r600_shader_sampler
, nreg
);
528 /* SHADER SAMPLER BORDER R600/R700 */
529 static int r600_state_sampler_border_init(struct r600_context
*ctx
, u32 offset
)
531 struct r600_reg r600_shader_sampler_border
[] = {
532 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, 0, 0},
533 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, 0, 0},
534 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, 0, 0},
535 {PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, 0, 0},
537 unsigned nreg
= Elements(r600_shader_sampler_border
);
539 for (int i
= 0; i
< nreg
; i
++) {
540 r600_shader_sampler_border
[i
].offset
+= offset
;
542 return r600_context_add_block(ctx
, r600_shader_sampler_border
, nreg
);
546 void r600_context_fini(struct r600_context
*ctx
)
548 struct r600_block
*block
;
549 struct r600_range
*range
;
551 for (int i
= 0; i
< 256; i
++) {
552 for (int j
= 0; j
< (1 << ctx
->hash_shift
); j
++) {
553 block
= ctx
->range
[i
].blocks
[j
];
555 for (int k
= 0, offset
= block
->start_offset
; k
< block
->nreg
; k
++, offset
+= 4) {
556 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
557 range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)] = NULL
;
562 free(ctx
->range
[i
].blocks
);
566 memset(ctx
, 0, sizeof(struct r600_context
));
569 int r600_context_init(struct r600_context
*ctx
, struct radeon
*radeon
)
573 memset(ctx
, 0, sizeof(struct r600_context
));
574 radeon
->use_mem_constant
= TRUE
;
575 ctx
->radeon
= radeon
;
576 LIST_INITHEAD(&ctx
->query_list
);
578 /* initialize hash */
580 ctx
->hash_shift
= 11;
581 for (int i
= 0; i
< 256; i
++) {
582 ctx
->range
[i
].start_offset
= i
<< ctx
->hash_shift
;
583 ctx
->range
[i
].end_offset
= ((i
+ 1) << ctx
->hash_shift
) - 1;
584 ctx
->range
[i
].blocks
= calloc(1 << ctx
->hash_shift
, sizeof(void*));
585 if (ctx
->range
[i
].blocks
== NULL
) {
591 r
= r600_context_add_block(ctx
, r600_config_reg_list
,
592 Elements(r600_config_reg_list
));
595 r
= r600_context_add_block(ctx
, r600_context_reg_list
,
596 Elements(r600_context_reg_list
));
599 r
= r600_context_add_block(ctx
, r600_ctl_const_list
,
600 Elements(r600_ctl_const_list
));
604 /* PS SAMPLER BORDER */
605 for (int j
= 0, offset
= 0; j
< 18; j
++, offset
+= 0x10) {
606 r
= r600_state_sampler_border_init(ctx
, offset
);
611 /* VS SAMPLER BORDER */
612 for (int j
= 0, offset
= 0x200; j
< 18; j
++, offset
+= 0x10) {
613 r
= r600_state_sampler_border_init(ctx
, offset
);
618 for (int j
= 0, offset
= 0; j
< 18; j
++, offset
+= 0xC) {
619 r
= r600_state_sampler_init(ctx
, offset
);
624 for (int j
= 0, offset
= 0xD8; j
< 18; j
++, offset
+= 0xC) {
625 r
= r600_state_sampler_init(ctx
, offset
);
630 for (int j
= 0, offset
= 0; j
< 160; j
++, offset
+= 0x1C) {
631 r
= r600_state_resource_init(ctx
, offset
);
636 for (int j
= 0, offset
= 0x1180; j
< 160; j
++, offset
+= 0x1C) {
637 r
= r600_state_resource_init(ctx
, offset
);
642 /* setup block table */
643 ctx
->blocks
= calloc(ctx
->nblocks
, sizeof(void*));
644 for (int i
= 0, c
= 0; i
< 256; i
++) {
645 for (int j
= 0, add
; j
< (1 << ctx
->hash_shift
); j
++) {
646 if (ctx
->range
[i
].blocks
[j
]) {
648 for (int k
= 0; k
< c
; k
++) {
649 if (ctx
->blocks
[k
] == ctx
->range
[i
].blocks
[j
]) {
655 assert(c
< ctx
->nblocks
);
656 ctx
->blocks
[c
++] = ctx
->range
[i
].blocks
[j
];
657 j
+= (ctx
->range
[i
].blocks
[j
]->nreg
<< 2) - 1;
663 /* allocate cs variables */
664 ctx
->nreloc
= RADEON_CTX_MAX_PM4
;
665 ctx
->reloc
= calloc(ctx
->nreloc
, sizeof(struct r600_reloc
));
666 if (ctx
->reloc
== NULL
) {
670 ctx
->bo
= calloc(ctx
->nreloc
, sizeof(void *));
671 if (ctx
->bo
== NULL
) {
675 ctx
->pm4_ndwords
= RADEON_CTX_MAX_PM4
;
676 ctx
->pm4
= calloc(ctx
->pm4_ndwords
, 4);
677 if (ctx
->pm4
== NULL
) {
683 r600_context_fini(ctx
);
687 void r600_context_bo_reloc(struct r600_context
*ctx
, u32
*pm4
, struct radeon_bo
*bo
)
692 for (i
= 0, reloc_id
= -1; i
< ctx
->creloc
; i
++) {
693 if (ctx
->reloc
[i
].handle
== bo
->handle
) {
694 reloc_id
= i
* sizeof(struct r600_reloc
) / 4;
695 /* set PKT3 to point to proper reloc */
699 if (reloc_id
== -1) {
700 /* add new relocation */
701 if (ctx
->creloc
>= ctx
->nreloc
) {
702 r600_context_flush(ctx
);
704 reloc_id
= ctx
->creloc
* sizeof(struct r600_reloc
) / 4;
705 ctx
->reloc
[ctx
->creloc
].handle
= bo
->handle
;
706 ctx
->reloc
[ctx
->creloc
].read_domain
= RADEON_GEM_DOMAIN_GTT
;
707 ctx
->reloc
[ctx
->creloc
].write_domain
= RADEON_GEM_DOMAIN_GTT
;
708 ctx
->reloc
[ctx
->creloc
].flags
= 0;
709 radeon_bo_reference(ctx
->radeon
, &ctx
->bo
[ctx
->creloc
], bo
);
711 /* set PKT3 to point to proper reloc */
716 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
)
718 struct r600_range
*range
;
719 struct r600_block
*block
;
721 for (int i
= 0; i
< state
->nregs
; i
++) {
724 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, state
->regs
[i
].offset
)];
725 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, state
->regs
[i
].offset
)];
726 id
= (state
->regs
[i
].offset
- block
->start_offset
) >> 2;
727 block
->reg
[id
] &= ~state
->regs
[i
].mask
;
728 block
->reg
[id
] |= state
->regs
[i
].value
;
729 if (block
->pm4_bo_index
[id
]) {
730 /* find relocation */
731 id
= block
->pm4_bo_index
[id
];
732 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[id
].bo
, state
->regs
[i
].bo
);
734 if (!(block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
735 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
736 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
737 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
;
742 static inline void r600_context_pipe_state_set_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
744 struct r600_range
*range
;
745 struct r600_block
*block
;
747 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
748 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)];
750 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
751 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[1].bo
, NULL
);
752 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[2].bo
, NULL
);
755 block
->reg
[0] = state
->regs
[0].value
;
756 block
->reg
[1] = state
->regs
[1].value
;
757 block
->reg
[2] = state
->regs
[2].value
;
758 block
->reg
[3] = state
->regs
[3].value
;
759 block
->reg
[4] = state
->regs
[4].value
;
760 block
->reg
[5] = state
->regs
[5].value
;
761 block
->reg
[6] = state
->regs
[6].value
;
762 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[1].bo
, NULL
);
763 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[2].bo
, NULL
);
764 if (state
->regs
[0].bo
) {
765 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
766 * we have single case btw VERTEX & TEXTURE resource
768 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[1].bo
, state
->regs
[0].bo
);
769 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[2].bo
, state
->regs
[0].bo
);
771 /* TEXTURE RESOURCE */
772 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[1].bo
, state
->regs
[2].bo
);
773 radeon_ws_bo_reference(ctx
->radeon
, &block
->reloc
[2].bo
, state
->regs
[3].bo
);
775 if (!(block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
776 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
777 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
778 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
;
782 void r600_context_pipe_state_set_ps_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned rid
)
784 unsigned offset
= R_038000_SQ_TEX_RESOURCE_WORD0_0
+ 0x1C * rid
;
786 r600_context_pipe_state_set_resource(ctx
, state
, offset
);
789 void r600_context_pipe_state_set_vs_resource(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned rid
)
791 unsigned offset
= R_038000_SQ_TEX_RESOURCE_WORD0_0
+ 0x1180 + 0x1C * rid
;
793 r600_context_pipe_state_set_resource(ctx
, state
, offset
);
796 static inline void r600_context_pipe_state_set_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
798 struct r600_range
*range
;
799 struct r600_block
*block
;
801 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
802 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)];
804 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
807 block
->reg
[0] = state
->regs
[0].value
;
808 block
->reg
[1] = state
->regs
[1].value
;
809 block
->reg
[2] = state
->regs
[2].value
;
810 if (!(block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
811 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
812 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
813 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
;
817 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned offset
)
819 struct r600_range
*range
;
820 struct r600_block
*block
;
822 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
823 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)];
825 block
->status
&= ~(R600_BLOCK_STATUS_ENABLED
| R600_BLOCK_STATUS_DIRTY
);
828 if (state
->nregs
<= 3) {
831 block
->reg
[0] = state
->regs
[3].value
;
832 block
->reg
[1] = state
->regs
[4].value
;
833 block
->reg
[2] = state
->regs
[5].value
;
834 block
->reg
[3] = state
->regs
[6].value
;
835 if (!(block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
836 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
837 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
838 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
;
842 void r600_context_pipe_state_set_ps_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
846 offset
= 0x0003C000 + id
* 0xc;
847 r600_context_pipe_state_set_sampler(ctx
, state
, offset
);
848 offset
= 0x0000A400 + id
* 0x10;
849 r600_context_pipe_state_set_sampler_border(ctx
, state
, offset
);
852 void r600_context_pipe_state_set_vs_sampler(struct r600_context
*ctx
, struct r600_pipe_state
*state
, unsigned id
)
856 offset
= 0x0003C0D8 + id
* 0xc;
857 r600_context_pipe_state_set_sampler(ctx
, state
, offset
);
858 offset
= 0x0000A600 + id
* 0x10;
859 r600_context_pipe_state_set_sampler_border(ctx
, state
, offset
);
862 struct radeon_bo
*r600_context_reg_bo(struct r600_context
*ctx
, unsigned offset
)
864 struct r600_range
*range
;
865 struct r600_block
*block
;
868 range
= &ctx
->range
[CTX_RANGE_ID(ctx
, offset
)];
869 block
= range
->blocks
[CTX_BLOCK_ID(ctx
, offset
)];
870 offset
-= block
->start_offset
;
871 id
= block
->pm4_bo_index
[offset
>> 2];
872 if (block
->reloc
[id
].bo
) {
873 return radeon_bo_pb_get_bo(block
->reloc
[id
].bo
->pb
);
878 void r600_context_draw(struct r600_context
*ctx
, const struct r600_draw
*draw
)
880 struct radeon_bo
*cb
[8];
881 struct radeon_bo
*db
;
882 unsigned ndwords
= 9;
886 /* make sure there is enough relocation space before scheduling draw */
887 if (ctx
->creloc
>= (ctx
->nreloc
- 1)) {
888 r600_context_flush(ctx
);
892 /* find number of color buffer */
893 db
= r600_context_reg_bo(ctx
, R_02800C_DB_DEPTH_BASE
);
894 cb
[0] = r600_context_reg_bo(ctx
, R_028040_CB_COLOR0_BASE
);
895 cb
[1] = r600_context_reg_bo(ctx
, R_028044_CB_COLOR1_BASE
);
896 cb
[2] = r600_context_reg_bo(ctx
, R_028048_CB_COLOR2_BASE
);
897 cb
[3] = r600_context_reg_bo(ctx
, R_02804C_CB_COLOR3_BASE
);
898 cb
[4] = r600_context_reg_bo(ctx
, R_028050_CB_COLOR4_BASE
);
899 cb
[5] = r600_context_reg_bo(ctx
, R_028054_CB_COLOR5_BASE
);
900 cb
[6] = r600_context_reg_bo(ctx
, R_028058_CB_COLOR6_BASE
);
901 cb
[7] = r600_context_reg_bo(ctx
, R_02805C_CB_COLOR7_BASE
);
902 for (int i
= 0; i
< 8; i
++) {
910 /* queries need some special values */
911 if (ctx
->num_query_running
) {
912 if (ctx
->radeon
->family
>= CHIP_RV770
) {
913 r600_context_reg(ctx
,
914 R_028D0C_DB_RENDER_CONTROL
,
915 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
916 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
918 r600_context_reg(ctx
,
919 R_028D10_DB_RENDER_OVERRIDE
,
920 S_028D10_NOOP_CULL_DISABLE(1),
921 S_028D10_NOOP_CULL_DISABLE(1));
924 if ((ctx
->pm4_dirty_cdwords
+ ndwords
+ ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
926 r600_context_flush(ctx
);
928 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
929 if ((ctx
->pm4_dirty_cdwords
+ ndwords
) > ctx
->pm4_ndwords
) {
930 R600_ERR("context is too big to be scheduled\n");
934 /* enough room to copy packet */
935 for (int i
= 0; i
< ctx
->nblocks
; i
++) {
936 if (ctx
->blocks
[i
]->status
& R600_BLOCK_STATUS_DIRTY
) {
937 r600_context_block_emit_dirty(ctx
, ctx
->blocks
[i
]);
942 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_INDEX_TYPE
, 0);
943 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_index_type
;
944 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NUM_INSTANCES
, 0);
945 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_instances
;
947 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_DRAW_INDEX
, 3);
948 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->indices_bo_offset
;
949 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
950 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_indices
;
951 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_draw_initiator
;
952 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0);
953 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
954 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], radeon_bo_pb_get_bo(draw
->indices
->pb
));
956 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1);
957 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_num_indices
;
958 ctx
->pm4
[ctx
->pm4_cdwords
++] = draw
->vgt_draw_initiator
;
960 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 0);
961 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
;
963 /* flush color buffer */
964 for (int i
= 0; i
< 8; i
++) {
966 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3);
967 ctx
->pm4
[ctx
->pm4_cdwords
++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i
) |
968 S_0085F0_CB_ACTION_ENA(1);
969 ctx
->pm4
[ctx
->pm4_cdwords
++] = (cb
[i
]->size
+ 255) >> 8;
970 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x00000000;
971 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x0000000A;
972 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0);
973 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
974 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], cb
[i
]);
978 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_SURFACE_SYNC
, 3);
979 ctx
->pm4
[ctx
->pm4_cdwords
++] = S_0085F0_DB_DEST_BASE_ENA(1) |
980 S_0085F0_DB_ACTION_ENA(1);
981 ctx
->pm4
[ctx
->pm4_cdwords
++] = (db
->size
+ 255) >> 8;
982 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x00000000;
983 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0x0000000A;
984 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0);
985 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
986 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], db
);
989 /* all dirty state have been scheduled in current cs */
990 ctx
->pm4_dirty_cdwords
= 0;
993 void r600_context_flush(struct r600_context
*ctx
)
995 struct drm_radeon_cs drmib
;
996 struct drm_radeon_cs_chunk chunks
[2];
997 uint64_t chunk_array
[2];
1000 if (!ctx
->pm4_cdwords
)
1003 /* suspend queries */
1004 r600_context_queries_suspend(ctx
);
1006 radeon_bo_pbmgr_flush_maps(ctx
->radeon
->kman
);
1009 drmib
.num_chunks
= 2;
1010 drmib
.chunks
= (uint64_t)(uintptr_t)chunk_array
;
1011 chunks
[0].chunk_id
= RADEON_CHUNK_ID_IB
;
1012 chunks
[0].length_dw
= ctx
->pm4_cdwords
;
1013 chunks
[0].chunk_data
= (uint64_t)(uintptr_t)ctx
->pm4
;
1014 chunks
[1].chunk_id
= RADEON_CHUNK_ID_RELOCS
;
1015 chunks
[1].length_dw
= ctx
->creloc
* sizeof(struct r600_reloc
) / 4;
1016 chunks
[1].chunk_data
= (uint64_t)(uintptr_t)ctx
->reloc
;
1017 chunk_array
[0] = (uint64_t)(uintptr_t)&chunks
[0];
1018 chunk_array
[1] = (uint64_t)(uintptr_t)&chunks
[1];
1019 r
= drmCommandWriteRead(ctx
->radeon
->fd
, DRM_RADEON_CS
, &drmib
,
1020 sizeof(struct drm_radeon_cs
));
1023 for (int i
= 0; i
< ctx
->creloc
; i
++) {
1024 radeon_bo_reference(ctx
->radeon
, &ctx
->bo
[i
], NULL
);
1027 ctx
->pm4_dirty_cdwords
= 0;
1028 ctx
->pm4_cdwords
= 0;
1030 /* resume queries */
1031 r600_context_queries_resume(ctx
);
1033 /* set all valid group as dirty so they get reemited on
1036 for (int i
= 0; i
< ctx
->nblocks
; i
++) {
1037 if (ctx
->blocks
[i
]->status
& R600_BLOCK_STATUS_ENABLED
) {
1038 ctx
->pm4_dirty_cdwords
+= ctx
->blocks
[i
]->pm4_ndwords
;
1039 ctx
->blocks
[i
]->status
|= R600_BLOCK_STATUS_DIRTY
;
1044 void r600_context_dump_bof(struct r600_context
*ctx
, const char *file
)
1046 bof_t
*bcs
, *blob
, *array
, *bo
, *size
, *handle
, *device_id
, *root
;
1049 root
= device_id
= bcs
= blob
= array
= bo
= size
= handle
= NULL
;
1050 root
= bof_object();
1053 device_id
= bof_int32(ctx
->radeon
->device
);
1054 if (device_id
== NULL
)
1056 if (bof_object_set(root
, "device_id", device_id
))
1058 bof_decref(device_id
);
1061 blob
= bof_blob(ctx
->creloc
* 16, ctx
->reloc
);
1064 if (bof_object_set(root
, "reloc", blob
))
1069 blob
= bof_blob(ctx
->pm4_cdwords
* 4, ctx
->pm4
);
1072 if (bof_object_set(root
, "pm4", blob
))
1077 array
= bof_array();
1080 for (i
= 0; i
< ctx
->creloc
; i
++) {
1081 struct radeon_bo
*rbo
= ctx
->bo
[i
];
1085 size
= bof_int32(rbo
->size
);
1088 if (bof_object_set(bo
, "size", size
))
1092 handle
= bof_int32(rbo
->handle
);
1095 if (bof_object_set(bo
, "handle", handle
))
1099 radeon_bo_map(ctx
->radeon
, rbo
);
1100 blob
= bof_blob(rbo
->size
, rbo
->data
);
1101 radeon_bo_unmap(ctx
->radeon
, rbo
);
1104 if (bof_object_set(bo
, "data", blob
))
1108 if (bof_array_append(array
, bo
))
1113 if (bof_object_set(root
, "bo", array
))
1115 bof_dump_file(root
, file
);
1122 bof_decref(device_id
);
1126 static void r600_query_result(struct r600_context
*ctx
, struct r600_query
*query
)
1132 results
= radeon_ws_bo_map(ctx
->radeon
, query
->buffer
, 0, NULL
);
1133 for (i
= 0; i
< query
->num_results
; i
+= 4) {
1134 start
= (u64
)results
[i
] | (u64
)results
[i
+ 1] << 32;
1135 end
= (u64
)results
[i
+ 2] | (u64
)results
[i
+ 3] << 32;
1136 if ((start
& 0x8000000000000000UL
) && (end
& 0x8000000000000000UL
)) {
1137 query
->result
+= end
- start
;
1140 radeon_ws_bo_unmap(ctx
->radeon
, query
->buffer
);
1141 query
->num_results
= 0;
1144 void r600_query_begin(struct r600_context
*ctx
, struct r600_query
*query
)
1146 /* query request needs 6 dwords for begin + 6 dwords for end */
1147 if ((12 + ctx
->pm4_cdwords
) > ctx
->pm4_ndwords
) {
1149 r600_context_flush(ctx
);
1152 /* if query buffer is full force a flush */
1153 if (query
->num_results
>= ((query
->buffer_size
>> 2) - 2)) {
1154 r600_context_flush(ctx
);
1155 r600_query_result(ctx
, query
);
1158 /* emit begin query */
1159 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 2);
1160 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE_ZPASS_DONE
;
1161 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->num_results
;
1162 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1163 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0);
1164 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1165 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], radeon_bo_pb_get_bo(query
->buffer
->pb
));
1167 query
->state
|= R600_QUERY_STATE_STARTED
;
1168 query
->state
^= R600_QUERY_STATE_ENDED
;
1169 ctx
->num_query_running
++;
1172 void r600_query_end(struct r600_context
*ctx
, struct r600_query
*query
)
1174 /* emit begin query */
1175 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_EVENT_WRITE
, 2);
1176 ctx
->pm4
[ctx
->pm4_cdwords
++] = EVENT_TYPE_ZPASS_DONE
;
1177 ctx
->pm4
[ctx
->pm4_cdwords
++] = query
->num_results
+ 8;
1178 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1179 ctx
->pm4
[ctx
->pm4_cdwords
++] = PKT3(PKT3_NOP
, 0);
1180 ctx
->pm4
[ctx
->pm4_cdwords
++] = 0;
1181 r600_context_bo_reloc(ctx
, &ctx
->pm4
[ctx
->pm4_cdwords
- 1], radeon_bo_pb_get_bo(query
->buffer
->pb
));
1183 query
->num_results
+= 16;
1184 query
->state
^= R600_QUERY_STATE_STARTED
;
1185 query
->state
|= R600_QUERY_STATE_ENDED
;
1186 ctx
->num_query_running
--;
1189 struct r600_query
*r600_context_query_create(struct r600_context
*ctx
, unsigned query_type
)
1191 struct r600_query
*query
;
1193 if (query_type
!= PIPE_QUERY_OCCLUSION_COUNTER
)
1196 query
= calloc(1, sizeof(struct r600_query
));
1200 query
->type
= query_type
;
1201 query
->buffer_size
= 4096;
1203 query
->buffer
= radeon_ws_bo(ctx
->radeon
, query
->buffer_size
, 1, 0);
1204 if (!query
->buffer
) {
1209 LIST_ADDTAIL(&query
->list
, &ctx
->query_list
);
1214 void r600_context_query_destroy(struct r600_context
*ctx
, struct r600_query
*query
)
1216 radeon_ws_bo_reference(ctx
->radeon
, &query
->buffer
, NULL
);
1217 LIST_DEL(&query
->list
);
1221 boolean
r600_context_query_result(struct r600_context
*ctx
,
1222 struct r600_query
*query
,
1223 boolean wait
, void *vresult
)
1225 uint64_t *result
= (uint64_t*)vresult
;
1227 if (query
->num_results
) {
1228 r600_context_flush(ctx
);
1230 r600_query_result(ctx
, query
);
1231 *result
= query
->result
;
1236 void r600_context_queries_suspend(struct r600_context
*ctx
)
1238 struct r600_query
*query
;
1240 LIST_FOR_EACH_ENTRY(query
, &ctx
->query_list
, list
) {
1241 if (query
->state
& R600_QUERY_STATE_STARTED
) {
1242 r600_query_end(ctx
, query
);
1243 query
->state
|= R600_QUERY_STATE_SUSPENDED
;
1248 void r600_context_queries_resume(struct r600_context
*ctx
)
1250 struct r600_query
*query
;
1252 LIST_FOR_EACH_ENTRY(query
, &ctx
->query_list
, list
) {
1253 if (query
->state
& R600_QUERY_STATE_SUSPENDED
) {
1254 r600_query_begin(ctx
, query
);
1255 query
->state
^= R600_QUERY_STATE_SUSPENDED
;