projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: move more DRM queries into winsys/radeon
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include "radeon_drm.h"
30 #include "xf86drm.h"
31 #include <errno.h>
32
33 #define GROUP_FORCE_NEW_BLOCK 0
34
35 /* Get backends mask */
36 void r600_get_backend_mask(struct r600_context *ctx)
37 {
38 struct r600_bo * buffer;
39 u32 * results;
40 unsigned num_backends = r600_get_num_backends(ctx->radeon);
41 unsigned i, mask = 0;
42
43 /* if backend_map query is supported by the kernel */
44 if (ctx->radeon->info.r600_backend_map_valid) {
45 unsigned num_tile_pipes = r600_get_num_tile_pipes(ctx->radeon);
46 unsigned backend_map = r600_get_backend_map(ctx->radeon);
47 unsigned item_width, item_mask;
48
49 if (ctx->radeon->chip_class >= EVERGREEN) {
50 item_width = 4;
51 item_mask = 0x7;
52 } else {
53 item_width = 2;
54 item_mask = 0x3;
55 }
56
57 while(num_tile_pipes--) {
58 i = backend_map & item_mask;
59 mask |= (1<<i);
60 backend_map >>= item_width;
61 }
62 if (mask != 0) {
63 ctx->backend_mask = mask;
64 return;
65 }
66 }
67
68 /* otherwise backup path for older kernels */
69
70 /* create buffer for event data */
71 buffer = r600_bo(ctx->radeon, ctx->max_db*16, 1, 0,
72 PIPE_USAGE_STAGING);
73 if (!buffer)
74 goto err;
75
76 /* initialize buffer with zeroes */
77 results = r600_bo_map(ctx->radeon, buffer, PB_USAGE_CPU_WRITE, NULL);
78 if (results) {
79 memset(results, 0, ctx->max_db * 4 * 4);
80 r600_bo_unmap(ctx->radeon, buffer);
81
82 /* emit EVENT_WRITE for ZPASS_DONE */
83 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
84 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
85 ctx->pm4[ctx->pm4_cdwords++] = 0;
86 ctx->pm4[ctx->pm4_cdwords++] = 0;
87
88 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
89 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, buffer);
90
91 /* execute */
92 r600_context_flush(ctx);
93
94 /* analyze results */
95 results = r600_bo_map(ctx->radeon, buffer, PB_USAGE_CPU_READ, NULL);
96 if (results) {
97 for(i = 0; i < ctx->max_db; i++) {
98 /* at least highest bit will be set if backend is used */
99 if (results[i*4 + 1])
100 mask |= (1<<i);
101 }
102 r600_bo_unmap(ctx->radeon, buffer);
103 }
104 }
105
106 r600_bo_reference(ctx->radeon, &buffer, NULL);
107
108 if (mask != 0) {
109 ctx->backend_mask = mask;
110 return;
111 }
112
113 err:
114 /* fallback to old method - set num_backends lower bits to 1 */
115 ctx->backend_mask = (~((u32)0))>>(32-num_backends);
116 return;
117 }
118
119 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
120 {
121 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
122 return;
123
124 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
125 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
126
127 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
128 }
129
130 void r600_init_cs(struct r600_context *ctx)
131 {
132 /* R6xx requires this packet at the start of each command buffer */
133 if (ctx->radeon->family < CHIP_RV770) {
134 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
135 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
136 }
137 /* All asics require this one */
138 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
139 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
140 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
141
142 ctx->init_dwords = ctx->pm4_cdwords;
143 }
144
145 static void r600_init_block(struct r600_context *ctx,
146 struct r600_block *block,
147 const struct r600_reg *reg, int index, int nreg,
148 unsigned opcode, unsigned offset_base)
149 {
150 int i = index;
151 int j, n = nreg;
152
153 /* initialize block */
154 if (opcode == PKT3_SET_RESOURCE) {
155 block->flags = BLOCK_FLAG_RESOURCE;
156 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
157 } else {
158 block->flags = 0;
159 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
160 }
161 block->start_offset = reg[i].offset;
162 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
163 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
164 block->reg = &block->pm4[block->pm4_ndwords];
165 block->pm4_ndwords += n;
166 block->nreg = n;
167 block->nreg_dirty = n;
168 LIST_INITHEAD(&block->list);
169 LIST_INITHEAD(&block->enable_list);
170
171 for (j = 0; j < n; j++) {
172 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
173 block->flags |= REG_FLAG_DIRTY_ALWAYS;
174 }
175 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
176 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
177 block->status |= R600_BLOCK_STATUS_ENABLED;
178 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
179 LIST_ADDTAIL(&block->list,&ctx->dirty);
180 }
181 }
182 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
183 block->flags |= REG_FLAG_FLUSH_CHANGE;
184 }
185
186 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
187 block->nbo++;
188 assert(block->nbo < R600_BLOCK_MAX_BO);
189 block->pm4_bo_index[j] = block->nbo;
190 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
191 block->pm4[block->pm4_ndwords++] = 0x00000000;
192 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
193 block->reloc[block->nbo].flush_flags = 0;
194 block->reloc[block->nbo].flush_mask = 0;
195 } else {
196 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
197 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
198 }
199 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
200 }
201 if ((ctx->radeon->family > CHIP_R600) &&
202 (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
203 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
204 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
205 }
206 }
207 for (j = 0; j < n; j++) {
208 if (reg[i+j].flush_flags) {
209 block->pm4_flush_ndwords += 7;
210 }
211 }
212 /* check that we stay in limit */
213 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
214 }
215
216 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
217 unsigned opcode, unsigned offset_base)
218 {
219 struct r600_block *block;
220 struct r600_range *range;
221 int offset;
222
223 for (unsigned i = 0, n = 0; i < nreg; i += n) {
224 /* ignore new block balise */
225 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
226 n = 1;
227 continue;
228 }
229
230 /* ignore regs not on R600 on R600 */
231 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
232 n = 1;
233 continue;
234 }
235
236 /* register that need relocation are in their own group */
237 /* find number of consecutive registers */
238 n = 0;
239 offset = reg[i].offset;
240 while (reg[i + n].offset == offset) {
241 n++;
242 offset += 4;
243 if ((n + i) >= nreg)
244 break;
245 if (n >= (R600_BLOCK_MAX_REG - 2))
246 break;
247 }
248
249 /* allocate new block */
250 block = calloc(1, sizeof(struct r600_block));
251 if (block == NULL) {
252 return -ENOMEM;
253 }
254 ctx->nblocks++;
255 for (int j = 0; j < n; j++) {
256 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
257 /* create block table if it doesn't exist */
258 if (!range->blocks)
259 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
260 if (!range->blocks)
261 return -1;
262
263 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
264 }
265
266 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
267
268 }
269 return 0;
270 }
271
272 /* R600/R700 configuration */
273 static const struct r600_reg r600_config_reg_list[] = {
274 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
275 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
276 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
277 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
278 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
279 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
280 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
281 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
282 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
283 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
284 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
285 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
286 };
287
288 static const struct r600_reg r600_ctl_const_list[] = {
289 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
290 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
291 };
292
293 static const struct r600_reg r600_context_reg_list[] = {
294 {R_028350_SX_MISC, 0, 0, 0},
295 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
296 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
297 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
298 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
299 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
300 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
301 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
302 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
303 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
304 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
305 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
306 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
307 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
308 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
309 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
310 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
311 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
312 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
313 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
314 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
315 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
316 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
317 {R_028A40_VGT_GS_MODE, 0, 0, 0},
318 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
319 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
320 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
321 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
322 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
323 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
324 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
325 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
326 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
327 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
328 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
329 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
330 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
331 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
332 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
333 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
334 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
335 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
336 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
337 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
338 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
339 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
340 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
341 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
342 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
343 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
345 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
346 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
347 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
348 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
349 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
350 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
351 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
352 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
353 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
354 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
355 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
356 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
357 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
358 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
359 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
360 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
361 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
362 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
363 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
364 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
365 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
366 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
367 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
368 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
369 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
370 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
371 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
372 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
373 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
374 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
375 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
376 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
377 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
378 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
379 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
380 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
381 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
382 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
383 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
384 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
385 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
386 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
387 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
388 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
389 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
390 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
391 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
392 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
393 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
394 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
395 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
396 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
397 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
398 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
399 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
400 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
401 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
402 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
403 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
404 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
405 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
406 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
407 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
408 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
409 {R_028120_CB_CLEAR_RED, 0, 0, 0},
410 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
411 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
412 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
413 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
414 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
415 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
416 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
417 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
418 {R_028238_CB_TARGET_MASK, 0, 0, 0},
419 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
420 {R_028414_CB_BLEND_RED, 0, 0, 0},
421 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
422 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
423 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
424 {R_028424_CB_FOG_RED, 0, 0, 0},
425 {R_028428_CB_FOG_GREEN, 0, 0, 0},
426 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
427 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
428 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
429 {R_028438_SX_ALPHA_REF, 0, 0, 0},
430 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
431 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
432 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
433 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
434 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
435 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
436 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
437 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
438 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
439 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
440 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
441 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
442 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
443 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
444 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
445 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
446 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
447 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
448 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
449 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
450 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
451 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
452 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
453 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
454 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
455 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
456 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
457 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
458 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
459 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
460 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
461 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
462 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
463 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
464 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
465 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
466 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
467 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
468 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
469 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
470 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
471 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
472 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
473 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
474 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
475 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
476 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
477 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
478 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
479 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
480 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
481 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
482 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
483 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
484 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
485 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
486 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
487 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
488 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
489 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
490 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
491 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
492 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
493 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
494 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
495 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
496 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
497 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
498 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
499 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
500 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
501 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
502 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
503 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
504 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
505 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
506 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
507 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
508 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
509 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
510 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
511 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
512 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
513 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
514 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
515 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
516 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
517 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
518 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
519 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
520 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
521 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
522 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
523 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
524 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
525 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
526 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
527 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
528 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
529 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
530 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
531 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
532 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
533 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
534 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
535 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
536 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
537 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
538 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
539 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
540 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
541 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
542 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
543 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
544 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
545 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
546 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
547 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
548 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
549 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
550 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
551 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
552 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
553 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
554 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
555 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
556 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
557 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
558 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
559 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
560 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
561 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
562 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
563 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
564 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
565 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
566 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
567 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
568 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
569 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
570 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
571 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
572 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
573 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
574 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
575 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
576 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
577 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
578 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
579 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
580 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
581 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
582 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
583 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
584 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
585 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
586 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
587 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
588 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
589 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
590 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
591 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
592 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
593 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
594 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
595 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
596 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
597 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
598 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
599 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
600 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
601 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
602 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
603 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
604 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
605 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
606 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
607 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
608 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
609 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
610 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
611 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
612 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
613 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
614 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
615 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
616 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
617 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
618 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
619 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
620 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
621 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
622 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
623 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
624 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
625 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
626 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
627 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
628 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
629 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
630 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
631 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
632 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
633 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
634 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
635 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
636 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
637 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
638 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
639 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
640 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
641 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
642 };
643
644 /* SHADER RESOURCE R600/R700 */
645 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
646 {
647 int i;
648 struct r600_block *block;
649 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
650 if (range->blocks == NULL)
651 return -ENOMEM;
652
653 reg[0].offset += offset;
654 for (i = 0; i < nblocks; i++) {
655 block = calloc(1, sizeof(struct r600_block));
656 if (block == NULL) {
657 return -ENOMEM;
658 }
659 ctx->nblocks++;
660 range->blocks[i] = block;
661 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
662
663 reg[0].offset += stride;
664 }
665 return 0;
666 }
667
668
669 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
670 {
671 struct r600_reg r600_shader_resource[] = {
672 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
673 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
674 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
675 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
676 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
677 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
678 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
679 };
680 unsigned nreg = Elements(r600_shader_resource);
681
682 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
683 }
684
685 /* SHADER SAMPLER R600/R700 */
686 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
687 {
688 struct r600_reg r600_shader_sampler[] = {
689 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
690 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
691 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
692 };
693 unsigned nreg = Elements(r600_shader_sampler);
694
695 for (int i = 0; i < nreg; i++) {
696 r600_shader_sampler[i].offset += offset;
697 }
698 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
699 }
700
701 /* SHADER SAMPLER BORDER R600/R700 */
702 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
703 {
704 struct r600_reg r600_shader_sampler_border[] = {
705 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
706 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
707 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
708 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
709 };
710 unsigned nreg = Elements(r600_shader_sampler_border);
711
712 for (int i = 0; i < nreg; i++) {
713 r600_shader_sampler_border[i].offset += offset;
714 }
715 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
716 }
717
718 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
719 {
720 unsigned nreg = 32;
721 struct r600_reg r600_loop_consts[32];
722 int i;
723
724 for (i = 0; i < nreg; i++) {
725 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
726 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
727 r600_loop_consts[i].flush_flags = 0;
728 r600_loop_consts[i].flush_mask = 0;
729 }
730 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
731 }
732
733 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
734 {
735 struct r600_block *block;
736 int i;
737 for (i = 0; i < nblocks; i++) {
738 block = range->blocks[i];
739 if (block) {
740 for (int k = 1; k <= block->nbo; k++)
741 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
742 free(block);
743 }
744 }
745 free(range->blocks);
746
747 }
748
749 /* initialize */
750 void r600_context_fini(struct r600_context *ctx)
751 {
752 struct r600_block *block;
753 struct r600_range *range;
754
755 for (int i = 0; i < NUM_RANGES; i++) {
756 if (!ctx->range[i].blocks)
757 continue;
758 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
759 block = ctx->range[i].blocks[j];
760 if (block) {
761 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
762 range = &ctx->range[CTX_RANGE_ID(offset)];
763 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
764 }
765 for (int k = 1; k <= block->nbo; k++) {
766 r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
767 }
768 free(block);
769 }
770 }
771 free(ctx->range[i].blocks);
772 }
773 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
774 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
775 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
776 free(ctx->range);
777 free(ctx->blocks);
778 free(ctx->bo);
779 ctx->radeon->ws->cs_destroy(ctx->cs);
780
781 memset(ctx, 0, sizeof(struct r600_context));
782 }
783
784 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
785 {
786 int c = *index;
787 for (int j = 0; j < num_blocks; j++) {
788 if (!range->blocks[j])
789 continue;
790
791 ctx->blocks[c++] = range->blocks[j];
792 }
793 *index = c;
794 }
795
796 int r600_setup_block_table(struct r600_context *ctx)
797 {
798 /* setup block table */
799 int c = 0;
800 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
801 if (!ctx->blocks)
802 return -ENOMEM;
803 for (int i = 0; i < NUM_RANGES; i++) {
804 if (!ctx->range[i].blocks)
805 continue;
806 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
807 if (!ctx->range[i].blocks[j])
808 continue;
809
810 add = 1;
811 for (int k = 0; k < c; k++) {
812 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
813 add = 0;
814 break;
815 }
816 }
817 if (add) {
818 assert(c < ctx->nblocks);
819 ctx->blocks[c++] = ctx->range[i].blocks[j];
820 j += (ctx->range[i].blocks[j]->nreg) - 1;
821 }
822 }
823 }
824
825 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
826 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
827 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
828 return 0;
829 }
830
831 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
832 {
833 int r;
834
835 memset(ctx, 0, sizeof(struct r600_context));
836 ctx->radeon = radeon;
837
838 LIST_INITHEAD(&ctx->query_list);
839
840 /* init dirty list */
841 LIST_INITHEAD(&ctx->dirty);
842 LIST_INITHEAD(&ctx->resource_dirty);
843 LIST_INITHEAD(&ctx->enable_list);
844
845 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
846 if (!ctx->range) {
847 r = -ENOMEM;
848 goto out_err;
849 }
850
851 /* add blocks */
852 r = r600_context_add_block(ctx, r600_config_reg_list,
853 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
854 if (r)
855 goto out_err;
856 r = r600_context_add_block(ctx, r600_context_reg_list,
857 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
858 if (r)
859 goto out_err;
860 r = r600_context_add_block(ctx, r600_ctl_const_list,
861 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
862 if (r)
863 goto out_err;
864
865 /* PS SAMPLER BORDER */
866 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
867 r = r600_state_sampler_border_init(ctx, offset);
868 if (r)
869 goto out_err;
870 }
871
872 /* VS SAMPLER BORDER */
873 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
874 r = r600_state_sampler_border_init(ctx, offset);
875 if (r)
876 goto out_err;
877 }
878 /* PS SAMPLER */
879 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
880 r = r600_state_sampler_init(ctx, offset);
881 if (r)
882 goto out_err;
883 }
884 /* VS SAMPLER */
885 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
886 r = r600_state_sampler_init(ctx, offset);
887 if (r)
888 goto out_err;
889 }
890
891 ctx->num_ps_resources = 160;
892 ctx->num_vs_resources = 160;
893 ctx->num_fs_resources = 16;
894 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
895 if (r)
896 goto out_err;
897 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
898 if (r)
899 goto out_err;
900 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
901 if (r)
902 goto out_err;
903
904 /* PS loop const */
905 r600_loop_const_init(ctx, 0);
906 /* VS loop const */
907 r600_loop_const_init(ctx, 32);
908
909 r = r600_setup_block_table(ctx);
910 if (r)
911 goto out_err;
912
913 ctx->cs = radeon->ws->cs_create(radeon->ws);
914
915 /* allocate cs variables */
916 ctx->bo = calloc(RADEON_CTX_MAX_PM4, sizeof(void *));
917 if (ctx->bo == NULL) {
918 r = -ENOMEM;
919 goto out_err;
920 }
921 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
922 ctx->pm4 = ctx->cs->buf;
923
924 r600_init_cs(ctx);
925 /* save 16dwords space for fence mecanism */
926 ctx->pm4_ndwords -= 16;
927 ctx->max_db = 4;
928
929 r600_get_backend_mask(ctx);
930 return 0;
931 out_err:
932 r600_context_fini(ctx);
933 return r;
934 }
935
936 /* Flushes all surfaces */
937 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
938 {
939 unsigned ndwords = 5;
940
941 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
942 /* need to flush */
943 r600_context_flush(ctx);
944 }
945
946 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
947 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
948 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
949 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
950 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
951 }
952
953 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
954 unsigned flush_mask, struct r600_bo *rbo)
955 {
956 struct radeon_bo *bo;
957
958 bo = rbo->bo;
959 /* if bo has already been flushed */
960 if (!(~bo->last_flush & flush_flags)) {
961 bo->last_flush &= flush_mask;
962 return;
963 }
964
965 if ((ctx->radeon->family < CHIP_RV770) &&
966 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
967 G_0085F0_DB_ACTION_ENA(flush_flags))) {
968 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
969 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
970 if ((bo->binding & BO_BOUND_TEXTURE) &&
971 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
972 if ((ctx->radeon->family == CHIP_RV670) ||
973 (ctx->radeon->family == CHIP_RS780) ||
974 (ctx->radeon->family == CHIP_RS880)) {
975 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
976 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
977 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
978 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
979 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
980 }
981 }
982
983 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
984 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
985 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
986 }
987 } else {
988 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
989 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
990 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
991 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
992 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
993 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
994 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, rbo);
995 }
996 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
997 }
998
999 void r600_context_reg(struct r600_context *ctx,
1000 unsigned offset, unsigned value,
1001 unsigned mask)
1002 {
1003 struct r600_range *range;
1004 struct r600_block *block;
1005 unsigned id;
1006 unsigned new_val;
1007 int dirty;
1008
1009 range = &ctx->range[CTX_RANGE_ID(offset)];
1010 block = range->blocks[CTX_BLOCK_ID(offset)];
1011 id = (offset - block->start_offset) >> 2;
1012
1013 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1014
1015 new_val = block->reg[id];
1016 new_val &= ~mask;
1017 new_val |= value;
1018 if (new_val != block->reg[id]) {
1019 dirty |= R600_BLOCK_STATUS_DIRTY;
1020 block->reg[id] = new_val;
1021 }
1022 if (dirty)
1023 r600_context_dirty_block(ctx, block, dirty, id);
1024 }
1025
1026 void r600_context_dirty_block(struct r600_context *ctx,
1027 struct r600_block *block,
1028 int dirty, int index)
1029 {
1030 if ((index + 1) > block->nreg_dirty)
1031 block->nreg_dirty = index + 1;
1032
1033 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1034 block->status |= R600_BLOCK_STATUS_DIRTY;
1035 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1036 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1037 block->status |= R600_BLOCK_STATUS_ENABLED;
1038 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1039 }
1040 LIST_ADDTAIL(&block->list,&ctx->dirty);
1041
1042 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1043 r600_context_ps_partial_flush(ctx);
1044 }
1045 }
1046 }
1047
1048 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1049 {
1050 struct r600_block *block;
1051 unsigned new_val;
1052 int dirty;
1053 for (int i = 0; i < state->nregs; i++) {
1054 unsigned id, reloc_id;
1055 struct r600_pipe_reg *reg = &state->regs[i];
1056
1057 block = reg->block;
1058 id = reg->id;
1059
1060 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1061
1062 new_val = block->reg[id];
1063 new_val &= ~reg->mask;
1064 new_val |= reg->value;
1065 if (new_val != block->reg[id]) {
1066 block->reg[id] = new_val;
1067 dirty |= R600_BLOCK_STATUS_DIRTY;
1068 }
1069 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1070 dirty |= R600_BLOCK_STATUS_DIRTY;
1071 if (block->pm4_bo_index[id]) {
1072 /* find relocation */
1073 reloc_id = block->pm4_bo_index[id];
1074 r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
1075 /* always force dirty for relocs for now */
1076 dirty |= R600_BLOCK_STATUS_DIRTY;
1077 }
1078
1079 if (dirty)
1080 r600_context_dirty_block(ctx, block, dirty, id);
1081 }
1082 }
1083
1084 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1085 struct r600_block *block,
1086 int dirty, int index)
1087 {
1088 block->nreg_dirty = index + 1;
1089
1090 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1091 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1092 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1093 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1094 block->status |= R600_BLOCK_STATUS_ENABLED;
1095 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1096 }
1097 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1098 }
1099 }
1100
1101 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1102 {
1103 int dirty;
1104 int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
1105 boolean is_vertex;
1106
1107 if (state == NULL) {
1108 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1109 if (block->reloc[1].bo)
1110 block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
1111
1112 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
1113 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1114 LIST_DELINIT(&block->list);
1115 LIST_DELINIT(&block->enable_list);
1116 return;
1117 }
1118
1119 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1120 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1121
1122 if (memcmp(block->reg, state->val, num_regs*4)) {
1123 memcpy(block->reg, state->val, num_regs * 4);
1124 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1125 }
1126
1127 /* if no BOs on block, force dirty */
1128 if (!block->reloc[1].bo || !block->reloc[2].bo)
1129 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1130
1131 if (!dirty) {
1132 if (is_vertex) {
1133 if (block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle)
1134 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1135 } else {
1136 if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
1137 (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
1138 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1139 }
1140 }
1141
1142 if (dirty) {
1143 if (is_vertex) {
1144 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1145 * we have single case btw VERTEX & TEXTURE resource
1146 */
1147 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1148 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
1149 } else {
1150 /* TEXTURE RESOURCE */
1151 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
1152 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
1153 state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
1154 }
1155
1156 if (is_vertex)
1157 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1158 else
1159 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1160
1161 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1162 }
1163 }
1164
1165 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1166 {
1167 struct r600_block *block = ctx->ps_resources.blocks[rid];
1168
1169 r600_context_pipe_state_set_resource(ctx, state, block);
1170 }
1171
1172 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1173 {
1174 struct r600_block *block = ctx->vs_resources.blocks[rid];
1175
1176 r600_context_pipe_state_set_resource(ctx, state, block);
1177 }
1178
1179 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1180 {
1181 struct r600_block *block = ctx->fs_resources.blocks[rid];
1182
1183 r600_context_pipe_state_set_resource(ctx, state, block);
1184 }
1185
1186 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1187 {
1188 struct r600_range *range;
1189 struct r600_block *block;
1190 int i;
1191 int dirty;
1192
1193 range = &ctx->range[CTX_RANGE_ID(offset)];
1194 block = range->blocks[CTX_BLOCK_ID(offset)];
1195 if (state == NULL) {
1196 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1197 LIST_DELINIT(&block->list);
1198 LIST_DELINIT(&block->enable_list);
1199 return;
1200 }
1201 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1202 for (i = 0; i < 3; i++) {
1203 if (block->reg[i] != state->regs[i].value) {
1204 block->reg[i] = state->regs[i].value;
1205 dirty |= R600_BLOCK_STATUS_DIRTY;
1206 }
1207 }
1208
1209 if (dirty)
1210 r600_context_dirty_block(ctx, block, dirty, 2);
1211 }
1212
1213
1214 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1215 {
1216 struct r600_range *range;
1217 struct r600_block *block;
1218 int i;
1219 int dirty;
1220
1221 range = &ctx->range[CTX_RANGE_ID(offset)];
1222 block = range->blocks[CTX_BLOCK_ID(offset)];
1223 if (state == NULL) {
1224 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1225 LIST_DELINIT(&block->list);
1226 LIST_DELINIT(&block->enable_list);
1227 return;
1228 }
1229 if (state->nregs <= 3) {
1230 return;
1231 }
1232 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1233 for (i = 0; i < 4; i++) {
1234 if (block->reg[i] != state->regs[i + 3].value) {
1235 block->reg[i] = state->regs[i + 3].value;
1236 dirty |= R600_BLOCK_STATUS_DIRTY;
1237 }
1238 }
1239
1240 /* We have to flush the shaders before we change the border color
1241 * registers, or previous draw commands that haven't completed yet
1242 * will end up using the new border color. */
1243 if (dirty & R600_BLOCK_STATUS_DIRTY)
1244 r600_context_ps_partial_flush(ctx);
1245 if (dirty)
1246 r600_context_dirty_block(ctx, block, dirty, 3);
1247 }
1248
1249 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1250 {
1251 unsigned offset;
1252
1253 offset = 0x0003C000 + id * 0xc;
1254 r600_context_pipe_state_set_sampler(ctx, state, offset);
1255 offset = 0x0000A400 + id * 0x10;
1256 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1257 }
1258
1259 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1260 {
1261 unsigned offset;
1262
1263 offset = 0x0003C0D8 + id * 0xc;
1264 r600_context_pipe_state_set_sampler(ctx, state, offset);
1265 offset = 0x0000A600 + id * 0x10;
1266 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1267 }
1268
1269 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1270 {
1271 struct r600_range *range;
1272 struct r600_block *block;
1273 unsigned id;
1274
1275 range = &ctx->range[CTX_RANGE_ID(offset)];
1276 block = range->blocks[CTX_BLOCK_ID(offset)];
1277 offset -= block->start_offset;
1278 id = block->pm4_bo_index[offset >> 2];
1279 if (block->reloc[id].bo) {
1280 return block->reloc[id].bo;
1281 }
1282 return NULL;
1283 }
1284
1285 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1286 {
1287 int id;
1288 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1289 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1290 int new_dwords = 0;
1291 int nbo = block->nbo;
1292
1293 if (block->nreg_dirty == 0 && optional) {
1294 goto out;
1295 }
1296
1297 if (nbo) {
1298 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1299
1300 for (int j = 0; j < block->nreg; j++) {
1301 if (block->pm4_bo_index[j]) {
1302 /* find relocation */
1303 id = block->pm4_bo_index[j];
1304 block->pm4[block->reloc[id].bo_pm4_index] =
1305 r600_context_bo_reloc(ctx, block->reloc[id].bo);
1306 r600_context_bo_flush(ctx,
1307 block->reloc[id].flush_flags,
1308 block->reloc[id].flush_mask,
1309 block->reloc[id].bo);
1310 nbo--;
1311 if (nbo == 0)
1312 break;
1313 }
1314 }
1315 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1316 }
1317
1318 optional &= (block->nreg_dirty != block->nreg);
1319 if (optional) {
1320 new_dwords = block->nreg_dirty;
1321 start_dword = ctx->pm4_cdwords;
1322 cp_dwords = new_dwords + 2;
1323 }
1324 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1325 ctx->pm4_cdwords += cp_dwords;
1326
1327 if (optional) {
1328 uint32_t newword;
1329
1330 newword = ctx->pm4[start_dword];
1331 newword &= PKT_COUNT_C;
1332 newword |= PKT_COUNT_S(new_dwords);
1333 ctx->pm4[start_dword] = newword;
1334 }
1335 out:
1336 block->status ^= R600_BLOCK_STATUS_DIRTY;
1337 block->nreg_dirty = 0;
1338 LIST_DELINIT(&block->list);
1339 }
1340
1341 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1342 {
1343 int id;
1344 int cp_dwords = block->pm4_ndwords;
1345 int nbo = block->nbo;
1346
1347 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1348
1349 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1350 nbo = 1;
1351 cp_dwords -= 2; /* don't copy the second NOP */
1352 }
1353
1354 for (int j = 0; j < nbo; j++) {
1355 if (block->pm4_bo_index[j]) {
1356 /* find relocation */
1357 id = block->pm4_bo_index[j];
1358 block->pm4[block->reloc[id].bo_pm4_index] =
1359 r600_context_bo_reloc(ctx, block->reloc[id].bo);
1360 r600_context_bo_flush(ctx,
1361 block->reloc[id].flush_flags,
1362 block->reloc[id].flush_mask,
1363 block->reloc[id].bo);
1364 }
1365 }
1366 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1367
1368 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1369 ctx->pm4_cdwords += cp_dwords;
1370
1371 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1372 block->nreg_dirty = 0;
1373 LIST_DELINIT(&block->list);
1374 }
1375
1376 void r600_context_flush_dest_caches(struct r600_context *ctx)
1377 {
1378 struct r600_bo *cb[8];
1379 struct r600_bo *db;
1380 int i;
1381
1382 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1383 return;
1384
1385 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1386 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1387 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1388 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1389 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1390 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1391 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1392 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1393 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1394
1395 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1396 /* flush the color buffers */
1397 for (i = 0; i < 8; i++) {
1398 if (!cb[i])
1399 continue;
1400
1401 r600_context_bo_flush(ctx,
1402 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1403 S_0085F0_CB_ACTION_ENA(1),
1404 0, cb[i]);
1405 }
1406 if (db) {
1407 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1408 }
1409 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1410 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1411 }
1412
1413 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1414 {
1415 unsigned ndwords = 7;
1416 struct r600_block *dirty_block = NULL;
1417 struct r600_block *next_block;
1418 uint32_t *pm4;
1419
1420 if (draw->indices) {
1421 ndwords = 11;
1422 }
1423
1424 /* queries need some special values */
1425 if (ctx->num_query_running) {
1426 if (ctx->radeon->family >= CHIP_RV770) {
1427 r600_context_reg(ctx,
1428 R_028D0C_DB_RENDER_CONTROL,
1429 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1430 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1431 }
1432 r600_context_reg(ctx,
1433 R_028D10_DB_RENDER_OVERRIDE,
1434 S_028D10_NOOP_CULL_DISABLE(1),
1435 S_028D10_NOOP_CULL_DISABLE(1));
1436 }
1437
1438 /* update the max dword count to make sure we have enough space
1439 * reserved for flushing the destination caches */
1440 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4 - ctx->num_dest_buffers * 7 - 16;
1441
1442 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1443 /* need to flush */
1444 r600_context_flush(ctx);
1445 }
1446 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1447 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1448 R600_ERR("context is too big to be scheduled\n");
1449 return;
1450 }
1451 /* enough room to copy packet */
1452 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1453 r600_context_block_emit_dirty(ctx, dirty_block);
1454 }
1455
1456 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1457 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1458 }
1459
1460 /* draw packet */
1461 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1462
1463 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1464 pm4[1] = draw->vgt_index_type;
1465 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1466 pm4[3] = draw->vgt_num_instances;
1467 if (draw->indices) {
1468 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1469 pm4[5] = draw->indices_bo_offset;
1470 pm4[6] = 0;
1471 pm4[7] = draw->vgt_num_indices;
1472 pm4[8] = draw->vgt_draw_initiator;
1473 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1474 pm4[10] = r600_context_bo_reloc(ctx, draw->indices);
1475 } else {
1476 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1477 pm4[5] = draw->vgt_num_indices;
1478 pm4[6] = draw->vgt_draw_initiator;
1479 }
1480 ctx->pm4_cdwords += ndwords;
1481
1482 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1483
1484 /* all dirty state have been scheduled in current cs */
1485 ctx->pm4_dirty_cdwords = 0;
1486 }
1487
1488 void r600_context_flush(struct r600_context *ctx)
1489 {
1490 struct r600_block *enable_block = NULL;
1491
1492 if (ctx->pm4_cdwords == ctx->init_dwords)
1493 return;
1494
1495 /* suspend queries */
1496 r600_context_queries_suspend(ctx);
1497
1498 if (ctx->radeon->chip_class >= EVERGREEN)
1499 evergreen_context_flush_dest_caches(ctx);
1500 else
1501 r600_context_flush_dest_caches(ctx);
1502
1503 /* partial flush is needed to avoid lockups on some chips with user fences */
1504 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1505 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1506
1507 /* Flush the CS. */
1508 ctx->cs->cdw = ctx->pm4_cdwords;
1509 ctx->radeon->ws->cs_flush(ctx->cs, 0);
1510 /* We need to get the pointer to the other CS,
1511 * the command streams are double-buffered. */
1512 ctx->pm4 = ctx->cs->buf;
1513
1514 /* restart */
1515 for (int i = 0; i < ctx->creloc; i++) {
1516 ctx->bo[i]->last_flush = 0;
1517 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1518 }
1519 ctx->creloc = 0;
1520 ctx->pm4_dirty_cdwords = 0;
1521 ctx->pm4_cdwords = 0;
1522 ctx->flags = 0;
1523
1524 r600_init_cs(ctx);
1525
1526 /* resume queries */
1527 r600_context_queries_resume(ctx, TRUE);
1528
1529 /* set all valid group as dirty so they get reemited on
1530 * next draw command
1531 */
1532 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1533 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1534 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1535 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1536 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1537 }
1538 } else {
1539 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1540 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1541 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1542 }
1543 }
1544 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1545 enable_block->pm4_flush_ndwords;
1546 enable_block->nreg_dirty = enable_block->nreg;
1547 }
1548 }
1549
1550 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence_bo, unsigned offset, unsigned value)
1551 {
1552 unsigned ndwords = 10;
1553
1554 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1555 /* need to flush */
1556 r600_context_flush(ctx);
1557 }
1558
1559 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1560 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1561 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1562 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1563 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */
1564 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */
1565 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1566 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1567 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1568 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, fence_bo);
1569 }
1570
1571 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1572 {
1573 unsigned results_base = query->results_start;
1574 u64 start, end;
1575 u32 *results, *current_result;
1576
1577 if (wait)
1578 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_READ, NULL);
1579 else
1580 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_DONTBLOCK | PIPE_TRANSFER_READ, NULL);
1581 if (!results)
1582 return FALSE;
1583
1584
1585 /* count all results across all data blocks */
1586 while (results_base != query->results_end) {
1587 current_result = (u32*)((char*)results + results_base);
1588
1589 start = (u64)current_result[0] | (u64)current_result[1] << 32;
1590 end = (u64)current_result[2] | (u64)current_result[3] << 32;
1591 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))
1592 || query->type == PIPE_QUERY_TIME_ELAPSED) {
1593 query->result += end - start;
1594 }
1595
1596 results_base += 4 * 4;
1597 if (results_base >= query->buffer_size)
1598 results_base = 0;
1599 }
1600
1601 query->results_start = query->results_end;
1602 r600_bo_unmap(ctx->radeon, query->buffer);
1603 return TRUE;
1604 }
1605
1606 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1607 {
1608 unsigned required_space, new_results_end;
1609
1610 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */
1611 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1612 required_space = 16;
1613 else
1614 required_space = 12;
1615
1616 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1617 /* need to flush */
1618 r600_context_flush(ctx);
1619 }
1620
1621 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1622 /* Count queries emitted without flushes, and flush if more than
1623 * half of buffer used, to avoid overwriting results which may be
1624 * still in use. */
1625 if (query->state & R600_QUERY_STATE_FLUSHED) {
1626 query->queries_emitted = 1;
1627 } else {
1628 if (++query->queries_emitted > query->buffer_size / query->result_size / 2)
1629 r600_context_flush(ctx);
1630 }
1631 }
1632
1633 new_results_end = query->results_end + query->result_size;
1634 if (new_results_end >= query->buffer_size)
1635 new_results_end = 0;
1636
1637 /* collect current results if query buffer is full */
1638 if (new_results_end == query->results_start) {
1639 if (!(query->state & R600_QUERY_STATE_FLUSHED))
1640 r600_context_flush(ctx);
1641 r600_query_result(ctx, query, TRUE);
1642 }
1643
1644 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
1645 u32 *results;
1646 int i;
1647
1648 results = r600_bo_map(ctx->radeon, query->buffer, PIPE_TRANSFER_WRITE, NULL);
1649 if (results) {
1650 results = (u32*)((char*)results + query->results_end);
1651 memset(results, 0, query->result_size);
1652
1653 /* Set top bits for unused backends */
1654 for (i = 0; i < ctx->max_db; i++) {
1655 if (!(ctx->backend_mask & (1<<i))) {
1656 results[(i * 4)+1] = 0x80000000;
1657 results[(i * 4)+3] = 0x80000000;
1658 }
1659 }
1660 r600_bo_unmap(ctx->radeon, query->buffer);
1661 }
1662 }
1663
1664 /* emit begin query */
1665 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1666 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1667 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1668 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1669 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1670 ctx->pm4[ctx->pm4_cdwords++] = 0;
1671 ctx->pm4[ctx->pm4_cdwords++] = 0;
1672 } else {
1673 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1674 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1675 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1676 ctx->pm4[ctx->pm4_cdwords++] = 0;
1677 }
1678 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1679 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer);
1680
1681 query->state |= R600_QUERY_STATE_STARTED;
1682 query->state ^= R600_QUERY_STATE_ENDED;
1683 ctx->num_query_running++;
1684 }
1685
1686 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1687 {
1688 /* emit end query */
1689 if (query->type == PIPE_QUERY_TIME_ELAPSED) {
1690 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1691 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1692 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
1693 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29);
1694 ctx->pm4[ctx->pm4_cdwords++] = 0;
1695 ctx->pm4[ctx->pm4_cdwords++] = 0;
1696 } else {
1697 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1698 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1699 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8;
1700 ctx->pm4[ctx->pm4_cdwords++] = 0;
1701 }
1702 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1703 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer);
1704
1705 query->results_end += query->result_size;
1706 if (query->results_end >= query->buffer_size)
1707 query->results_end = 0;
1708
1709 query->state ^= R600_QUERY_STATE_STARTED;
1710 query->state |= R600_QUERY_STATE_ENDED;
1711 query->state &= ~R600_QUERY_STATE_FLUSHED;
1712
1713 ctx->num_query_running--;
1714 }
1715
1716 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1717 int flag_wait)
1718 {
1719 if (operation == PREDICATION_OP_CLEAR) {
1720 if (ctx->pm4_cdwords + 3 > ctx->pm4_ndwords)
1721 r600_context_flush(ctx);
1722
1723 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1724 ctx->pm4[ctx->pm4_cdwords++] = 0;
1725 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1726 } else {
1727 unsigned results_base = query->results_start;
1728 unsigned count;
1729 u32 op;
1730
1731 /* find count of the query data blocks */
1732 count = query->buffer_size + query->results_end - query->results_start;
1733 if (count >= query->buffer_size) count-=query->buffer_size;
1734 count /= query->result_size;
1735
1736 if (ctx->pm4_cdwords + 5 * count > ctx->pm4_ndwords)
1737 r600_context_flush(ctx);
1738
1739 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
1740 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
1741
1742 /* emit predicate packets for all data blocks */
1743 while (results_base != query->results_end) {
1744 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1745 ctx->pm4[ctx->pm4_cdwords++] = results_base;
1746 ctx->pm4[ctx->pm4_cdwords++] = op;
1747 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1748 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer);
1749 results_base += query->result_size;
1750 if (results_base >= query->buffer_size)
1751 results_base = 0;
1752 /* set CONTINUE bit for all packets except the first */
1753 op |= PREDICATION_CONTINUE;
1754 }
1755 }
1756 }
1757
1758 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1759 {
1760 struct r600_query *query;
1761
1762 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER && query_type != PIPE_QUERY_TIME_ELAPSED)
1763 return NULL;
1764
1765 query = calloc(1, sizeof(struct r600_query));
1766 if (query == NULL)
1767 return NULL;
1768
1769 query->type = query_type;
1770 query->buffer_size = 4096;
1771
1772 if (query_type == PIPE_QUERY_OCCLUSION_COUNTER)
1773 query->result_size = 4 * 4 * ctx->max_db;
1774 else
1775 query->result_size = 4 * 4;
1776
1777 /* adjust buffer size to simplify offsets wrapping math */
1778 query->buffer_size -= query->buffer_size % query->result_size;
1779
1780 /* As of GL4, query buffers are normally read by the CPU after
1781 * being written by the gpu, hence staging is probably a good
1782 * usage pattern.
1783 */
1784 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1785 PIPE_USAGE_STAGING);
1786 if (!query->buffer) {
1787 free(query);
1788 return NULL;
1789 }
1790
1791 LIST_ADDTAIL(&query->list, &ctx->query_list);
1792
1793 return query;
1794 }
1795
1796 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1797 {
1798 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1799 LIST_DELINIT(&query->list);
1800 free(query);
1801 }
1802
1803 boolean r600_context_query_result(struct r600_context *ctx,
1804 struct r600_query *query,
1805 boolean wait, void *vresult)
1806 {
1807 uint64_t *result = (uint64_t*)vresult;
1808
1809 if (!(query->state & R600_QUERY_STATE_FLUSHED)) {
1810 r600_context_flush(ctx);
1811 }
1812 if (!r600_query_result(ctx, query, wait))
1813 return FALSE;
1814 if (query->type == PIPE_QUERY_TIME_ELAPSED)
1815 *result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
1816 else
1817 *result = query->result;
1818 query->result = 0;
1819 return TRUE;
1820 }
1821
1822 void r600_context_queries_suspend(struct r600_context *ctx)
1823 {
1824 struct r600_query *query;
1825
1826 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1827 if (query->state & R600_QUERY_STATE_STARTED) {
1828 r600_query_end(ctx, query);
1829 query->state |= R600_QUERY_STATE_SUSPENDED;
1830 }
1831 }
1832 }
1833
1834 void r600_context_queries_resume(struct r600_context *ctx, boolean flushed)
1835 {
1836 struct r600_query *query;
1837
1838 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1839 if (flushed)
1840 query->state |= R600_QUERY_STATE_FLUSHED;
1841
1842 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1843 r600_query_begin(ctx, query);
1844 query->state ^= R600_QUERY_STATE_SUSPENDED;
1845 }
1846 }
1847 }