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Merge branch 'lp-offset-twoside'
[mesa.git] / src / gallium / winsys / r600 / drm / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <errno.h>
27 #include <stdint.h>
28 #include <string.h>
29 #include <stdlib.h>
30 #include <assert.h>
31 #include "xf86drm.h"
32 #include "r600.h"
33 #include "r600d.h"
34 #include "radeon_drm.h"
35 #include "bof.h"
36 #include "pipe/p_compiler.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include <pipebuffer/pb_bufmgr.h>
40 #include "r600_priv.h"
41
42 #define GROUP_FORCE_NEW_BLOCK 0
43
44 int r600_context_init_fence(struct r600_context *ctx)
45 {
46 ctx->fence = 1;
47 ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
48 if (ctx->fence_bo == NULL) {
49 return -ENOMEM;
50 }
51 ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL);
52 *ctx->cfence = 0;
53 LIST_INITHEAD(&ctx->fenced_bo);
54 return 0;
55 }
56
57 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
58 {
59 for (int i = 0; i < ctx->creloc; i++) {
60 if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist))
61 LIST_DELINIT(&ctx->bo[i]->fencedlist);
62 LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo);
63 ctx->bo[i]->fence = ctx->fence;
64 ctx->bo[i]->ctx = ctx;
65 }
66 }
67
68 static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence)
69 {
70 struct radeon_bo *bo = NULL;
71 struct radeon_bo *tmp;
72
73 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
74 if (bo->fence <= *ctx->cfence) {
75 LIST_DELINIT(&bo->fencedlist);
76 bo->fence = 0;
77 } else {
78 bo->fence = fence;
79 }
80 }
81 }
82
83 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
84 {
85 struct r600_block *block;
86 struct r600_range *range;
87 int offset;
88
89 for (unsigned i = 0, n = 0; i < nreg; i += n) {
90 u32 j;
91
92 /* ignore new block balise */
93 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
94 n = 1;
95 continue;
96 }
97
98 /* register that need relocation are in their own group */
99 /* find number of consecutive registers */
100 n = 0;
101 offset = reg[i].offset;
102 while (reg[i + n].offset == offset) {
103 n++;
104 offset += 4;
105 if ((n + i) >= nreg)
106 break;
107 if (n >= (R600_BLOCK_MAX_REG - 2))
108 break;
109 }
110
111 /* allocate new block */
112 block = calloc(1, sizeof(struct r600_block));
113 if (block == NULL) {
114 return -ENOMEM;
115 }
116 ctx->nblocks++;
117 for (int j = 0; j < n; j++) {
118 range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
119 range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
120 }
121
122 /* initialize block */
123 block->start_offset = reg[i].offset;
124 block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n);
125 block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
126 block->reg = &block->pm4[block->pm4_ndwords];
127 block->pm4_ndwords += n;
128 block->nreg = n;
129 LIST_INITHEAD(&block->list);
130
131 for (j = 0; j < n; j++) {
132 if (reg[i+j].need_bo) {
133 block->nbo++;
134 assert(block->nbo < R600_BLOCK_MAX_BO);
135 block->pm4_bo_index[j] = block->nbo;
136 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
137 block->pm4[block->pm4_ndwords++] = 0x00000000;
138 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
139 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
140 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
141 }
142 }
143 for (j = 0; j < n; j++) {
144 if (reg[i+j].flush_flags) {
145 block->pm4_flush_ndwords += 7;
146 }
147 }
148 /* check that we stay in limit */
149 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
150 }
151 return 0;
152 }
153
154 /* R600/R700 configuration */
155 static const struct r600_reg r600_config_reg_list[] = {
156 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
157 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
158 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
159 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
160 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
161 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
162 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
163 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
164 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
165 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
166 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
167 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
168 };
169
170 static const struct r600_reg r600_ctl_const_list[] = {
171 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
172 {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
173 };
174
175 static const struct r600_reg r600_context_reg_list[] = {
176 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
177 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
178 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
179 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
180 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
181 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
182 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
183 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
184 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
185 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
186 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
187 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
188 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
189 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
190 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
191 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
192 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
193 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
194 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
195 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
196 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
197 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
198 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
199 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
200 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
201 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
202 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
203 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
204 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
205 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
206 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
207 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
208 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0, 0},
209 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
210 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF},
211 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
212 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
213 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
214 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0, 0},
215 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
216 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0, 0},
217 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
218 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
219 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0, 0},
220 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
221 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF},
222 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
223 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
224 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
225 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0, 0},
226 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
227 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0, 0},
228 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
229 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
230 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0, 0},
231 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
232 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF},
233 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
234 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
235 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
236 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0, 0},
237 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
238 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0, 0},
239 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
240 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
241 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0, 0},
242 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
243 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF},
244 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
245 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
246 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
247 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0, 0},
248 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
249 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0, 0},
250 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
251 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
252 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0, 0},
253 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
254 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF},
255 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
256 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
257 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
258 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0, 0},
259 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
260 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0, 0},
261 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
262 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
263 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0, 0},
264 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
265 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF},
266 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
267 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
268 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
269 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0, 0},
270 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
271 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0, 0},
272 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
273 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0, 0},
274 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF},
275 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
276 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
277 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
278 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0, 0},
279 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
280 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0, 0},
281 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
282 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
283 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0, 0},
284 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
285 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF},
286 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
287 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
288 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0, 0},
289 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0, 0},
290 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
291 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
292 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
293 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
294 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
295 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0},
296 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0},
297 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
298 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
299 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
300 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
301 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
302 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
303 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
304 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
305 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
306 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
307 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
308 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
309 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
310 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
311 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
312 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
313 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
314 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
315 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
316 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
317 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
318 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
319 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
320 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
321 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
322 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
323 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
324 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
325 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
326 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
327 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
328 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
329 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
330 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
331 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
332 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
333 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
334 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
335 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
336 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
337 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
338 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0, 0},
339 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
340 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
341 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
342 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0, 0},
343 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
344 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
345 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
346 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
347 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
348 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
349 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
350 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
351 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
352 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
353 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
354 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
355 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
356 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
357 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
358 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
359 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
360 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
361 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
362 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
363 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
364 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
365 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
366 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
367 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
368 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
369 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
370 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
371 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
372 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
373 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
374 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
375 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
376 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
377 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
378 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
379 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
380 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
381 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
382 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
383 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
384 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
385 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
386 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
387 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
388 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
389 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
390 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
391 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
392 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
393 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
394 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
395 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
396 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
397 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
398 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
399 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
400 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
401 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
402 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
403 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
404 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
405 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
406 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
407 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
408 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
409 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
410 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
411 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
412 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
413 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
414 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
415 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
416 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
417 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
418 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
419 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
420 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
421 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
422 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
423 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
424 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
425 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
426 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
427 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
428 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
429 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
430 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
431 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
432 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
433 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
434 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
435 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
436 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
437 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
438 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
439 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
440 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
441 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
442 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
443 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
444 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
445 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
446 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
447 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
448 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
449 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
450 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
451 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
452 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
453 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
454 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
455 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
456 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
457 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
458 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
459 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
460 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
461 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
462 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
463 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
464 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
465 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
466 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
467 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
468 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
469 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
470 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
471 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
472 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
473 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
474 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
475 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
476 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
477 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
478 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
479 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
480 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
481 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
482 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
483 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
484 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
485 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
486 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
487 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
488 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
489 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
490 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
491 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
492 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
493 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
494 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
495 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
496 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
497 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
498 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
499 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
500 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
501 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
502 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
503 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
504 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
505 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
506 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
507 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
508 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
509 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
510 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
511 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
512 {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
513 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
514 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
515 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
516 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
517 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
518 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
519 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
520 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
521 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
522 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
523 {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
524 };
525
526 /* SHADER RESOURCE R600/R700 */
527 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
528 {
529 struct r600_reg r600_shader_resource[] = {
530 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
531 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
532 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
533 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
534 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
535 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
536 {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
537 };
538 unsigned nreg = Elements(r600_shader_resource);
539
540 for (int i = 0; i < nreg; i++) {
541 r600_shader_resource[i].offset += offset;
542 }
543 return r600_context_add_block(ctx, r600_shader_resource, nreg);
544 }
545
546 /* SHADER SAMPLER R600/R700 */
547 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
548 {
549 struct r600_reg r600_shader_sampler[] = {
550 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
551 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
552 {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
553 };
554 unsigned nreg = Elements(r600_shader_sampler);
555
556 for (int i = 0; i < nreg; i++) {
557 r600_shader_sampler[i].offset += offset;
558 }
559 return r600_context_add_block(ctx, r600_shader_sampler, nreg);
560 }
561
562 /* SHADER SAMPLER BORDER R600/R700 */
563 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
564 {
565 struct r600_reg r600_shader_sampler_border[] = {
566 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
567 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
568 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
569 {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
570 };
571 unsigned nreg = Elements(r600_shader_sampler_border);
572
573 for (int i = 0; i < nreg; i++) {
574 r600_shader_sampler_border[i].offset += offset;
575 }
576 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
577 }
578
579 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
580 {
581 unsigned nreg = 32;
582 struct r600_reg r600_loop_consts[32];
583 int i;
584
585 for (i = 0; i < nreg; i++) {
586 r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
587 r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
588 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
589 r600_loop_consts[i].need_bo = 0;
590 r600_loop_consts[i].flush_flags = 0;
591 r600_loop_consts[i].flush_mask = 0;
592 }
593 return r600_context_add_block(ctx, r600_loop_consts, nreg);
594 }
595
596 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
597 {
598 struct radeon_bo *bo, *tmp;
599
600 LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) {
601 LIST_DELINIT(&bo->fencedlist);
602 bo->fence = 0;
603 bo->ctx = NULL;
604 }
605 }
606
607 /* initialize */
608 void r600_context_fini(struct r600_context *ctx)
609 {
610 struct r600_block *block;
611 struct r600_range *range;
612
613 for (int i = 0; i < 256; i++) {
614 for (int j = 0; j < (1 << ctx->hash_shift); j++) {
615 block = ctx->range[i].blocks[j];
616 if (block) {
617 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
618 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
619 range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
620 }
621 free(block);
622 }
623 }
624 free(ctx->range[i].blocks);
625 }
626 free(ctx->blocks);
627 free(ctx->reloc);
628 free(ctx->bo);
629 free(ctx->pm4);
630
631 r600_context_clear_fenced_bo(ctx);
632 if (ctx->fence_bo) {
633 r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL);
634 }
635 memset(ctx, 0, sizeof(struct r600_context));
636 }
637
638 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
639 {
640 int r;
641
642 memset(ctx, 0, sizeof(struct r600_context));
643 ctx->radeon = radeon;
644 LIST_INITHEAD(&ctx->query_list);
645
646 /* initialize hash */
647 ctx->hash_size = 19;
648 ctx->hash_shift = 11;
649 for (int i = 0; i < 256; i++) {
650 ctx->range[i].start_offset = i << ctx->hash_shift;
651 ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
652 ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
653 if (ctx->range[i].blocks == NULL) {
654 return -ENOMEM;
655 }
656 }
657
658 /* add blocks */
659 r = r600_context_add_block(ctx, r600_config_reg_list,
660 Elements(r600_config_reg_list));
661 if (r)
662 goto out_err;
663 r = r600_context_add_block(ctx, r600_context_reg_list,
664 Elements(r600_context_reg_list));
665 if (r)
666 goto out_err;
667 r = r600_context_add_block(ctx, r600_ctl_const_list,
668 Elements(r600_ctl_const_list));
669 if (r)
670 goto out_err;
671
672 /* PS SAMPLER BORDER */
673 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
674 r = r600_state_sampler_border_init(ctx, offset);
675 if (r)
676 goto out_err;
677 }
678
679 /* VS SAMPLER BORDER */
680 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
681 r = r600_state_sampler_border_init(ctx, offset);
682 if (r)
683 goto out_err;
684 }
685 /* PS SAMPLER */
686 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
687 r = r600_state_sampler_init(ctx, offset);
688 if (r)
689 goto out_err;
690 }
691 /* VS SAMPLER */
692 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
693 r = r600_state_sampler_init(ctx, offset);
694 if (r)
695 goto out_err;
696 }
697 /* PS RESOURCE */
698 for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
699 r = r600_state_resource_init(ctx, offset);
700 if (r)
701 goto out_err;
702 }
703 /* VS RESOURCE */
704 for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
705 r = r600_state_resource_init(ctx, offset);
706 if (r)
707 goto out_err;
708 }
709 /* FS RESOURCE */
710 for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
711 r = r600_state_resource_init(ctx, offset);
712 if (r)
713 goto out_err;
714 }
715
716 /* PS loop const */
717 r600_loop_const_init(ctx, 0);
718 /* VS loop const */
719 r600_loop_const_init(ctx, 32);
720
721 /* setup block table */
722 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
723 for (int i = 0, c = 0; i < 256; i++) {
724 for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
725 if (ctx->range[i].blocks[j]) {
726 add = 1;
727 for (int k = 0; k < c; k++) {
728 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
729 add = 0;
730 break;
731 }
732 }
733 if (add) {
734 assert(c < ctx->nblocks);
735 ctx->blocks[c++] = ctx->range[i].blocks[j];
736 j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
737 }
738 }
739 }
740 }
741
742 /* allocate cs variables */
743 ctx->nreloc = RADEON_CTX_MAX_PM4;
744 ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
745 if (ctx->reloc == NULL) {
746 r = -ENOMEM;
747 goto out_err;
748 }
749 ctx->bo = calloc(ctx->nreloc, sizeof(void *));
750 if (ctx->bo == NULL) {
751 r = -ENOMEM;
752 goto out_err;
753 }
754 ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
755 ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
756 if (ctx->pm4 == NULL) {
757 r = -ENOMEM;
758 goto out_err;
759 }
760 /* save 16dwords space for fence mecanism */
761 ctx->pm4_ndwords -= 16;
762
763 r = r600_context_init_fence(ctx);
764 if (r) {
765 goto out_err;
766 }
767
768 /* init dirty list */
769 LIST_INITHEAD(&ctx->dirty);
770 return 0;
771 out_err:
772 r600_context_fini(ctx);
773 return r;
774 }
775
776 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
777 unsigned flush_mask, struct r600_bo *rbo)
778 {
779 struct radeon_bo *bo;
780
781 bo = r600_bo_get_bo(rbo);
782 /* if bo has already been flush */
783 if (!(bo->last_flush ^ flush_flags)) {
784 bo->last_flush &= flush_mask;
785 return;
786 }
787 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
788 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
789 ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8;
790 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
791 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
792 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
793 ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id;
794 bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
795 }
796
797 void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
798 {
799 struct radeon_bo *bo;
800
801 bo = r600_bo_get_bo(rbo);
802 assert(bo != NULL);
803 if (bo->reloc) {
804 *pm4 = bo->reloc_id;
805 return;
806 }
807 bo->reloc = &ctx->reloc[ctx->creloc];
808 bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
809 ctx->reloc[ctx->creloc].handle = bo->handle;
810 ctx->reloc[ctx->creloc].read_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
811 ctx->reloc[ctx->creloc].write_domain = rbo->domains & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM);
812 ctx->reloc[ctx->creloc].flags = 0;
813 radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
814 ctx->creloc++;
815 /* set PKT3 to point to proper reloc */
816 *pm4 = bo->reloc_id;
817 }
818
819 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
820 {
821 struct r600_range *range;
822 struct r600_block *block;
823
824 for (int i = 0; i < state->nregs; i++) {
825 unsigned id;
826
827 range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
828 block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
829 id = (state->regs[i].offset - block->start_offset) >> 2;
830 block->reg[id] &= ~state->regs[i].mask;
831 block->reg[id] |= state->regs[i].value;
832 if (block->pm4_bo_index[id]) {
833 /* find relocation */
834 id = block->pm4_bo_index[id];
835 r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
836 }
837 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
838 block->status |= R600_BLOCK_STATUS_ENABLED;
839 block->status |= R600_BLOCK_STATUS_DIRTY;
840 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
841 LIST_ADDTAIL(&block->list,&ctx->dirty);
842 }
843 }
844 }
845
846 static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
847 {
848 struct r600_range *range;
849 struct r600_block *block;
850
851 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
852 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
853 if (state == NULL) {
854 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
855 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
856 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
857 LIST_DELINIT(&block->list);
858 return;
859 }
860 block->reg[0] = state->regs[0].value;
861 block->reg[1] = state->regs[1].value;
862 block->reg[2] = state->regs[2].value;
863 block->reg[3] = state->regs[3].value;
864 block->reg[4] = state->regs[4].value;
865 block->reg[5] = state->regs[5].value;
866 block->reg[6] = state->regs[6].value;
867 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
868 r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
869 if (state->regs[0].bo) {
870 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
871 * we have single case btw VERTEX & TEXTURE resource
872 */
873 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
874 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
875 } else {
876 /* TEXTURE RESOURCE */
877 r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
878 r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
879 }
880 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
881 block->status |= R600_BLOCK_STATUS_ENABLED;
882 block->status |= R600_BLOCK_STATUS_DIRTY;
883 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
884 LIST_ADDTAIL(&block->list,&ctx->dirty);
885 }
886 }
887
888 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
889 {
890 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
891
892 r600_context_pipe_state_set_resource(ctx, state, offset);
893 }
894
895 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
896 {
897 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
898
899 r600_context_pipe_state_set_resource(ctx, state, offset);
900 }
901
902 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
903 {
904 unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
905
906 r600_context_pipe_state_set_resource(ctx, state, offset);
907 }
908
909 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
910 {
911 struct r600_range *range;
912 struct r600_block *block;
913
914 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
915 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
916 if (state == NULL) {
917 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
918 LIST_DELINIT(&block->list);
919 return;
920 }
921 block->reg[0] = state->regs[0].value;
922 block->reg[1] = state->regs[1].value;
923 block->reg[2] = state->regs[2].value;
924 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
925 block->status |= R600_BLOCK_STATUS_ENABLED;
926 block->status |= R600_BLOCK_STATUS_DIRTY;
927 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
928 LIST_ADDTAIL(&block->list,&ctx->dirty);
929 }
930 }
931
932 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
933 {
934 struct r600_range *range;
935 struct r600_block *block;
936
937 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
938 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
939 if (state == NULL) {
940 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
941 LIST_DELINIT(&block->list);
942 return;
943 }
944 if (state->nregs <= 3) {
945 return;
946 }
947 block->reg[0] = state->regs[3].value;
948 block->reg[1] = state->regs[4].value;
949 block->reg[2] = state->regs[5].value;
950 block->reg[3] = state->regs[6].value;
951 if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
952 block->status |= R600_BLOCK_STATUS_ENABLED;
953 block->status |= R600_BLOCK_STATUS_DIRTY;
954 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
955 LIST_ADDTAIL(&block->list,&ctx->dirty);
956 }
957 }
958
959 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
960 {
961 unsigned offset;
962
963 offset = 0x0003C000 + id * 0xc;
964 r600_context_pipe_state_set_sampler(ctx, state, offset);
965 offset = 0x0000A400 + id * 0x10;
966 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
967 }
968
969 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
970 {
971 unsigned offset;
972
973 offset = 0x0003C0D8 + id * 0xc;
974 r600_context_pipe_state_set_sampler(ctx, state, offset);
975 offset = 0x0000A600 + id * 0x10;
976 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
977 }
978
979 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
980 {
981 struct r600_range *range;
982 struct r600_block *block;
983 unsigned id;
984
985 range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
986 block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
987 offset -= block->start_offset;
988 id = block->pm4_bo_index[offset >> 2];
989 if (block->reloc[id].bo) {
990 return block->reloc[id].bo;
991 }
992 return NULL;
993 }
994
995 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
996 {
997 struct r600_bo *cb[8];
998 struct r600_bo *db;
999 unsigned ndwords = 9;
1000 struct r600_block *dirty_block = NULL;
1001 struct r600_block *next_block;
1002
1003 if (draw->indices) {
1004 ndwords = 13;
1005 /* make sure there is enough relocation space before scheduling draw */
1006 if (ctx->creloc >= (ctx->nreloc - 1)) {
1007 r600_context_flush(ctx);
1008 }
1009 }
1010
1011 /* find number of color buffer */
1012 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1013 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1014 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1015 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1016 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1017 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1018 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1019 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1020 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1021 for (int i = 0; i < 8; i++) {
1022 if (cb[i]) {
1023 ndwords += 7;
1024 }
1025 }
1026 if (db)
1027 ndwords += 7;
1028
1029 /* queries need some special values */
1030 if (ctx->num_query_running) {
1031 if (ctx->radeon->family >= CHIP_RV770) {
1032 r600_context_reg(ctx,
1033 R_028D0C_DB_RENDER_CONTROL,
1034 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1035 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1036 }
1037 r600_context_reg(ctx,
1038 R_028D10_DB_RENDER_OVERRIDE,
1039 S_028D10_NOOP_CULL_DISABLE(1),
1040 S_028D10_NOOP_CULL_DISABLE(1));
1041 }
1042
1043 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1044 /* need to flush */
1045 r600_context_flush(ctx);
1046 }
1047 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
1048 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
1049 R600_ERR("context is too big to be scheduled\n");
1050 return;
1051 }
1052
1053 /* enough room to copy packet */
1054 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) {
1055 r600_context_block_emit_dirty(ctx, dirty_block);
1056 }
1057
1058 /* draw packet */
1059 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
1060 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
1061 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
1062 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
1063 if (draw->indices) {
1064 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
1065 ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
1066 ctx->pm4[ctx->pm4_cdwords++] = 0;
1067 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1068 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1069 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1070 ctx->pm4[ctx->pm4_cdwords++] = 0;
1071 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
1072 } else {
1073 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
1074 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
1075 ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
1076 }
1077 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
1078 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
1079
1080 /* flush color buffer */
1081 for (int i = 0; i < 8; i++) {
1082 if (cb[i]) {
1083 r600_context_bo_flush(ctx,
1084 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1085 S_0085F0_CB_ACTION_ENA(1),
1086 0, cb[i]);
1087 }
1088 }
1089 if (db) {
1090 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
1091 }
1092
1093 /* all dirty state have been scheduled in current cs */
1094 ctx->pm4_dirty_cdwords = 0;
1095 }
1096
1097 void r600_context_flush(struct r600_context *ctx)
1098 {
1099 struct drm_radeon_cs drmib;
1100 struct drm_radeon_cs_chunk chunks[2];
1101 uint64_t chunk_array[2];
1102 unsigned fence;
1103 int r;
1104
1105 if (!ctx->pm4_cdwords)
1106 return;
1107
1108 /* suspend queries */
1109 r600_context_queries_suspend(ctx);
1110
1111 radeon_bo_pbmgr_flush_maps(ctx->radeon->kman);
1112
1113 /* emit fence */
1114 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4);
1115 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1116 ctx->pm4[ctx->pm4_cdwords++] = 0;
1117 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24);
1118 ctx->pm4[ctx->pm4_cdwords++] = ctx->fence;
1119 ctx->pm4[ctx->pm4_cdwords++] = 0;
1120 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1121 ctx->pm4[ctx->pm4_cdwords++] = 0;
1122 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->fence_bo);
1123
1124 #if 1
1125 /* emit cs */
1126 drmib.num_chunks = 2;
1127 drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
1128 chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
1129 chunks[0].length_dw = ctx->pm4_cdwords;
1130 chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
1131 chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
1132 chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
1133 chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
1134 chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
1135 chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
1136 r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
1137 sizeof(struct drm_radeon_cs));
1138 #else
1139 *ctx->cfence = ctx->fence;
1140 #endif
1141
1142 r600_context_update_fenced_list(ctx);
1143
1144 fence = ctx->fence + 1;
1145 if (fence < ctx->fence) {
1146 /* wrap around */
1147 fence = 1;
1148 r600_context_fence_wraparound(ctx, fence);
1149 }
1150 ctx->fence = fence;
1151
1152 /* restart */
1153 for (int i = 0; i < ctx->creloc; i++) {
1154 ctx->bo[i]->reloc = NULL;
1155 ctx->bo[i]->last_flush = 0;
1156 radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
1157 }
1158 ctx->creloc = 0;
1159 ctx->pm4_dirty_cdwords = 0;
1160 ctx->pm4_cdwords = 0;
1161
1162 /* resume queries */
1163 r600_context_queries_resume(ctx);
1164
1165 /* set all valid group as dirty so they get reemited on
1166 * next draw command
1167 */
1168 for (int i = 0; i < ctx->nblocks; i++) {
1169 if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
1170 if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
1171 LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
1172 }
1173 ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
1174 ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
1175 }
1176 }
1177 }
1178
1179 void r600_context_dump_bof(struct r600_context *ctx, const char *file)
1180 {
1181 bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
1182 unsigned i;
1183
1184 root = device_id = bcs = blob = array = bo = size = handle = NULL;
1185 root = bof_object();
1186 if (root == NULL)
1187 goto out_err;
1188 device_id = bof_int32(ctx->radeon->device);
1189 if (device_id == NULL)
1190 goto out_err;
1191 if (bof_object_set(root, "device_id", device_id))
1192 goto out_err;
1193 bof_decref(device_id);
1194 device_id = NULL;
1195 /* dump relocs */
1196 blob = bof_blob(ctx->creloc * 16, ctx->reloc);
1197 if (blob == NULL)
1198 goto out_err;
1199 if (bof_object_set(root, "reloc", blob))
1200 goto out_err;
1201 bof_decref(blob);
1202 blob = NULL;
1203 /* dump cs */
1204 blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
1205 if (blob == NULL)
1206 goto out_err;
1207 if (bof_object_set(root, "pm4", blob))
1208 goto out_err;
1209 bof_decref(blob);
1210 blob = NULL;
1211 /* dump bo */
1212 array = bof_array();
1213 if (array == NULL)
1214 goto out_err;
1215 for (i = 0; i < ctx->creloc; i++) {
1216 struct radeon_bo *rbo = ctx->bo[i];
1217 bo = bof_object();
1218 if (bo == NULL)
1219 goto out_err;
1220 size = bof_int32(rbo->size);
1221 if (size == NULL)
1222 goto out_err;
1223 if (bof_object_set(bo, "size", size))
1224 goto out_err;
1225 bof_decref(size);
1226 size = NULL;
1227 handle = bof_int32(rbo->handle);
1228 if (handle == NULL)
1229 goto out_err;
1230 if (bof_object_set(bo, "handle", handle))
1231 goto out_err;
1232 bof_decref(handle);
1233 handle = NULL;
1234 radeon_bo_map(ctx->radeon, rbo);
1235 blob = bof_blob(rbo->size, rbo->data);
1236 radeon_bo_unmap(ctx->radeon, rbo);
1237 if (blob == NULL)
1238 goto out_err;
1239 if (bof_object_set(bo, "data", blob))
1240 goto out_err;
1241 bof_decref(blob);
1242 blob = NULL;
1243 if (bof_array_append(array, bo))
1244 goto out_err;
1245 bof_decref(bo);
1246 bo = NULL;
1247 }
1248 if (bof_object_set(root, "bo", array))
1249 goto out_err;
1250 bof_dump_file(root, file);
1251 out_err:
1252 bof_decref(blob);
1253 bof_decref(array);
1254 bof_decref(bo);
1255 bof_decref(size);
1256 bof_decref(handle);
1257 bof_decref(device_id);
1258 bof_decref(root);
1259 }
1260
1261 static void r600_query_result(struct r600_context *ctx, struct r600_query *query)
1262 {
1263 u64 start, end;
1264 u32 *results;
1265 int i;
1266
1267 results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL);
1268 for (i = 0; i < query->num_results; i += 4) {
1269 start = (u64)results[i] | (u64)results[i + 1] << 32;
1270 end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
1271 if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
1272 query->result += end - start;
1273 }
1274 }
1275 r600_bo_unmap(ctx->radeon, query->buffer);
1276 query->num_results = 0;
1277 }
1278
1279 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1280 {
1281 /* query request needs 6 dwords for begin + 6 dwords for end */
1282 if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
1283 /* need to flush */
1284 r600_context_flush(ctx);
1285 }
1286
1287 /* if query buffer is full force a flush */
1288 if (query->num_results >= ((query->buffer_size >> 2) - 2)) {
1289 r600_context_flush(ctx);
1290 r600_query_result(ctx, query);
1291 }
1292
1293 /* emit begin query */
1294 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1295 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1296 ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer);
1297 ctx->pm4[ctx->pm4_cdwords++] = 0;
1298 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1299 ctx->pm4[ctx->pm4_cdwords++] = 0;
1300 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1301
1302 query->state |= R600_QUERY_STATE_STARTED;
1303 query->state ^= R600_QUERY_STATE_ENDED;
1304 ctx->num_query_running++;
1305 }
1306
1307 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1308 {
1309 /* emit begin query */
1310 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
1311 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1312 ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer);
1313 ctx->pm4[ctx->pm4_cdwords++] = 0;
1314 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
1315 ctx->pm4[ctx->pm4_cdwords++] = 0;
1316 r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
1317
1318 query->num_results += 16;
1319 query->state ^= R600_QUERY_STATE_STARTED;
1320 query->state |= R600_QUERY_STATE_ENDED;
1321 ctx->num_query_running--;
1322 }
1323
1324 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1325 {
1326 struct r600_query *query;
1327
1328 if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
1329 return NULL;
1330
1331 query = calloc(1, sizeof(struct r600_query));
1332 if (query == NULL)
1333 return NULL;
1334
1335 query->type = query_type;
1336 query->buffer_size = 4096;
1337
1338 /* As of GL4, query buffers are normally read by the CPU after
1339 * being written by the gpu, hence staging is probably a good
1340 * usage pattern.
1341 */
1342 query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0,
1343 PIPE_USAGE_STAGING);
1344 if (!query->buffer) {
1345 free(query);
1346 return NULL;
1347 }
1348
1349 LIST_ADDTAIL(&query->list, &ctx->query_list);
1350
1351 return query;
1352 }
1353
1354 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1355 {
1356 r600_bo_reference(ctx->radeon, &query->buffer, NULL);
1357 LIST_DELINIT(&query->list);
1358 free(query);
1359 }
1360
1361 boolean r600_context_query_result(struct r600_context *ctx,
1362 struct r600_query *query,
1363 boolean wait, void *vresult)
1364 {
1365 uint64_t *result = (uint64_t*)vresult;
1366
1367 if (query->num_results) {
1368 r600_context_flush(ctx);
1369 }
1370 r600_query_result(ctx, query);
1371 *result = query->result;
1372 query->result = 0;
1373 return TRUE;
1374 }
1375
1376 void r600_context_queries_suspend(struct r600_context *ctx)
1377 {
1378 struct r600_query *query;
1379
1380 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1381 if (query->state & R600_QUERY_STATE_STARTED) {
1382 r600_query_end(ctx, query);
1383 query->state |= R600_QUERY_STATE_SUSPENDED;
1384 }
1385 }
1386 }
1387
1388 void r600_context_queries_resume(struct r600_context *ctx)
1389 {
1390 struct r600_query *query;
1391
1392 LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
1393 if (query->state & R600_QUERY_STATE_SUSPENDED) {
1394 r600_query_begin(ctx, query);
1395 query->state ^= R600_QUERY_STATE_SUSPENDED;
1396 }
1397 }
1398 }