src/gallium/winsys/r600/drm/r600_states.h

   1 /*
   2  * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software Foundation,
  15  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  16  */
  17 #ifndef R600_STATES_H
  18 #define R600_STATES_H
  19
  20 static const struct radeon_register R600_names_CONFIG[] = {
  21         {0x00008C00, 0, 0, "SQ_CONFIG"},
  22         {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
  23         {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
  24         {0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
  25         {0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
  26         {0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
  27         {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
  28         {0x00009508, 0, 0, "TA_CNTL_AUX"},
  29         {0x00009714, 0, 0, "VC_ENHANCE"},
  30         {0x00009830, 0, 0, "DB_DEBUG"},
  31         {0x00009838, 0, 0, "DB_WATERMARKS"},
  32         {0x00028350, 0, 0, "SX_MISC"},
  33         {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
  34         {0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
  35         {0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
  36         {0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
  37         {0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
  38         {0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
  39         {0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
  40         {0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
  41         {0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
  42         {0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
  43         {0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
  44         {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
  45         {0x00028A14, 0, 0, "VGT_HOS_CNTL"},
  46         {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
  47         {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
  48         {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
  49         {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
  50         {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
  51         {0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
  52         {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
  53         {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
  54         {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
  55         {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
  56         {0x00028A40, 0, 0, "VGT_GS_MODE"},
  57         {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
  58         {0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
  59         {0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
  60         {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
  61         {0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
  62 };
  63
  64 static const struct radeon_register R600_names_CB_CNTL[] = {
  65         {0x00028120, 0, 0, "CB_CLEAR_RED"},
  66         {0x00028124, 0, 0, "CB_CLEAR_GREEN"},
  67         {0x00028128, 0, 0, "CB_CLEAR_BLUE"},
  68         {0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
  69         {0x0002823C, 0, 0, "CB_SHADER_MASK"},
  70         {0x00028238, 0, 0, "CB_TARGET_MASK"},
  71         {0x00028424, 0, 0, "CB_FOG_RED"},
  72         {0x00028428, 0, 0, "CB_FOG_GREEN"},
  73         {0x0002842C, 0, 0, "CB_FOG_BLUE"},
  74         {0x00028808, 0, 0, "CB_COLOR_CONTROL"},
  75         {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
  76         {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
  77         {0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
  78         {0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
  79         {0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
  80         {0x00028C38, 0, 0, "CB_CLRCMP_DST"},
  81         {0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
  82         {0x00028C48, 0, 0, "PA_SC_AA_MASK"},
  83 };
  84
  85 static const struct radeon_register R600_names_RASTERIZER[] = {
  86         {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
  87         {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
  88         {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
  89         {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
  90         {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
  91         {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
  92         {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
  93         {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
  94         {0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
  95         {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
  96         {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
  97         {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
  98         {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
  99         {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
 100         {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
 101         {0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
 102         {0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
 103         {0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
 104         {0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
 105         {0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
 106         {0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
 107 };
 108
 109 static const struct radeon_register R600_names_VIEWPORT[] = {
 110         {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
 111         {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
 112         {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
 113         {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
 114         {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
 115         {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
 116         {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
 117         {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
 118         {0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
 119 };
 120
 121 static const struct radeon_register R600_names_SCISSOR[] = {
 122         {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
 123         {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
 124         {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
 125         {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
 126         {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
 127         {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
 128         {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
 129         {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
 130         {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
 131         {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
 132         {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
 133         {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
 134         {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
 135         {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
 136         {0x00028230, 0, 0, "PA_SC_EDGERULE"},
 137         {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
 138         {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
 139         {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
 140         {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
 141 };
 142
 143 static const struct radeon_register R600_names_BLEND[] = {
 144         {0x00028414, 0, 0, "CB_BLEND_RED"},
 145         {0x00028418, 0, 0, "CB_BLEND_GREEN"},
 146         {0x0002841C, 0, 0, "CB_BLEND_BLUE"},
 147         {0x00028420, 0, 0, "CB_BLEND_ALPHA"},
 148         {0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
 149         {0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
 150         {0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
 151         {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
 152         {0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
 153         {0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
 154         {0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
 155         {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
 156         {0x00028804, 0, 0, "CB_BLEND_CONTROL"},
 157 };
 158
 159 static const struct radeon_register R600_names_DSA[] = {
 160         {0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
 161         {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
 162         {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
 163         {0x00028430, 0, 0, "DB_STENCILREFMASK"},
 164         {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
 165         {0x00028438, 0, 0, "SX_ALPHA_REF"},
 166         {0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
 167         {0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
 168         {0x000286DC, 0, 0, "SPI_FOG_CNTL"},
 169         {0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
 170         {0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
 171         {0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
 172         {0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
 173         {0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
 174         {0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
 175         {0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
 176 };
 177
 178 static const struct radeon_register R600_names_VS_SHADER[] = {
 179         {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
 180         {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
 181         {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
 182         {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
 183         {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
 184         {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
 185         {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
 186         {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
 187         {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
 188         {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
 189         {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
 190         {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
 191         {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
 192         {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
 193         {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
 194         {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
 195         {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
 196         {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
 197         {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
 198         {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
 199         {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
 200         {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
 201         {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
 202         {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
 203         {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
 204         {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
 205         {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
 206         {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
 207         {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
 208         {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
 209         {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
 210         {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
 211         {0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
 212         {0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
 213         {0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
 214         {0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
 215         {0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
 216         {0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
 217         {0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
 218         {0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
 219         {0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
 220         {0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
 221         {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
 222         {0x00028858, 1, 0, "SQ_PGM_START_VS"},
 223         {0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
 224         {0x00028894, 1, 1, "SQ_PGM_START_FS"},
 225         {0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
 226         {0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
 227         {0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
 228 };
 229
 230 static const struct radeon_register R600_names_PS_SHADER[] = {
 231         {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
 232         {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
 233         {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
 234         {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
 235         {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
 236         {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
 237         {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
 238         {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
 239         {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
 240         {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
 241         {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
 242         {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
 243         {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
 244         {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
 245         {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
 246         {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
 247         {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
 248         {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
 249         {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
 250         {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
 251         {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
 252         {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
 253         {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
 254         {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
 255         {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
 256         {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
 257         {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
 258         {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
 259         {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
 260         {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
 261         {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
 262         {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
 263         {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
 264         {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
 265         {0x000286D8, 0, 0, "SPI_INPUT_Z"},
 266         {0x00028840, 1, 0, "SQ_PGM_START_PS"},
 267         {0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
 268         {0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
 269         {0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
 270 };
 271
 272 static const struct radeon_register R600_names_PS_CONSTANT[] = {
 273         {0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
 274         {0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
 275         {0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
 276         {0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
 277 };
 278
 279 static const struct radeon_register R600_names_VS_CONSTANT[] = {
 280         {0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
 281         {0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
 282         {0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
 283         {0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
 284 };
 285
 286 static const struct radeon_register R600_names_UCP[] = {
 287         {0x00028E20, 0, 0, "PA_CL_UCP0_X"},
 288         {0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
 289         {0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
 290         {0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
 291         {0x00028E30, 0, 0, "PA_CL_UCP1_X"},
 292         {0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
 293         {0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
 294         {0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
 295         {0x00028E40, 0, 0, "PA_CL_UCP2_X"},
 296         {0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
 297         {0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
 298         {0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
 299         {0x00028E50, 0, 0, "PA_CL_UCP3_X"},
 300         {0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
 301         {0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
 302         {0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
 303         {0x00028E60, 0, 0, "PA_CL_UCP4_X"},
 304         {0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
 305         {0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
 306         {0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
 307         {0x00028E70, 0, 0, "PA_CL_UCP5_X"},
 308         {0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
 309         {0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
 310         {0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
 311 };
 312
 313 static const struct radeon_register R600_names_PS_RESOURCE[] = {
 314         {0x00038000, 0, 0, "RESOURCE0_WORD0"},
 315         {0x00038004, 0, 0, "RESOURCE0_WORD1"},
 316         {0x00038008, 0, 0, "RESOURCE0_WORD2"},
 317         {0x0003800C, 0, 0, "RESOURCE0_WORD3"},
 318         {0x00038010, 0, 0, "RESOURCE0_WORD4"},
 319         {0x00038014, 0, 0, "RESOURCE0_WORD5"},
 320         {0x00038018, 0, 0, "RESOURCE0_WORD6"},
 321 };
 322
 323 static const struct radeon_register R600_names_VS_RESOURCE[] = {
 324         {0x00039180, 0, 0, "RESOURCE160_WORD0"},
 325         {0x00039184, 0, 0, "RESOURCE160_WORD1"},
 326         {0x00039188, 0, 0, "RESOURCE160_WORD2"},
 327         {0x0003918C, 0, 0, "RESOURCE160_WORD3"},
 328         {0x00039190, 0, 0, "RESOURCE160_WORD4"},
 329         {0x00039194, 0, 0, "RESOURCE160_WORD5"},
 330         {0x00039198, 0, 0, "RESOURCE160_WORD6"},
 331 };
 332
 333 static const struct radeon_register R600_names_FS_RESOURCE[] = {
 334         {0x0003A300, 0, 0, "RESOURCE320_WORD0"},
 335         {0x0003A304, 0, 0, "RESOURCE320_WORD1"},
 336         {0x0003A308, 0, 0, "RESOURCE320_WORD2"},
 337         {0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
 338         {0x0003A310, 0, 0, "RESOURCE320_WORD4"},
 339         {0x0003A314, 0, 0, "RESOURCE320_WORD5"},
 340         {0x0003A318, 0, 0, "RESOURCE320_WORD6"},
 341 };
 342
 343 static const struct radeon_register R600_names_GS_RESOURCE[] = {
 344         {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
 345         {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
 346         {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
 347         {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
 348         {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
 349         {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
 350         {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
 351 };
 352
 353 static const struct radeon_register R600_names_PS_SAMPLER[] = {
 354         {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
 355         {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
 356         {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
 357 };
 358
 359 static const struct radeon_register R600_names_VS_SAMPLER[] = {
 360         {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
 361         {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
 362         {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
 363 };
 364
 365 static const struct radeon_register R600_names_GS_SAMPLER[] = {
 366         {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
 367         {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
 368         {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
 369 };
 370
 371 static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = {
 372         {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
 373         {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
 374         {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
 375         {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
 376 };
 377
 378 static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = {
 379         {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
 380         {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
 381         {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
 382         {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
 383 };
 384
 385 static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = {
 386         {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
 387         {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
 388         {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
 389         {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
 390 };
 391
 392 static const struct radeon_register R600_names_CB0[] = {
 393         {0x00028040, 1, 0, "CB_COLOR0_BASE"},
 394         {0x000280A0, 0, 0, "CB_COLOR0_INFO"},
 395         {0x00028060, 0, 0, "CB_COLOR0_SIZE"},
 396         {0x00028080, 0, 0, "CB_COLOR0_VIEW"},
 397         {0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
 398         {0x000280C0, 1, 2, "CB_COLOR0_TILE"},
 399         {0x00028100, 0, 0, "CB_COLOR0_MASK"},
 400 };
 401
 402 static const struct radeon_register R600_names_CB1[] = {
 403         {0x00028044, 1, 0, "CB_COLOR1_BASE"},
 404         {0x000280A4, 0, 0, "CB_COLOR1_INFO"},
 405         {0x00028064, 0, 0, "CB_COLOR1_SIZE"},
 406         {0x00028084, 0, 0, "CB_COLOR1_VIEW"},
 407         {0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
 408         {0x000280C4, 1, 2, "CB_COLOR1_TILE"},
 409         {0x00028104, 0, 0, "CB_COLOR1_MASK"},
 410 };
 411
 412 static const struct radeon_register R600_names_CB2[] = {
 413         {0x00028048, 1, 0, "CB_COLOR2_BASE"},
 414         {0x000280A8, 0, 0, "CB_COLOR2_INFO"},
 415         {0x00028068, 0, 0, "CB_COLOR2_SIZE"},
 416         {0x00028088, 0, 0, "CB_COLOR2_VIEW"},
 417         {0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
 418         {0x000280C8, 1, 2, "CB_COLOR2_TILE"},
 419         {0x00028108, 0, 0, "CB_COLOR2_MASK"},
 420 };
 421
 422 static const struct radeon_register R600_names_CB3[] = {
 423         {0x0002804C, 1, 0, "CB_COLOR3_BASE"},
 424         {0x000280AC, 0, 0, "CB_COLOR3_INFO"},
 425         {0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
 426         {0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
 427         {0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
 428         {0x000280CC, 1, 2, "CB_COLOR3_TILE"},
 429         {0x0002810C, 0, 0, "CB_COLOR3_MASK"},
 430 };
 431
 432 static const struct radeon_register R600_names_CB4[] = {
 433         {0x00028050, 1, 0, "CB_COLOR4_BASE"},
 434         {0x000280B0, 0, 0, "CB_COLOR4_INFO"},
 435         {0x00028070, 0, 0, "CB_COLOR4_SIZE"},
 436         {0x00028090, 0, 0, "CB_COLOR4_VIEW"},
 437         {0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
 438         {0x000280D0, 1, 2, "CB_COLOR4_TILE"},
 439         {0x00028110, 0, 0, "CB_COLOR4_MASK"},
 440 };
 441
 442 static const struct radeon_register R600_names_CB5[] = {
 443         {0x00028054, 1, 0, "CB_COLOR5_BASE"},
 444         {0x000280B4, 0, 0, "CB_COLOR5_INFO"},
 445         {0x00028074, 0, 0, "CB_COLOR5_SIZE"},
 446         {0x00028094, 0, 0, "CB_COLOR5_VIEW"},
 447         {0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
 448         {0x000280D4, 1, 2, "CB_COLOR5_TILE"},
 449         {0x00028114, 0, 0, "CB_COLOR5_MASK"},
 450 };
 451
 452 static const struct radeon_register R600_names_CB6[] = {
 453         {0x00028058, 1, 0, "CB_COLOR6_BASE"},
 454         {0x000280B8, 0, 0, "CB_COLOR6_INFO"},
 455         {0x00028078, 0, 0, "CB_COLOR6_SIZE"},
 456         {0x00028098, 0, 0, "CB_COLOR6_VIEW"},
 457         {0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
 458         {0x000280D8, 1, 2, "CB_COLOR6_TILE"},
 459         {0x00028118, 0, 0, "CB_COLOR6_MASK"},
 460 };
 461
 462 static const struct radeon_register R600_names_CB7[] = {
 463         {0x0002805C, 1, 0, "CB_COLOR7_BASE"},
 464         {0x000280BC, 0, 0, "CB_COLOR7_INFO"},
 465         {0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
 466         {0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
 467         {0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
 468         {0x000280DC, 1, 2, "CB_COLOR7_TILE"},
 469         {0x0002811C, 0, 0, "CB_COLOR7_MASK"},
 470 };
 471
 472 static const struct radeon_register R600_names_DB[] = {
 473         {0x0002800C, 1, 0, "DB_DEPTH_BASE"},
 474         {0x00028000, 0, 0, "DB_DEPTH_SIZE"},
 475         {0x00028004, 0, 0, "DB_DEPTH_VIEW"},
 476         {0x00028010, 0, 0, "DB_DEPTH_INFO"},
 477         {0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
 478         {0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
 479 };
 480
 481 static const struct radeon_register R600_names_VGT[] = {
 482         {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
 483         {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
 484         {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
 485         {0x00028408, 0, 0, "VGT_INDX_OFFSET"},
 486         {0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
 487         {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
 488         {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
 489         {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
 490         {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
 491         {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
 492         {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
 493 };
 494
 495 static const struct radeon_register R600_names_DRAW[] = {
 496         {0x00008970, 0, 0, "VGT_NUM_INDICES"},
 497         {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
 498         {0x000287E8, 1, 0, "VGT_DMA_BASE"},
 499         {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
 500 };
 501
 502 static const struct radeon_register R600_names_VGT_EVENT[] = {
 503         {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
 504 };
 505
 506 #endif