2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_priv.h"
30 #include "radeon_drm.h"
33 static int radeon_ctx_set_bo_new(struct radeon_ctx
*ctx
, struct radeon_ws_bo
*bo
)
35 if (ctx
->nbo
>= RADEON_CTX_MAX_PM4
)
37 /* take a reference to the kernel bo */
38 radeon_bo_reference(ctx
->radeon
, &ctx
->bo
[ctx
->nbo
], radeon_bo_pb_get_bo(bo
->pb
));
43 static void radeon_ctx_get_placement(struct radeon_ctx
*ctx
, unsigned reloc
, u32
*placement
)
45 struct radeon_cs_reloc
*greloc
;
50 greloc
= (void *)(((u8
*)ctx
->reloc
) + reloc
* 4);
51 for (i
= 0; i
< ctx
->nbo
; i
++) {
52 if (ctx
->bo
[i
]->handle
== greloc
->handle
) {
53 placement
[0] = greloc
->read_domain
| greloc
->write_domain
;
54 placement
[1] = placement
[0];
60 void radeon_ctx_clear(struct radeon_ctx
*ctx
)
62 for (int i
= 0; i
< ctx
->nbo
; i
++) {
63 radeon_bo_reference(ctx
->radeon
, &ctx
->bo
[i
], NULL
);
65 ctx
->ndwords
= RADEON_CTX_MAX_PM4
;
71 struct radeon_ctx
*radeon_ctx_init(struct radeon
*radeon
)
73 struct radeon_ctx
*ctx
;
76 ctx
= calloc(1, sizeof(struct radeon_ctx
));
77 ctx
->radeon
= radeon_incref(radeon
);
78 radeon_ctx_clear(ctx
);
79 ctx
->pm4
= malloc(RADEON_CTX_MAX_PM4
* 4);
80 if (ctx
->pm4
== NULL
) {
84 ctx
->reloc
= malloc(sizeof(struct radeon_cs_reloc
) * RADEON_CTX_MAX_PM4
);
85 if (ctx
->reloc
== NULL
) {
89 ctx
->bo
= calloc(sizeof(void *), RADEON_CTX_MAX_PM4
);
90 if (ctx
->bo
== NULL
) {
97 void radeon_ctx_fini(struct radeon_ctx
*ctx
)
104 for (i
= 0; i
< ctx
->nbo
; i
++) {
105 radeon_bo_reference(ctx
->radeon
, &ctx
->bo
[i
], NULL
);
107 ctx
->radeon
= radeon_decref(ctx
->radeon
);
114 static int radeon_ctx_state_bo(struct radeon_ctx
*ctx
, struct radeon_state
*state
)
118 struct radeon_bo
*state_bo
;
121 for (i
= 0; i
< state
->nbo
; i
++) {
122 for (j
= 0; j
< ctx
->nbo
; j
++) {
123 state_bo
= radeon_bo_pb_get_bo(state
->bo
[i
]->pb
);
124 if (state_bo
== ctx
->bo
[j
])
128 r
= radeon_ctx_set_bo_new(ctx
, state
->bo
[i
]);
137 int radeon_ctx_submit(struct radeon_ctx
*ctx
)
139 struct drm_radeon_cs drmib
;
140 struct drm_radeon_cs_chunk chunks
[2];
141 uint64_t chunk_array
[2];
147 radeon_bo_pbmgr_flush_maps(ctx
->radeon
->kman
);
149 for (r
= 0; r
< ctx
->cdwords
; r
++) {
150 fprintf(stderr
, "0x%08X\n", ctx
->pm4
[r
]);
153 drmib
.num_chunks
= 2;
154 drmib
.chunks
= (uint64_t)(uintptr_t)chunk_array
;
155 chunks
[0].chunk_id
= RADEON_CHUNK_ID_IB
;
156 chunks
[0].length_dw
= ctx
->cdwords
;
157 chunks
[0].chunk_data
= (uint64_t)(uintptr_t)ctx
->pm4
;
158 chunks
[1].chunk_id
= RADEON_CHUNK_ID_RELOCS
;
159 chunks
[1].length_dw
= ctx
->nreloc
* sizeof(struct radeon_cs_reloc
) / 4;
160 chunks
[1].chunk_data
= (uint64_t)(uintptr_t)ctx
->reloc
;
161 chunk_array
[0] = (uint64_t)(uintptr_t)&chunks
[0];
162 chunk_array
[1] = (uint64_t)(uintptr_t)&chunks
[1];
164 r
= drmCommandWriteRead(ctx
->radeon
->fd
, DRM_RADEON_CS
, &drmib
,
165 sizeof(struct drm_radeon_cs
));
170 static int radeon_ctx_reloc(struct radeon_ctx
*ctx
, struct radeon_ws_bo
*bo
,
171 unsigned id
, unsigned *placement
)
174 unsigned bo_handle
= radeon_ws_bo_get_handle(bo
);
176 for (i
= 0; i
< ctx
->nreloc
; i
++) {
177 if (ctx
->reloc
[i
].handle
== bo_handle
) {
178 ctx
->pm4
[id
] = i
* sizeof(struct radeon_cs_reloc
) / 4;
182 if (ctx
->nreloc
>= RADEON_CTX_MAX_PM4
) {
185 ctx
->reloc
[ctx
->nreloc
].handle
= bo_handle
;
186 ctx
->reloc
[ctx
->nreloc
].read_domain
= placement
[0] | placement
[1];
187 ctx
->reloc
[ctx
->nreloc
].write_domain
= placement
[0] | placement
[1];
188 ctx
->reloc
[ctx
->nreloc
].flags
= 0;
189 ctx
->pm4
[id
] = ctx
->nreloc
* sizeof(struct radeon_cs_reloc
) / 4;
194 static int radeon_ctx_state_schedule(struct radeon_ctx
*ctx
, struct radeon_state
*state
)
196 unsigned i
, rid
, bid
, cid
;
201 if (state
->cpm4
> ctx
->ndwords
) {
204 memcpy(&ctx
->pm4
[ctx
->cdwords
], state
->pm4
, state
->cpm4
* 4);
205 for (i
= 0; i
< state
->nreloc
; i
++) {
206 rid
= state
->reloc_pm4_id
[i
];
207 bid
= state
->reloc_bo_id
[i
];
208 cid
= ctx
->cdwords
+ rid
;
209 r
= radeon_ctx_reloc(ctx
, state
->bo
[bid
], cid
,
210 &state
->placement
[bid
* 2]);
212 fprintf(stderr
, "%s state %d failed to reloc\n", __func__
, state
->stype
->stype
);
216 ctx
->cdwords
+= state
->cpm4
;
217 ctx
->ndwords
-= state
->cpm4
;
221 int radeon_ctx_set_query_state(struct radeon_ctx
*ctx
, struct radeon_state
*state
)
225 /* !!! ONLY ACCEPT QUERY STATE HERE !!! */
226 r
= radeon_state_pm4(state
);
229 /* BEGIN/END query are balanced in the same cs so account for END
230 * END query when scheduling BEGIN query
232 switch (state
->stype
->stype
) {
233 case R600_STATE_QUERY_BEGIN
:
234 /* is there enough place for begin & end */
235 if ((state
->cpm4
* 2) > ctx
->ndwords
)
237 ctx
->ndwords
-= state
->cpm4
;
239 case R600_STATE_QUERY_END
:
240 ctx
->ndwords
+= state
->cpm4
;
245 return radeon_ctx_state_schedule(ctx
, state
);
248 int radeon_ctx_set_draw(struct radeon_ctx
*ctx
, struct radeon_draw
*draw
)
250 unsigned previous_cdwords
;
254 for (i
= 0; i
< ctx
->radeon
->max_states
; i
++) {
255 r
= radeon_ctx_state_bo(ctx
, draw
->state
[i
]);
259 previous_cdwords
= ctx
->cdwords
;
260 for (i
= 0; i
< ctx
->radeon
->max_states
; i
++) {
261 if (draw
->state
[i
]) {
262 r
= radeon_ctx_state_schedule(ctx
, draw
->state
[i
]);
264 ctx
->cdwords
= previous_cdwords
;
274 int radeon_ctx_pm4(struct radeon_ctx
*ctx
)
281 ctx
->pm4
= malloc(ctx
->draw_cpm4
* 4);
282 if (ctx
->pm4
== NULL
)
284 for (i
= 0, ctx
->id
= 0; i
< ctx
->nstate
; i
++) {
286 if (ctx
->id
!= ctx
->draw_cpm4
) {
287 fprintf(stderr
, "%s miss predicted pm4 size %d for %d\n",
288 __func__
, ctx
->draw_cpm4
, ctx
->id
);
291 ctx
->cpm4
= ctx
->draw_cpm4
;
296 void radeon_ctx_dump_bof(struct radeon_ctx
*ctx
, const char *file
)
298 bof_t
*bcs
, *blob
, *array
, *bo
, *size
, *handle
, *device_id
, *root
;
301 root
= device_id
= bcs
= blob
= array
= bo
= size
= handle
= NULL
;
305 device_id
= bof_int32(ctx
->radeon
->device
);
306 if (device_id
== NULL
)
308 if (bof_object_set(root
, "device_id", device_id
))
310 bof_decref(device_id
);
313 blob
= bof_blob(ctx
->nreloc
* 16, ctx
->reloc
);
316 if (bof_object_set(root
, "reloc", blob
))
321 blob
= bof_blob(ctx
->cdwords
* 4, ctx
->pm4
);
324 if (bof_object_set(root
, "pm4", blob
))
332 for (i
= 0; i
< ctx
->nbo
; i
++) {
336 bo_size
= ctx
->bo
[i
]->size
;
337 size
= bof_int32(bo_size
);
340 if (bof_object_set(bo
, "size", size
))
344 handle
= bof_int32(ctx
->bo
[i
]->handle
);
347 if (bof_object_set(bo
, "handle", handle
))
351 radeon_bo_map(ctx
->radeon
, ctx
->bo
[i
]);
352 blob
= bof_blob(bo_size
, ctx
->bo
[i
]->data
);
353 radeon_bo_unmap(ctx
->radeon
, ctx
->bo
[i
]);
356 if (bof_object_set(bo
, "data", blob
))
360 if (bof_array_append(array
, bo
))
365 if (bof_object_set(root
, "bo", array
))
367 bof_dump_file(root
, file
);
374 bof_decref(device_id
);