src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "util/u_double_list.h"
  34 #include "os/os_thread.h"
  35 #include "os/os_mman.h"
  36
  37 #include "state_tracker/drm_driver.h"
  38
  39 #include <sys/ioctl.h>
  40 #include <xf86drm.h>
  41 #include <errno.h>
  42
  43 /*
  44  * this are copy from radeon_drm, once an updated libdrm is released
  45  * we should bump configure.ac requirement for it and remove the following
  46  * field
  47  */
  48 #define RADEON_BO_FLAGS_MACRO_TILE  1
  49 #define RADEON_BO_FLAGS_MICRO_TILE  2
  50 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  51
  52 #ifndef DRM_RADEON_GEM_WAIT
  53 #define DRM_RADEON_GEM_WAIT     0x2b
  54
  55 #define RADEON_GEM_NO_WAIT      0x1
  56 #define RADEON_GEM_USAGE_READ   0x2
  57 #define RADEON_GEM_USAGE_WRITE  0x4
  58
  59 struct drm_radeon_gem_wait {
  60     uint32_t    handle;
  61     uint32_t    flags;  /* one of RADEON_GEM_* */
  62 };
  63
  64 #endif
  65
  66 #ifndef RADEON_VA_MAP
  67
  68 #define RADEON_VA_MAP               1
  69 #define RADEON_VA_UNMAP             2
  70
  71 #define RADEON_VA_RESULT_OK         0
  72 #define RADEON_VA_RESULT_ERROR      1
  73 #define RADEON_VA_RESULT_VA_EXIST   2
  74
  75 #define RADEON_VM_PAGE_VALID        (1 << 0)
  76 #define RADEON_VM_PAGE_READABLE     (1 << 1)
  77 #define RADEON_VM_PAGE_WRITEABLE    (1 << 2)
  78 #define RADEON_VM_PAGE_SYSTEM       (1 << 3)
  79 #define RADEON_VM_PAGE_SNOOPED      (1 << 4)
  80
  81 struct drm_radeon_gem_va {
  82     uint32_t    handle;
  83     uint32_t    operation;
  84     uint32_t    vm_id;
  85     uint32_t    flags;
  86     uint64_t    offset;
  87 };
  88
  89 #define DRM_RADEON_GEM_VA   0x2b
  90 #endif
  91
  92
  93
  94 extern const struct pb_vtbl radeon_bo_vtbl;
  95
  96
  97 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  98 {
  99     assert(bo->vtbl == &radeon_bo_vtbl);
 100     return (struct radeon_bo *)bo;
 101 }
 102
 103 struct radeon_bo_va_hole {
 104     struct list_head list;
 105     uint64_t         offset;
 106     uint64_t         size;
 107 };
 108
 109 struct radeon_bomgr {
 110     /* Base class. */
 111     struct pb_manager base;
 112
 113     /* Winsys. */
 114     struct radeon_drm_winsys *rws;
 115
 116     /* List of buffer handles and its mutex. */
 117     struct util_hash_table *bo_handles;
 118     pipe_mutex bo_handles_mutex;
 119     pipe_mutex bo_va_mutex;
 120
 121     /* is virtual address supported */
 122     bool va;
 123     unsigned va_offset;
 124     struct list_head va_holes;
 125 };
 126
 127 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
 128 {
 129     return (struct radeon_bomgr *)mgr;
 130 }
 131
 132 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
 133 {
 134     struct radeon_bo *bo = NULL;
 135
 136     if (_buf->vtbl == &radeon_bo_vtbl) {
 137         bo = radeon_bo(_buf);
 138     } else {
 139         struct pb_buffer *base_buf;
 140         pb_size offset;
 141         pb_get_base_buffer(_buf, &base_buf, &offset);
 142
 143         if (base_buf->vtbl == &radeon_bo_vtbl)
 144             bo = radeon_bo(base_buf);
 145     }
 146
 147     return bo;
 148 }
 149
 150 static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
 151 {
 152     struct radeon_bo *bo = get_radeon_bo(_buf);
 153
 154     while (p_atomic_read(&bo->num_active_ioctls)) {
 155         sched_yield();
 156     }
 157
 158     /* XXX use this when it's ready */
 159     /*if (bo->rws->info.drm_minor >= 12) {
 160         struct drm_radeon_gem_wait args = {};
 161         args.handle = bo->handle;
 162         args.flags = usage;
 163         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 164                                    &args, sizeof(args)) == -EBUSY);
 165     } else*/ {
 166         struct drm_radeon_gem_wait_idle args;
 167         memset(&args, 0, sizeof(args));
 168         args.handle = bo->handle;
 169         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 170                                    &args, sizeof(args)) == -EBUSY);
 171     }
 172 }
 173
 174 static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
 175                                  enum radeon_bo_usage usage)
 176 {
 177     struct radeon_bo *bo = get_radeon_bo(_buf);
 178
 179     if (p_atomic_read(&bo->num_active_ioctls)) {
 180         return TRUE;
 181     }
 182
 183     /* XXX use this when it's ready */
 184     /*if (bo->rws->info.drm_minor >= 12) {
 185         struct drm_radeon_gem_wait args = {};
 186         args.handle = bo->handle;
 187         args.flags = usage | RADEON_GEM_NO_WAIT;
 188         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
 189                                    &args, sizeof(args)) != 0;
 190     } else*/ {
 191         struct drm_radeon_gem_busy args;
 192         memset(&args, 0, sizeof(args));
 193         args.handle = bo->handle;
 194         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 195                                    &args, sizeof(args)) != 0;
 196     }
 197 }
 198
 199 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, uint64_t alignment)
 200 {
 201     struct radeon_bo_va_hole *hole, *n;
 202     uint64_t offset = 0, waste = 0;
 203
 204     pipe_mutex_lock(mgr->bo_va_mutex);
 205     /* first look for a hole */
 206     LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
 207         offset = hole->offset;
 208         waste = 0;
 209         if (alignment) {
 210             waste = offset % alignment;
 211             waste = waste ? alignment - waste : 0;
 212         }
 213         offset += waste;
 214         if (offset >= (hole->offset + hole->size)) {
 215             continue;
 216         }
 217         if (!waste && hole->size == size) {
 218             offset = hole->offset;
 219             list_del(&hole->list);
 220             FREE(hole);
 221             pipe_mutex_unlock(mgr->bo_va_mutex);
 222             return offset;
 223         }
 224         if ((hole->size - waste) >= size) {
 225             if (waste) {
 226                 n = CALLOC_STRUCT(radeon_bo_va_hole);
 227                 n->size = waste;
 228                 n->offset = hole->offset;
 229                 list_add(&n->list, &mgr->va_holes);
 230             }
 231             hole->size -= (size + waste);
 232             hole->offset += size + waste;
 233             pipe_mutex_unlock(mgr->bo_va_mutex);
 234             return offset;
 235         }
 236     }
 237
 238     offset = mgr->va_offset;
 239     waste = 0;
 240     if (alignment) {
 241         waste = offset % alignment;
 242         waste = waste ? alignment - waste : 0;
 243     }
 244     offset += waste;
 245     mgr->va_offset += size + waste;
 246     pipe_mutex_unlock(mgr->bo_va_mutex);
 247     return offset;
 248 }
 249
 250 static void radeon_bomgr_force_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
 251 {
 252     pipe_mutex_lock(mgr->bo_va_mutex);
 253     if (va >= mgr->va_offset) {
 254         if (va > mgr->va_offset) {
 255             struct radeon_bo_va_hole *hole;
 256             hole = CALLOC_STRUCT(radeon_bo_va_hole);
 257             if (hole) {
 258                 hole->size = va - mgr->va_offset;
 259                 hole->offset = mgr->va_offset;
 260                 list_add(&hole->list, &mgr->va_holes);
 261             }
 262         }
 263         mgr->va_offset = va + size;
 264     } else {
 265         struct radeon_bo_va_hole *hole, *n;
 266         uint64_t stmp, etmp;
 267
 268         /* free all holes that fall into the range
 269          * NOTE that we might lose virtual address space
 270          */
 271         LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
 272             stmp = hole->offset;
 273             etmp = stmp + hole->size;
 274             if (va >= stmp && va < etmp) {
 275                 list_del(&hole->list);
 276                 FREE(hole);
 277             }
 278         }
 279     }
 280     pipe_mutex_unlock(mgr->bo_va_mutex);
 281 }
 282
 283 static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
 284 {
 285     pipe_mutex_lock(mgr->bo_va_mutex);
 286     if ((va + size) == mgr->va_offset) {
 287         mgr->va_offset = va;
 288     } else {
 289         struct radeon_bo_va_hole *hole;
 290
 291         /* FIXME on allocation failure we just lose virtual address space
 292          * maybe print a warning
 293          */
 294         hole = CALLOC_STRUCT(radeon_bo_va_hole);
 295         if (hole) {
 296             hole->size = size;
 297             hole->offset = va;
 298             list_add(&hole->list, &mgr->va_holes);
 299         }
 300     }
 301     pipe_mutex_unlock(mgr->bo_va_mutex);
 302 }
 303
 304 static void radeon_bo_destroy(struct pb_buffer *_buf)
 305 {
 306     struct radeon_bo *bo = radeon_bo(_buf);
 307     struct radeon_bomgr *mgr = bo->mgr;
 308     struct drm_gem_close args;
 309
 310     memset(&args, 0, sizeof(args));
 311
 312     if (bo->name) {
 313         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
 314         util_hash_table_remove(bo->mgr->bo_handles,
 315                                (void*)(uintptr_t)bo->name);
 316         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 317     }
 318
 319     if (bo->ptr)
 320         os_munmap(bo->ptr, bo->base.size);
 321
 322     if (mgr->va) {
 323         radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
 324     }
 325
 326     /* Close object. */
 327     args.handle = bo->handle;
 328     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 329     pipe_mutex_destroy(bo->map_mutex);
 330     FREE(bo);
 331 }
 332
 333 static void *radeon_bo_map(struct radeon_winsys_cs_handle *buf,
 334                            struct radeon_winsys_cs *rcs,
 335                            enum pipe_transfer_usage usage)
 336 {
 337     struct radeon_bo *bo = (struct radeon_bo*)buf;
 338     struct radeon_drm_cs *cs = (struct radeon_drm_cs*)rcs;
 339     struct drm_radeon_gem_mmap args = {0};
 340     void *ptr;
 341
 342     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 343     if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 344         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 345         if (usage & PIPE_TRANSFER_DONTBLOCK) {
 346             if (!(usage & PIPE_TRANSFER_WRITE)) {
 347                 /* Mapping for read.
 348                  *
 349                  * Since we are mapping for read, we don't need to wait
 350                  * if the GPU is using the buffer for read too
 351                  * (neither one is changing it).
 352                  *
 353                  * Only check whether the buffer is being used for write. */
 354                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 355                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 356                     return NULL;
 357                 }
 358
 359                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 360                                       RADEON_USAGE_WRITE)) {
 361                     return NULL;
 362                 }
 363             } else {
 364                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 365                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
 366                     return NULL;
 367                 }
 368
 369                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
 370                                       RADEON_USAGE_READWRITE)) {
 371                     return NULL;
 372                 }
 373             }
 374         } else {
 375             if (!(usage & PIPE_TRANSFER_WRITE)) {
 376                 /* Mapping for read.
 377                  *
 378                  * Since we are mapping for read, we don't need to wait
 379                  * if the GPU is using the buffer for read too
 380                  * (neither one is changing it).
 381                  *
 382                  * Only check whether the buffer is being used for write. */
 383                 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
 384                     cs->flush_cs(cs->flush_data, 0);
 385                 }
 386                 radeon_bo_wait((struct pb_buffer*)bo,
 387                                RADEON_USAGE_WRITE);
 388             } else {
 389                 /* Mapping for write. */
 390                 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 391                     cs->flush_cs(cs->flush_data, 0);
 392                 } else {
 393                     /* Try to avoid busy-waiting in radeon_bo_wait. */
 394                     if (p_atomic_read(&bo->num_active_ioctls))
 395                         radeon_drm_cs_sync_flush(cs);
 396                 }
 397
 398                 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
 399             }
 400         }
 401     }
 402
 403     /* Return the pointer if it's already mapped. */
 404     if (bo->ptr)
 405         return bo->ptr;
 406
 407     /* Map the buffer. */
 408     pipe_mutex_lock(bo->map_mutex);
 409     /* Return the pointer if it's already mapped (in case of a race). */
 410     if (bo->ptr) {
 411         pipe_mutex_unlock(bo->map_mutex);
 412         return bo->ptr;
 413     }
 414     args.handle = bo->handle;
 415     args.offset = 0;
 416     args.size = (uint64_t)bo->base.size;
 417     if (drmCommandWriteRead(bo->rws->fd,
 418                             DRM_RADEON_GEM_MMAP,
 419                             &args,
 420                             sizeof(args))) {
 421         pipe_mutex_unlock(bo->map_mutex);
 422         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 423                 bo, bo->handle);
 424         return NULL;
 425     }
 426
 427     ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 428                bo->rws->fd, args.addr_ptr);
 429     if (ptr == MAP_FAILED) {
 430         pipe_mutex_unlock(bo->map_mutex);
 431         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 432         return NULL;
 433     }
 434     bo->ptr = ptr;
 435     pipe_mutex_unlock(bo->map_mutex);
 436
 437     return bo->ptr;
 438 }
 439
 440 static void radeon_bo_unmap(struct radeon_winsys_cs_handle *_buf)
 441 {
 442     /* NOP */
 443 }
 444
 445 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 446                                       struct pb_buffer **base_buf,
 447                                       unsigned *offset)
 448 {
 449     *base_buf = buf;
 450     *offset = 0;
 451 }
 452
 453 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 454                                           struct pb_validate *vl,
 455                                           unsigned flags)
 456 {
 457     /* Always pinned */
 458     return PIPE_OK;
 459 }
 460
 461 static void radeon_bo_fence(struct pb_buffer *buf,
 462                             struct pipe_fence_handle *fence)
 463 {
 464 }
 465
 466 const struct pb_vtbl radeon_bo_vtbl = {
 467     radeon_bo_destroy,
 468     NULL, /* never called */
 469     NULL, /* never called */
 470     radeon_bo_validate,
 471     radeon_bo_fence,
 472     radeon_bo_get_base_buffer,
 473 };
 474
 475 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 476                                                 pb_size size,
 477                                                 const struct pb_desc *desc)
 478 {
 479     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 480     struct radeon_drm_winsys *rws = mgr->rws;
 481     struct radeon_bo *bo;
 482     struct drm_radeon_gem_create args;
 483     struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc;
 484     int r;
 485
 486     memset(&args, 0, sizeof(args));
 487
 488     assert(rdesc->initial_domains);
 489     assert((rdesc->initial_domains &
 490             ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
 491
 492     args.size = size;
 493     args.alignment = desc->alignment;
 494     args.initial_domain = rdesc->initial_domains;
 495
 496     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 497                             &args, sizeof(args))) {
 498         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 499         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 500         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 501         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 502         return NULL;
 503     }
 504
 505     bo = CALLOC_STRUCT(radeon_bo);
 506     if (!bo)
 507         return NULL;
 508
 509     pipe_reference_init(&bo->base.reference, 1);
 510     bo->base.alignment = desc->alignment;
 511     bo->base.usage = desc->usage;
 512     bo->base.size = size;
 513     bo->base.vtbl = &radeon_bo_vtbl;
 514     bo->mgr = mgr;
 515     bo->rws = mgr->rws;
 516     bo->handle = args.handle;
 517     bo->va = 0;
 518     pipe_mutex_init(bo->map_mutex);
 519
 520     if (mgr->va) {
 521         struct drm_radeon_gem_va va;
 522
 523         bo->va_size = align(size,  4096);
 524         bo->va = radeon_bomgr_find_va(mgr, bo->va_size, desc->alignment);
 525
 526         va.handle = bo->handle;
 527         va.vm_id = 0;
 528         va.operation = RADEON_VA_MAP;
 529         va.flags = RADEON_VM_PAGE_READABLE |
 530                    RADEON_VM_PAGE_WRITEABLE |
 531                    RADEON_VM_PAGE_SNOOPED;
 532         va.offset = bo->va;
 533         r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
 534         if (r && va.operation == RADEON_VA_RESULT_ERROR) {
 535             fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
 536             fprintf(stderr, "radeon:    size      : %d bytes\n", size);
 537             fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
 538             fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
 539             radeon_bo_destroy(&bo->base);
 540             return NULL;
 541         }
 542         if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
 543             radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
 544             bo->va = va.offset;
 545             radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
 546         }
 547     }
 548
 549     return &bo->base;
 550 }
 551
 552 static void radeon_bomgr_flush(struct pb_manager *mgr)
 553 {
 554     /* NOP */
 555 }
 556
 557 /* This is for the cache bufmgr. */
 558 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 559                                            struct pb_buffer *_buf)
 560 {
 561    struct radeon_bo *bo = radeon_bo(_buf);
 562
 563    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 564        return TRUE;
 565    }
 566
 567    if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
 568        return TRUE;
 569    }
 570
 571    return FALSE;
 572 }
 573
 574 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 575 {
 576     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 577     util_hash_table_destroy(mgr->bo_handles);
 578     pipe_mutex_destroy(mgr->bo_handles_mutex);
 579     pipe_mutex_destroy(mgr->bo_va_mutex);
 580     FREE(mgr);
 581 }
 582
 583 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 584
 585 static unsigned handle_hash(void *key)
 586 {
 587     return PTR_TO_UINT(key);
 588 }
 589
 590 static int handle_compare(void *key1, void *key2)
 591 {
 592     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 593 }
 594
 595 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 596 {
 597     struct radeon_bomgr *mgr;
 598
 599     mgr = CALLOC_STRUCT(radeon_bomgr);
 600     if (!mgr)
 601         return NULL;
 602
 603     mgr->base.destroy = radeon_bomgr_destroy;
 604     mgr->base.create_buffer = radeon_bomgr_create_bo;
 605     mgr->base.flush = radeon_bomgr_flush;
 606     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 607
 608     mgr->rws = rws;
 609     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 610     pipe_mutex_init(mgr->bo_handles_mutex);
 611     pipe_mutex_init(mgr->bo_va_mutex);
 612
 613     mgr->va = rws->info.r600_virtual_address;
 614     mgr->va_offset = rws->info.r600_va_start;
 615     list_inithead(&mgr->va_holes);
 616
 617     return &mgr->base;
 618 }
 619
 620 static unsigned eg_tile_split(unsigned tile_split)
 621 {
 622     switch (tile_split) {
 623     case 0:     tile_split = 64;    break;
 624     case 1:     tile_split = 128;   break;
 625     case 2:     tile_split = 256;   break;
 626     case 3:     tile_split = 512;   break;
 627     default:
 628     case 4:     tile_split = 1024;  break;
 629     case 5:     tile_split = 2048;  break;
 630     case 6:     tile_split = 4096;  break;
 631     }
 632     return tile_split;
 633 }
 634
 635 static unsigned eg_tile_split_rev(unsigned eg_tile_split)
 636 {
 637     switch (eg_tile_split) {
 638     case 64:    return 0;
 639     case 128:   return 1;
 640     case 256:   return 2;
 641     case 512:   return 3;
 642     default:
 643     case 1024:  return 4;
 644     case 2048:  return 5;
 645     case 4096:  return 6;
 646     }
 647 }
 648
 649 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 650                                  enum radeon_bo_layout *microtiled,
 651                                  enum radeon_bo_layout *macrotiled,
 652                                  unsigned *bankw, unsigned *bankh,
 653                                  unsigned *tile_split,
 654                                  unsigned *stencil_tile_split,
 655                                  unsigned *mtilea)
 656 {
 657     struct radeon_bo *bo = get_radeon_bo(_buf);
 658     struct drm_radeon_gem_set_tiling args;
 659
 660     memset(&args, 0, sizeof(args));
 661
 662     args.handle = bo->handle;
 663
 664     drmCommandWriteRead(bo->rws->fd,
 665                         DRM_RADEON_GEM_GET_TILING,
 666                         &args,
 667                         sizeof(args));
 668
 669     *microtiled = RADEON_LAYOUT_LINEAR;
 670     *macrotiled = RADEON_LAYOUT_LINEAR;
 671     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 672         *microtiled = RADEON_LAYOUT_TILED;
 673
 674     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 675         *macrotiled = RADEON_LAYOUT_TILED;
 676     if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
 677         *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 678         *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 679         *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 680         *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 681         *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 682         *tile_split = eg_tile_split(*tile_split);
 683     }
 684 }
 685
 686 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
 687                                  enum radeon_bo_layout microtiled,
 688                                  enum radeon_bo_layout macrotiled,
 689                                  unsigned bankw, unsigned bankh,
 690                                  unsigned tile_split,
 691                                  unsigned stencil_tile_split,
 692                                  unsigned mtilea,
 693                                  uint32_t pitch)
 694 {
 695     struct radeon_bo *bo = get_radeon_bo(_buf);
 696     struct drm_radeon_gem_set_tiling args;
 697
 698     memset(&args, 0, sizeof(args));
 699
 700     while (p_atomic_read(&bo->num_active_ioctls)) {
 701         sched_yield();
 702     }
 703
 704     if (microtiled == RADEON_LAYOUT_TILED)
 705         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 706     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
 707         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 708
 709     if (macrotiled == RADEON_LAYOUT_TILED)
 710         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 711
 712     args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
 713         RADEON_TILING_EG_BANKW_SHIFT;
 714     args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
 715         RADEON_TILING_EG_BANKH_SHIFT;
 716     args.tiling_flags |= (eg_tile_split_rev(tile_split) &
 717                           RADEON_TILING_EG_TILE_SPLIT_MASK) <<
 718         RADEON_TILING_EG_TILE_SPLIT_SHIFT;
 719     args.tiling_flags |= (stencil_tile_split &
 720                           RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
 721         RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
 722     args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
 723         RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
 724
 725     args.handle = bo->handle;
 726     args.pitch = pitch;
 727
 728     drmCommandWriteRead(bo->rws->fd,
 729                         DRM_RADEON_GEM_SET_TILING,
 730                         &args,
 731                         sizeof(args));
 732 }
 733
 734 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
 735         struct pb_buffer *_buf)
 736 {
 737     /* return radeon_bo. */
 738     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
 739 }
 740
 741 static struct pb_buffer *
 742 radeon_winsys_bo_create(struct radeon_winsys *rws,
 743                         unsigned size,
 744                         unsigned alignment,
 745                         unsigned bind,
 746                         enum radeon_bo_domain domain)
 747 {
 748     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 749     struct radeon_bo_desc desc;
 750     struct pb_manager *provider;
 751     struct pb_buffer *buffer;
 752
 753     memset(&desc, 0, sizeof(desc));
 754     desc.base.alignment = alignment;
 755
 756     /* Additional criteria for the cache manager. */
 757     desc.base.usage = domain;
 758     desc.initial_domains = domain;
 759
 760     /* Assign a buffer manager. */
 761     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 762                 PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_CUSTOM))
 763         provider = ws->cman;
 764     else
 765         provider = ws->kman;
 766
 767     buffer = provider->create_buffer(provider, size, &desc.base);
 768     if (!buffer)
 769         return NULL;
 770
 771     return (struct pb_buffer*)buffer;
 772 }
 773
 774 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
 775                                                       struct winsys_handle *whandle,
 776                                                       unsigned *stride)
 777 {
 778     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 779     struct radeon_bo *bo;
 780     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 781     struct drm_gem_open open_arg = {};
 782     int r;
 783
 784     memset(&open_arg, 0, sizeof(open_arg));
 785
 786     /* We must maintain a list of pairs <handle, bo>, so that we always return
 787      * the same BO for one particular handle. If we didn't do that and created
 788      * more than one BO for the same handle and then relocated them in a CS,
 789      * we would hit a deadlock in the kernel.
 790      *
 791      * The list of pairs is guarded by a mutex, of course. */
 792     pipe_mutex_lock(mgr->bo_handles_mutex);
 793
 794     /* First check if there already is an existing bo for the handle. */
 795     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 796     if (bo) {
 797         /* Increase the refcount. */
 798         struct pb_buffer *b = NULL;
 799         pb_reference(&b, &bo->base);
 800         goto done;
 801     }
 802
 803     /* There isn't, create a new one. */
 804     bo = CALLOC_STRUCT(radeon_bo);
 805     if (!bo) {
 806         goto fail;
 807     }
 808
 809     /* Open the BO. */
 810     open_arg.name = whandle->handle;
 811     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 812         FREE(bo);
 813         goto fail;
 814     }
 815     bo->handle = open_arg.handle;
 816     bo->name = whandle->handle;
 817
 818     /* Initialize it. */
 819     pipe_reference_init(&bo->base.reference, 1);
 820     bo->base.alignment = 0;
 821     bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 822     bo->base.size = open_arg.size;
 823     bo->base.vtbl = &radeon_bo_vtbl;
 824     bo->mgr = mgr;
 825     bo->rws = mgr->rws;
 826     bo->va = 0;
 827     pipe_mutex_init(bo->map_mutex);
 828
 829     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 830
 831 done:
 832     pipe_mutex_unlock(mgr->bo_handles_mutex);
 833
 834     if (stride)
 835         *stride = whandle->stride;
 836
 837     if (mgr->va) {
 838         struct drm_radeon_gem_va va;
 839
 840         bo->va_size = ((bo->base.size + 4095) & ~4095);
 841         bo->va = radeon_bomgr_find_va(mgr, bo->va_size, 1 << 20);
 842
 843         va.handle = bo->handle;
 844         va.operation = RADEON_VA_MAP;
 845         va.vm_id = 0;
 846         va.offset = bo->va;
 847         va.flags = RADEON_VM_PAGE_READABLE |
 848                    RADEON_VM_PAGE_WRITEABLE |
 849                    RADEON_VM_PAGE_SNOOPED;
 850         va.offset = bo->va;
 851         r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
 852         if (r && va.operation == RADEON_VA_RESULT_ERROR) {
 853             fprintf(stderr, "radeon: Failed to assign virtual address space\n");
 854             radeon_bo_destroy(&bo->base);
 855             return NULL;
 856         }
 857         if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
 858             radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
 859             bo->va = va.offset;
 860             radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
 861         }
 862     }
 863
 864     return (struct pb_buffer*)bo;
 865
 866 fail:
 867     pipe_mutex_unlock(mgr->bo_handles_mutex);
 868     return NULL;
 869 }
 870
 871 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
 872                                            unsigned stride,
 873                                            struct winsys_handle *whandle)
 874 {
 875     struct drm_gem_flink flink;
 876     struct radeon_bo *bo = get_radeon_bo(buffer);
 877
 878     memset(&flink, 0, sizeof(flink));
 879
 880     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 881         if (!bo->flinked) {
 882             flink.handle = bo->handle;
 883
 884             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 885                 return FALSE;
 886             }
 887
 888             bo->flinked = TRUE;
 889             bo->flink = flink.name;
 890         }
 891         whandle->handle = bo->flink;
 892     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 893         whandle->handle = bo->handle;
 894     }
 895
 896     whandle->stride = stride;
 897     return TRUE;
 898 }
 899
 900 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle *buf)
 901 {
 902     return ((struct radeon_bo*)buf)->va;
 903 }
 904
 905 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 906 {
 907     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 908     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 909     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 910     ws->base.buffer_map = radeon_bo_map;
 911     ws->base.buffer_unmap = radeon_bo_unmap;
 912     ws->base.buffer_wait = radeon_bo_wait;
 913     ws->base.buffer_is_busy = radeon_bo_is_busy;
 914     ws->base.buffer_create = radeon_winsys_bo_create;
 915     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 916     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 917     ws->base.buffer_get_virtual_address = radeon_winsys_bo_va;
 918 }