src/gallium/winsys/radeon/drm/radeon_drm_bo.c

   1 /*
   2  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 #define _FILE_OFFSET_BITS 64
  28 #include "radeon_drm_cs.h"
  29
  30 #include "util/u_hash_table.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_simple_list.h"
  33 #include "os/os_thread.h"
  34
  35 #include "state_tracker/drm_driver.h"
  36
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <xf86drm.h>
  40 #include <errno.h>
  41
  42 #define RADEON_BO_FLAGS_MACRO_TILE  1
  43 #define RADEON_BO_FLAGS_MICRO_TILE  2
  44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  45
  46 extern const struct pb_vtbl radeon_bo_vtbl;
  47
  48
  49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  50 {
  51     assert(bo->vtbl == &radeon_bo_vtbl);
  52     return (struct radeon_bo *)bo;
  53 }
  54
  55 struct radeon_bomgr {
  56     /* Base class. */
  57     struct pb_manager base;
  58
  59     /* Winsys. */
  60     struct radeon_drm_winsys *rws;
  61
  62     /* List of buffer handles and its mutex. */
  63     struct util_hash_table *bo_handles;
  64     pipe_mutex bo_handles_mutex;
  65 };
  66
  67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  68 {
  69     return (struct radeon_bomgr *)mgr;
  70 }
  71
  72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  73 {
  74     struct radeon_bo *bo = NULL;
  75
  76     if (_buf->vtbl == &radeon_bo_vtbl) {
  77         bo = radeon_bo(_buf);
  78     } else {
  79         struct pb_buffer *base_buf;
  80         pb_size offset;
  81         pb_get_base_buffer(_buf, &base_buf, &offset);
  82
  83         if (base_buf->vtbl == &radeon_bo_vtbl)
  84             bo = radeon_bo(base_buf);
  85     }
  86
  87     return bo;
  88 }
  89
  90 void radeon_bo_unref(struct radeon_bo *bo)
  91 {
  92     struct drm_gem_close args = {};
  93
  94     if (!p_atomic_dec_zero(&bo->ref_count))
  95         return;
  96
  97     if (bo->name) {
  98         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
  99         util_hash_table_remove(bo->mgr->bo_handles,
 100                                (void*)(uintptr_t)bo->name);
 101         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
 102     }
 103
 104     if (bo->ptr)
 105         munmap(bo->ptr, bo->size);
 106
 107     /* Close object. */
 108     args.handle = bo->handle;
 109     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
 110     pipe_mutex_destroy(bo->map_mutex);
 111     FREE(bo);
 112 }
 113
 114 static void radeon_bo_wait(struct r300_winsys_bo *_buf)
 115 {
 116     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 117     struct drm_radeon_gem_wait_idle args = {};
 118
 119     args.handle = bo->handle;
 120     while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
 121                                &args, sizeof(args)) == -EBUSY);
 122 }
 123
 124 static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf)
 125 {
 126     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 127     struct drm_radeon_gem_busy args = {};
 128
 129     args.handle = bo->handle;
 130     return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
 131                                &args, sizeof(args)) != 0;
 132 }
 133
 134 static void radeon_bo_destroy(struct pb_buffer *_buf)
 135 {
 136     struct radeon_bo *bo = radeon_bo(_buf);
 137
 138     radeon_bo_unref(bo);
 139 }
 140
 141 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
 142 {
 143     unsigned res = 0;
 144
 145     if (usage & PIPE_TRANSFER_DONTBLOCK)
 146         res |= PB_USAGE_DONTBLOCK;
 147
 148     if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 149         res |= PB_USAGE_UNSYNCHRONIZED;
 150
 151     return res;
 152 }
 153
 154 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
 155                                     unsigned flags, void *flush_ctx)
 156 {
 157     struct radeon_bo *bo = radeon_bo(_buf);
 158     struct radeon_drm_cs *cs = flush_ctx;
 159     struct drm_radeon_gem_mmap args = {};
 160     void *ptr;
 161
 162     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
 163     if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
 164         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
 165         if (flags & PB_USAGE_DONTBLOCK) {
 166             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 167                 cs->flush_cs(cs->flush_data);
 168                 return NULL;
 169             }
 170
 171             if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) {
 172                 return NULL;
 173             }
 174         } else {
 175             if (radeon_bo_is_referenced_by_cs(cs, bo)) {
 176                 cs->flush_cs(cs->flush_data);
 177             }
 178
 179             radeon_bo_wait((struct r300_winsys_bo*)bo);
 180         }
 181     }
 182
 183     /* Return the pointer if it's already mapped. */
 184     if (bo->ptr)
 185         return bo->ptr;
 186
 187     /* Map the buffer. */
 188     pipe_mutex_lock(bo->map_mutex);
 189     args.handle = bo->handle;
 190     args.offset = 0;
 191     args.size = (uint64_t)bo->size;
 192     if (drmCommandWriteRead(bo->rws->fd,
 193                             DRM_RADEON_GEM_MMAP,
 194                             &args,
 195                             sizeof(args))) {
 196         pipe_mutex_unlock(bo->map_mutex);
 197         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
 198                 bo, bo->handle);
 199         return NULL;
 200     }
 201
 202     ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
 203                bo->rws->fd, args.addr_ptr);
 204     if (ptr == MAP_FAILED) {
 205         pipe_mutex_unlock(bo->map_mutex);
 206         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
 207         return NULL;
 208     }
 209     bo->ptr = ptr;
 210     pipe_mutex_unlock(bo->map_mutex);
 211
 212     return bo->ptr;
 213 }
 214
 215 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
 216 {
 217     /* NOP */
 218 }
 219
 220 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
 221                                       struct pb_buffer **base_buf,
 222                                       unsigned *offset)
 223 {
 224     *base_buf = buf;
 225     *offset = 0;
 226 }
 227
 228 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
 229                                           struct pb_validate *vl,
 230                                           unsigned flags)
 231 {
 232     /* Always pinned */
 233     return PIPE_OK;
 234 }
 235
 236 static void radeon_bo_fence(struct pb_buffer *buf,
 237                             struct pipe_fence_handle *fence)
 238 {
 239 }
 240
 241 const struct pb_vtbl radeon_bo_vtbl = {
 242     radeon_bo_destroy,
 243     radeon_bo_map_internal,
 244     radeon_bo_unmap_internal,
 245     radeon_bo_validate,
 246     radeon_bo_fence,
 247     radeon_bo_get_base_buffer,
 248 };
 249
 250 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 251                                                 pb_size size,
 252                                                 const struct pb_desc *desc)
 253 {
 254     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 255     struct radeon_drm_winsys *rws = mgr->rws;
 256     struct radeon_bo *bo;
 257     struct drm_radeon_gem_create args = {};
 258
 259     args.size = size;
 260     args.alignment = desc->alignment;
 261     args.initial_domain =
 262         (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT  ?
 263          RADEON_GEM_DOMAIN_GTT  : 0) |
 264         (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
 265          RADEON_GEM_DOMAIN_VRAM : 0);
 266
 267     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
 268                             &args, sizeof(args))) {
 269         fprintf(stderr, "Failed to allocate :\n");
 270         fprintf(stderr, "   size      : %d bytes\n", size);
 271         fprintf(stderr, "   alignment : %d bytes\n", desc->alignment);
 272         fprintf(stderr, "   domains   : %d\n", args.initial_domain);
 273         return NULL;
 274     }
 275
 276     bo = CALLOC_STRUCT(radeon_bo);
 277     if (!bo)
 278         return NULL;
 279
 280     pipe_reference_init(&bo->base.base.reference, 1);
 281     bo->base.base.alignment = desc->alignment;
 282     bo->base.base.usage = desc->usage;
 283     bo->base.base.size = size;
 284     bo->base.vtbl = &radeon_bo_vtbl;
 285     bo->mgr = mgr;
 286     bo->rws = mgr->rws;
 287     bo->handle = args.handle;
 288     bo->size = size;
 289     pipe_mutex_init(bo->map_mutex);
 290
 291     radeon_bo_ref(bo);
 292     return &bo->base;
 293 }
 294
 295 static void radeon_bomgr_flush(struct pb_manager *mgr)
 296 {
 297     /* NOP */
 298 }
 299
 300 /* This is for the cache bufmgr. */
 301 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
 302                                            struct pb_buffer *_buf)
 303 {
 304    struct radeon_bo *bo = radeon_bo(_buf);
 305
 306    if (radeon_bo_is_referenced_by_any_cs(bo)) {
 307        return TRUE;
 308    }
 309
 310    if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) {
 311        return TRUE;
 312    }
 313
 314    return FALSE;
 315 }
 316
 317 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
 318 {
 319     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
 320     util_hash_table_destroy(mgr->bo_handles);
 321     pipe_mutex_destroy(mgr->bo_handles_mutex);
 322     FREE(mgr);
 323 }
 324
 325 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 326
 327 static unsigned handle_hash(void *key)
 328 {
 329     return PTR_TO_UINT(key);
 330 }
 331
 332 static int handle_compare(void *key1, void *key2)
 333 {
 334     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 335 }
 336
 337 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
 338 {
 339     struct radeon_bomgr *mgr;
 340
 341     mgr = CALLOC_STRUCT(radeon_bomgr);
 342     if (!mgr)
 343         return NULL;
 344
 345     mgr->base.destroy = radeon_bomgr_destroy;
 346     mgr->base.create_buffer = radeon_bomgr_create_bo;
 347     mgr->base.flush = radeon_bomgr_flush;
 348     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
 349
 350     mgr->rws = rws;
 351     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 352     pipe_mutex_init(mgr->bo_handles_mutex);
 353     return &mgr->base;
 354 }
 355
 356 static void *radeon_bo_map(struct r300_winsys_bo *buf,
 357                            struct r300_winsys_cs *cs,
 358                            enum pipe_transfer_usage usage)
 359 {
 360     struct pb_buffer *_buf = pb_buffer(buf);
 361
 362     return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs);
 363 }
 364
 365 static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf,
 366                                  enum r300_buffer_tiling *microtiled,
 367                                  enum r300_buffer_tiling *macrotiled)
 368 {
 369     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 370     struct drm_radeon_gem_set_tiling args = {};
 371
 372     args.handle = bo->handle;
 373
 374     drmCommandWriteRead(bo->rws->fd,
 375                         DRM_RADEON_GEM_GET_TILING,
 376                         &args,
 377                         sizeof(args));
 378
 379     *microtiled = R300_BUFFER_LINEAR;
 380     *macrotiled = R300_BUFFER_LINEAR;
 381     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
 382         *microtiled = R300_BUFFER_TILED;
 383
 384     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
 385         *macrotiled = R300_BUFFER_TILED;
 386 }
 387
 388 static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf,
 389                                  enum r300_buffer_tiling microtiled,
 390                                  enum r300_buffer_tiling macrotiled,
 391                                  uint32_t pitch)
 392 {
 393     struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
 394     struct drm_radeon_gem_set_tiling args = {};
 395
 396     if (microtiled == R300_BUFFER_TILED)
 397         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
 398     else if (microtiled == R300_BUFFER_SQUARETILED)
 399         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
 400
 401     if (macrotiled == R300_BUFFER_TILED)
 402         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
 403
 404     args.handle = bo->handle;
 405     args.pitch = pitch;
 406
 407     drmCommandWriteRead(bo->rws->fd,
 408                         DRM_RADEON_GEM_SET_TILING,
 409                         &args,
 410                         sizeof(args));
 411 }
 412
 413 static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle(
 414         struct r300_winsys_bo *_buf)
 415 {
 416     /* return radeon_bo. */
 417     return (struct r300_winsys_cs_handle*)
 418             get_radeon_bo(pb_buffer(_buf));
 419 }
 420
 421 static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage,
 422                                                enum r300_buffer_domain domain)
 423 {
 424     unsigned res = 0;
 425
 426     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
 427         res |= RADEON_PB_USAGE_CACHE;
 428
 429     if (domain & R300_DOMAIN_GTT)
 430         res |= RADEON_PB_USAGE_DOMAIN_GTT;
 431
 432     if (domain & R300_DOMAIN_VRAM)
 433         res |= RADEON_PB_USAGE_DOMAIN_VRAM;
 434
 435     return res;
 436 }
 437
 438 static struct r300_winsys_bo *
 439 radeon_winsys_bo_create(struct r300_winsys_screen *rws,
 440                         unsigned size,
 441                         unsigned alignment,
 442                         unsigned bind,
 443                         unsigned usage,
 444                         enum r300_buffer_domain domain)
 445 {
 446     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 447     struct pb_desc desc;
 448     struct pb_manager *provider;
 449     struct pb_buffer *buffer;
 450
 451     memset(&desc, 0, sizeof(desc));
 452     desc.alignment = alignment;
 453     desc.usage = get_pb_usage_from_create_flags(bind, usage, domain);
 454
 455     /* Assign a buffer manager. */
 456     if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
 457         provider = ws->cman;
 458     else
 459         provider = ws->kman;
 460
 461     buffer = provider->create_buffer(provider, size, &desc);
 462     if (!buffer)
 463         return NULL;
 464
 465     return (struct r300_winsys_bo*)buffer;
 466 }
 467
 468 static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws,
 469                                                            struct winsys_handle *whandle,
 470                                                            unsigned *stride,
 471                                                            unsigned *size)
 472 {
 473     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
 474     struct radeon_bo *bo;
 475     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
 476     struct drm_gem_open open_arg = {};
 477
 478     /* We must maintain a list of pairs <handle, bo>, so that we always return
 479      * the same BO for one particular handle. If we didn't do that and created
 480      * more than one BO for the same handle and then relocated them in a CS,
 481      * we would hit a deadlock in the kernel.
 482      *
 483      * The list of pairs is guarded by a mutex, of course. */
 484     pipe_mutex_lock(mgr->bo_handles_mutex);
 485
 486     /* First check if there already is an existing bo for the handle. */
 487     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
 488     if (bo) {
 489         /* Increase the refcount. */
 490         struct pb_buffer *b = NULL;
 491         pb_reference(&b, &bo->base);
 492         goto done;
 493     }
 494
 495     /* There isn't, create a new one. */
 496     bo = CALLOC_STRUCT(radeon_bo);
 497     if (!bo) {
 498         goto fail;
 499     }
 500
 501     /* Open the BO. */
 502     open_arg.name = whandle->handle;
 503     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
 504         FREE(bo);
 505         goto fail;
 506     }
 507     bo->handle = open_arg.handle;
 508     bo->size = open_arg.size;
 509     bo->name = whandle->handle;
 510     radeon_bo_ref(bo);
 511
 512     /* Initialize it. */
 513     pipe_reference_init(&bo->base.base.reference, 1);
 514     bo->base.base.alignment = 0;
 515     bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
 516     bo->base.base.size = bo->size;
 517     bo->base.vtbl = &radeon_bo_vtbl;
 518     bo->mgr = mgr;
 519     bo->rws = mgr->rws;
 520     pipe_mutex_init(bo->map_mutex);
 521
 522     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
 523
 524 done:
 525     pipe_mutex_unlock(mgr->bo_handles_mutex);
 526
 527     if (stride)
 528         *stride = whandle->stride;
 529     if (size)
 530         *size = bo->base.base.size;
 531
 532     return (struct r300_winsys_bo*)bo;
 533
 534 fail:
 535     pipe_mutex_unlock(mgr->bo_handles_mutex);
 536     return NULL;
 537 }
 538
 539 static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer,
 540                                            unsigned stride,
 541                                            struct winsys_handle *whandle)
 542 {
 543     struct drm_gem_flink flink = {};
 544     struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer));
 545
 546     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 547         if (!bo->flinked) {
 548             flink.handle = bo->handle;
 549
 550             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
 551                 return FALSE;
 552             }
 553
 554             bo->flinked = TRUE;
 555             bo->flink = flink.name;
 556         }
 557         whandle->handle = bo->flink;
 558     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 559         whandle->handle = bo->handle;
 560     }
 561
 562     whandle->stride = stride;
 563     return TRUE;
 564 }
 565
 566 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
 567 {
 568     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
 569     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
 570     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
 571     ws->base.buffer_map = radeon_bo_map;
 572     ws->base.buffer_unmap = pb_unmap;
 573     ws->base.buffer_wait = radeon_bo_wait;
 574     ws->base.buffer_is_busy = radeon_bo_is_busy;
 575     ws->base.buffer_create = radeon_winsys_bo_create;
 576     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
 577     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
 578 }