2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "os/os_thread.h"
33 #include "os/os_mman.h"
34 #include "os/os_time.h"
36 #include "state_tracker/drm_driver.h"
38 #include <sys/ioctl.h>
45 static inline struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
47 return (struct radeon_bo
*)bo
;
50 struct radeon_bo_va_hole
{
51 struct list_head list
;
56 static bool radeon_bo_is_busy(struct radeon_bo
*bo
)
58 struct drm_radeon_gem_busy args
= {0};
60 args
.handle
= bo
->handle
;
61 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
62 &args
, sizeof(args
)) != 0;
65 static void radeon_bo_wait_idle(struct radeon_bo
*bo
)
67 struct drm_radeon_gem_wait_idle args
= {0};
69 args
.handle
= bo
->handle
;
70 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
71 &args
, sizeof(args
)) == -EBUSY
);
74 static bool radeon_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
75 enum radeon_bo_usage usage
)
77 struct radeon_bo
*bo
= radeon_bo(_buf
);
80 /* No timeout. Just query. */
82 return !bo
->num_active_ioctls
&& !radeon_bo_is_busy(bo
);
84 abs_timeout
= os_time_get_absolute_timeout(timeout
);
86 /* Wait if any ioctl is being submitted with this buffer. */
87 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
90 /* Infinite timeout. */
91 if (abs_timeout
== PIPE_TIMEOUT_INFINITE
) {
92 radeon_bo_wait_idle(bo
);
96 /* Other timeouts need to be emulated with a loop. */
97 while (radeon_bo_is_busy(bo
)) {
98 if (os_time_get_nano() >= abs_timeout
)
106 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
108 /* Zero domains the driver doesn't understand. */
109 domain
&= RADEON_DOMAIN_VRAM_GTT
;
111 /* If no domain is set, we must set something... */
113 domain
= RADEON_DOMAIN_VRAM_GTT
;
118 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
119 struct pb_buffer
*buf
)
121 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
122 struct drm_radeon_gem_op args
;
124 if (bo
->rws
->info
.drm_minor
< 38)
125 return RADEON_DOMAIN_VRAM_GTT
;
127 memset(&args
, 0, sizeof(args
));
128 args
.handle
= bo
->handle
;
129 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
131 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
132 &args
, sizeof(args
));
134 /* GEM domains and winsys domains are defined the same. */
135 return get_valid_domain(args
.value
);
138 static uint64_t radeon_bomgr_find_va(struct radeon_drm_winsys
*rws
,
139 uint64_t size
, uint64_t alignment
)
141 struct radeon_bo_va_hole
*hole
, *n
;
142 uint64_t offset
= 0, waste
= 0;
144 /* All VM address space holes will implicitly start aligned to the
145 * size alignment, so we don't need to sanitize the alignment here
147 size
= align(size
, rws
->info
.gart_page_size
);
149 pipe_mutex_lock(rws
->bo_va_mutex
);
150 /* first look for a hole */
151 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &rws
->va_holes
, list
) {
152 offset
= hole
->offset
;
153 waste
= offset
% alignment
;
154 waste
= waste
? alignment
- waste
: 0;
156 if (offset
>= (hole
->offset
+ hole
->size
)) {
159 if (!waste
&& hole
->size
== size
) {
160 offset
= hole
->offset
;
161 list_del(&hole
->list
);
163 pipe_mutex_unlock(rws
->bo_va_mutex
);
166 if ((hole
->size
- waste
) > size
) {
168 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
170 n
->offset
= hole
->offset
;
171 list_add(&n
->list
, &hole
->list
);
173 hole
->size
-= (size
+ waste
);
174 hole
->offset
+= size
+ waste
;
175 pipe_mutex_unlock(rws
->bo_va_mutex
);
178 if ((hole
->size
- waste
) == size
) {
180 pipe_mutex_unlock(rws
->bo_va_mutex
);
185 offset
= rws
->va_offset
;
186 waste
= offset
% alignment
;
187 waste
= waste
? alignment
- waste
: 0;
189 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
192 list_add(&n
->list
, &rws
->va_holes
);
195 rws
->va_offset
+= size
+ waste
;
196 pipe_mutex_unlock(rws
->bo_va_mutex
);
200 static void radeon_bomgr_free_va(struct radeon_drm_winsys
*rws
,
201 uint64_t va
, uint64_t size
)
203 struct radeon_bo_va_hole
*hole
;
205 size
= align(size
, rws
->info
.gart_page_size
);
207 pipe_mutex_lock(rws
->bo_va_mutex
);
208 if ((va
+ size
) == rws
->va_offset
) {
210 /* Delete uppermost hole if it reaches the new top */
211 if (!LIST_IS_EMPTY(&rws
->va_holes
)) {
212 hole
= container_of(rws
->va_holes
.next
, hole
, list
);
213 if ((hole
->offset
+ hole
->size
) == va
) {
214 rws
->va_offset
= hole
->offset
;
215 list_del(&hole
->list
);
220 struct radeon_bo_va_hole
*next
;
222 hole
= container_of(&rws
->va_holes
, hole
, list
);
223 LIST_FOR_EACH_ENTRY(next
, &rws
->va_holes
, list
) {
224 if (next
->offset
< va
)
229 if (&hole
->list
!= &rws
->va_holes
) {
230 /* Grow upper hole if it's adjacent */
231 if (hole
->offset
== (va
+ size
)) {
234 /* Merge lower hole if it's adjacent */
235 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
236 (next
->offset
+ next
->size
) == va
) {
237 next
->size
+= hole
->size
;
238 list_del(&hole
->list
);
245 /* Grow lower hole if it's adjacent */
246 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
247 (next
->offset
+ next
->size
) == va
) {
252 /* FIXME on allocation failure we just lose virtual address space
253 * maybe print a warning
255 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
259 list_add(&next
->list
, &hole
->list
);
263 pipe_mutex_unlock(rws
->bo_va_mutex
);
266 void radeon_bo_destroy(struct pb_buffer
*_buf
)
268 struct radeon_bo
*bo
= radeon_bo(_buf
);
269 struct radeon_drm_winsys
*rws
= bo
->rws
;
270 struct drm_gem_close args
;
272 memset(&args
, 0, sizeof(args
));
274 pipe_mutex_lock(rws
->bo_handles_mutex
);
275 util_hash_table_remove(rws
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
276 if (bo
->flink_name
) {
277 util_hash_table_remove(rws
->bo_names
,
278 (void*)(uintptr_t)bo
->flink_name
);
280 pipe_mutex_unlock(rws
->bo_handles_mutex
);
283 os_munmap(bo
->ptr
, bo
->base
.size
);
285 if (rws
->info
.has_virtual_memory
) {
286 if (rws
->va_unmap_working
) {
287 struct drm_radeon_gem_va va
;
289 va
.handle
= bo
->handle
;
291 va
.operation
= RADEON_VA_UNMAP
;
292 va
.flags
= RADEON_VM_PAGE_READABLE
|
293 RADEON_VM_PAGE_WRITEABLE
|
294 RADEON_VM_PAGE_SNOOPED
;
297 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
,
299 va
.operation
== RADEON_VA_RESULT_ERROR
) {
300 fprintf(stderr
, "radeon: Failed to deallocate virtual address for buffer:\n");
301 fprintf(stderr
, "radeon: size : %"PRIu64
" bytes\n", bo
->base
.size
);
302 fprintf(stderr
, "radeon: va : 0x%"PRIx64
"\n", bo
->va
);
306 radeon_bomgr_free_va(rws
, bo
->va
, bo
->base
.size
);
310 args
.handle
= bo
->handle
;
311 drmIoctl(rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
313 pipe_mutex_destroy(bo
->map_mutex
);
315 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
316 rws
->allocated_vram
-= align(bo
->base
.size
, rws
->info
.gart_page_size
);
317 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
318 rws
->allocated_gtt
-= align(bo
->base
.size
, rws
->info
.gart_page_size
);
320 if (bo
->map_count
>= 1) {
321 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
322 bo
->rws
->mapped_vram
-= bo
->base
.size
;
324 bo
->rws
->mapped_gtt
-= bo
->base
.size
;
330 static void radeon_bo_destroy_or_cache(struct pb_buffer
*_buf
)
332 struct radeon_bo
*bo
= radeon_bo(_buf
);
334 if (bo
->use_reusable_pool
)
335 pb_cache_add_buffer(&bo
->cache_entry
);
337 radeon_bo_destroy(_buf
);
340 void *radeon_bo_do_map(struct radeon_bo
*bo
)
342 struct drm_radeon_gem_mmap args
= {0};
345 /* If the buffer is created from user memory, return the user pointer. */
349 /* Map the buffer. */
350 pipe_mutex_lock(bo
->map_mutex
);
351 /* Return the pointer if it's already mapped. */
354 pipe_mutex_unlock(bo
->map_mutex
);
357 args
.handle
= bo
->handle
;
359 args
.size
= (uint64_t)bo
->base
.size
;
360 if (drmCommandWriteRead(bo
->rws
->fd
,
364 pipe_mutex_unlock(bo
->map_mutex
);
365 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
370 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
371 bo
->rws
->fd
, args
.addr_ptr
);
372 if (ptr
== MAP_FAILED
) {
373 /* Clear the cache and try again. */
374 pb_cache_release_all_buffers(&bo
->rws
->bo_cache
);
376 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
377 bo
->rws
->fd
, args
.addr_ptr
);
378 if (ptr
== MAP_FAILED
) {
379 pipe_mutex_unlock(bo
->map_mutex
);
380 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
387 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
388 bo
->rws
->mapped_vram
+= bo
->base
.size
;
390 bo
->rws
->mapped_gtt
+= bo
->base
.size
;
392 pipe_mutex_unlock(bo
->map_mutex
);
396 static void *radeon_bo_map(struct pb_buffer
*buf
,
397 struct radeon_winsys_cs
*rcs
,
398 enum pipe_transfer_usage usage
)
400 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
401 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
403 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
404 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
405 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
406 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
407 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
410 * Since we are mapping for read, we don't need to wait
411 * if the GPU is using the buffer for read too
412 * (neither one is changing it).
414 * Only check whether the buffer is being used for write. */
415 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
416 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
420 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
421 RADEON_USAGE_WRITE
)) {
425 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
426 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
430 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
431 RADEON_USAGE_READWRITE
)) {
436 uint64_t time
= os_time_get_nano();
438 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
441 * Since we are mapping for read, we don't need to wait
442 * if the GPU is using the buffer for read too
443 * (neither one is changing it).
445 * Only check whether the buffer is being used for write. */
446 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
447 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
449 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
452 /* Mapping for write. */
454 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
455 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
457 /* Try to avoid busy-waiting in radeon_bo_wait. */
458 if (p_atomic_read(&bo
->num_active_ioctls
))
459 radeon_drm_cs_sync_flush(rcs
);
463 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
464 RADEON_USAGE_READWRITE
);
467 bo
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
471 return radeon_bo_do_map(bo
);
474 static void radeon_bo_unmap(struct pb_buffer
*_buf
)
476 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
481 pipe_mutex_lock(bo
->map_mutex
);
483 pipe_mutex_unlock(bo
->map_mutex
);
484 return; /* it's not been mapped */
487 assert(bo
->map_count
);
488 if (--bo
->map_count
) {
489 pipe_mutex_unlock(bo
->map_mutex
);
490 return; /* it's been mapped multiple times */
493 os_munmap(bo
->ptr
, bo
->base
.size
);
496 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
497 bo
->rws
->mapped_vram
-= bo
->base
.size
;
499 bo
->rws
->mapped_gtt
-= bo
->base
.size
;
501 pipe_mutex_unlock(bo
->map_mutex
);
504 static const struct pb_vtbl radeon_bo_vtbl
= {
505 radeon_bo_destroy_or_cache
506 /* other functions are never called */
509 #ifndef RADEON_GEM_GTT_WC
510 #define RADEON_GEM_GTT_WC (1 << 2)
512 #ifndef RADEON_GEM_CPU_ACCESS
513 /* BO is expected to be accessed by the CPU */
514 #define RADEON_GEM_CPU_ACCESS (1 << 3)
516 #ifndef RADEON_GEM_NO_CPU_ACCESS
517 /* CPU access is not expected to work for this BO */
518 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
521 static struct radeon_bo
*radeon_create_bo(struct radeon_drm_winsys
*rws
,
522 unsigned size
, unsigned alignment
,
524 unsigned initial_domains
,
526 unsigned pb_cache_bucket
)
528 struct radeon_bo
*bo
;
529 struct drm_radeon_gem_create args
;
532 memset(&args
, 0, sizeof(args
));
534 assert(initial_domains
);
535 assert((initial_domains
&
536 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
539 args
.alignment
= alignment
;
540 args
.initial_domain
= initial_domains
;
543 if (flags
& RADEON_FLAG_GTT_WC
)
544 args
.flags
|= RADEON_GEM_GTT_WC
;
545 if (flags
& RADEON_FLAG_CPU_ACCESS
)
546 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
547 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
548 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
550 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
551 &args
, sizeof(args
))) {
552 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
553 fprintf(stderr
, "radeon: size : %u bytes\n", size
);
554 fprintf(stderr
, "radeon: alignment : %u bytes\n", alignment
);
555 fprintf(stderr
, "radeon: domains : %u\n", args
.initial_domain
);
556 fprintf(stderr
, "radeon: flags : %u\n", args
.flags
);
560 bo
= CALLOC_STRUCT(radeon_bo
);
564 pipe_reference_init(&bo
->base
.reference
, 1);
565 bo
->base
.alignment
= alignment
;
566 bo
->base
.usage
= usage
;
567 bo
->base
.size
= size
;
568 bo
->base
.vtbl
= &radeon_bo_vtbl
;
570 bo
->handle
= args
.handle
;
572 bo
->initial_domain
= initial_domains
;
573 pipe_mutex_init(bo
->map_mutex
);
574 pb_cache_init_entry(&rws
->bo_cache
, &bo
->cache_entry
, &bo
->base
,
577 if (rws
->info
.has_virtual_memory
) {
578 struct drm_radeon_gem_va va
;
579 unsigned va_gap_size
;
581 va_gap_size
= rws
->check_vm
? MAX2(4 * alignment
, 64 * 1024) : 0;
582 bo
->va
= radeon_bomgr_find_va(rws
, size
+ va_gap_size
, alignment
);
584 va
.handle
= bo
->handle
;
586 va
.operation
= RADEON_VA_MAP
;
587 va
.flags
= RADEON_VM_PAGE_READABLE
|
588 RADEON_VM_PAGE_WRITEABLE
|
589 RADEON_VM_PAGE_SNOOPED
;
591 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
592 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
593 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
594 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
595 fprintf(stderr
, "radeon: alignment : %d bytes\n", alignment
);
596 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
597 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
598 radeon_bo_destroy(&bo
->base
);
601 pipe_mutex_lock(rws
->bo_handles_mutex
);
602 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
603 struct pb_buffer
*b
= &bo
->base
;
604 struct radeon_bo
*old_bo
=
605 util_hash_table_get(rws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
607 pipe_mutex_unlock(rws
->bo_handles_mutex
);
608 pb_reference(&b
, &old_bo
->base
);
612 util_hash_table_set(rws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
613 pipe_mutex_unlock(rws
->bo_handles_mutex
);
616 if (initial_domains
& RADEON_DOMAIN_VRAM
)
617 rws
->allocated_vram
+= align(size
, rws
->info
.gart_page_size
);
618 else if (initial_domains
& RADEON_DOMAIN_GTT
)
619 rws
->allocated_gtt
+= align(size
, rws
->info
.gart_page_size
);
624 bool radeon_bo_can_reclaim(struct pb_buffer
*_buf
)
626 struct radeon_bo
*bo
= radeon_bo(_buf
);
628 if (radeon_bo_is_referenced_by_any_cs(bo
))
631 return radeon_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
634 static unsigned eg_tile_split(unsigned tile_split
)
636 switch (tile_split
) {
637 case 0: tile_split
= 64; break;
638 case 1: tile_split
= 128; break;
639 case 2: tile_split
= 256; break;
640 case 3: tile_split
= 512; break;
642 case 4: tile_split
= 1024; break;
643 case 5: tile_split
= 2048; break;
644 case 6: tile_split
= 4096; break;
649 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
651 switch (eg_tile_split
) {
663 static void radeon_bo_get_metadata(struct pb_buffer
*_buf
,
664 struct radeon_bo_metadata
*md
)
666 struct radeon_bo
*bo
= radeon_bo(_buf
);
667 struct drm_radeon_gem_set_tiling args
;
669 memset(&args
, 0, sizeof(args
));
671 args
.handle
= bo
->handle
;
673 drmCommandWriteRead(bo
->rws
->fd
,
674 DRM_RADEON_GEM_GET_TILING
,
678 md
->microtile
= RADEON_LAYOUT_LINEAR
;
679 md
->macrotile
= RADEON_LAYOUT_LINEAR
;
680 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
681 md
->microtile
= RADEON_LAYOUT_TILED
;
682 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
683 md
->microtile
= RADEON_LAYOUT_SQUARETILED
;
685 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
686 md
->macrotile
= RADEON_LAYOUT_TILED
;
688 md
->bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
689 md
->bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
690 md
->tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
691 md
->mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
692 md
->tile_split
= eg_tile_split(md
->tile_split
);
693 md
->scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
696 static void radeon_bo_set_metadata(struct pb_buffer
*_buf
,
697 struct radeon_bo_metadata
*md
)
699 struct radeon_bo
*bo
= radeon_bo(_buf
);
700 struct drm_radeon_gem_set_tiling args
;
702 memset(&args
, 0, sizeof(args
));
704 os_wait_until_zero(&bo
->num_active_ioctls
, PIPE_TIMEOUT_INFINITE
);
706 if (md
->microtile
== RADEON_LAYOUT_TILED
)
707 args
.tiling_flags
|= RADEON_TILING_MICRO
;
708 else if (md
->microtile
== RADEON_LAYOUT_SQUARETILED
)
709 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
711 if (md
->macrotile
== RADEON_LAYOUT_TILED
)
712 args
.tiling_flags
|= RADEON_TILING_MACRO
;
714 args
.tiling_flags
|= (md
->bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
715 RADEON_TILING_EG_BANKW_SHIFT
;
716 args
.tiling_flags
|= (md
->bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
717 RADEON_TILING_EG_BANKH_SHIFT
;
718 if (md
->tile_split
) {
719 args
.tiling_flags
|= (eg_tile_split_rev(md
->tile_split
) &
720 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
721 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
723 args
.tiling_flags
|= (md
->mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
724 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
726 if (bo
->rws
->gen
>= DRV_SI
&& !md
->scanout
)
727 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
729 args
.handle
= bo
->handle
;
730 args
.pitch
= md
->stride
;
732 drmCommandWriteRead(bo
->rws
->fd
,
733 DRM_RADEON_GEM_SET_TILING
,
738 static struct pb_buffer
*
739 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
742 enum radeon_bo_domain domain
,
743 enum radeon_bo_flag flags
)
745 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
746 struct radeon_bo
*bo
;
747 unsigned usage
= 0, pb_cache_bucket
;
749 /* Only 32-bit sizes are supported. */
753 /* Align size to page size. This is the minimum alignment for normal
754 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
755 * like constant/uniform buffers, can benefit from better and more reuse.
757 size
= align(size
, ws
->info
.gart_page_size
);
758 alignment
= align(alignment
, ws
->info
.gart_page_size
);
760 /* Only set one usage bit each for domains and flags, or the cache manager
761 * might consider different sets of domains / flags compatible
763 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
766 usage
= (unsigned)domain
>> 1;
767 assert(flags
< sizeof(usage
) * 8 - 3);
768 usage
|= 1 << (flags
+ 3);
770 /* Determine the pb_cache bucket for minimizing pb_cache misses. */
772 if (size
<= 4096) /* small buffers */
773 pb_cache_bucket
+= 1;
774 if (domain
& RADEON_DOMAIN_VRAM
) /* VRAM or VRAM+GTT */
775 pb_cache_bucket
+= 2;
776 if (flags
== RADEON_FLAG_GTT_WC
) /* WC */
777 pb_cache_bucket
+= 4;
778 assert(pb_cache_bucket
< ARRAY_SIZE(ws
->bo_cache
.buckets
));
780 bo
= radeon_bo(pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
,
781 usage
, pb_cache_bucket
));
785 bo
= radeon_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
788 /* Clear the cache and try again. */
789 pb_cache_release_all_buffers(&ws
->bo_cache
);
790 bo
= radeon_create_bo(ws
, size
, alignment
, usage
, domain
, flags
,
796 bo
->use_reusable_pool
= true;
798 pipe_mutex_lock(ws
->bo_handles_mutex
);
799 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
800 pipe_mutex_unlock(ws
->bo_handles_mutex
);
805 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
806 void *pointer
, uint64_t size
)
808 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
809 struct drm_radeon_gem_userptr args
;
810 struct radeon_bo
*bo
;
813 bo
= CALLOC_STRUCT(radeon_bo
);
817 memset(&args
, 0, sizeof(args
));
818 args
.addr
= (uintptr_t)pointer
;
819 args
.size
= align(size
, ws
->info
.gart_page_size
);
820 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
821 RADEON_GEM_USERPTR_VALIDATE
|
822 RADEON_GEM_USERPTR_REGISTER
;
823 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
824 &args
, sizeof(args
))) {
829 pipe_mutex_lock(ws
->bo_handles_mutex
);
832 pipe_reference_init(&bo
->base
.reference
, 1);
833 bo
->handle
= args
.handle
;
834 bo
->base
.alignment
= 0;
835 bo
->base
.size
= size
;
836 bo
->base
.vtbl
= &radeon_bo_vtbl
;
838 bo
->user_ptr
= pointer
;
840 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
841 pipe_mutex_init(bo
->map_mutex
);
843 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
845 pipe_mutex_unlock(ws
->bo_handles_mutex
);
847 if (ws
->info
.has_virtual_memory
) {
848 struct drm_radeon_gem_va va
;
850 bo
->va
= radeon_bomgr_find_va(ws
, bo
->base
.size
, 1 << 20);
852 va
.handle
= bo
->handle
;
853 va
.operation
= RADEON_VA_MAP
;
856 va
.flags
= RADEON_VM_PAGE_READABLE
|
857 RADEON_VM_PAGE_WRITEABLE
|
858 RADEON_VM_PAGE_SNOOPED
;
860 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
861 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
862 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
863 radeon_bo_destroy(&bo
->base
);
866 pipe_mutex_lock(ws
->bo_handles_mutex
);
867 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
868 struct pb_buffer
*b
= &bo
->base
;
869 struct radeon_bo
*old_bo
=
870 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
872 pipe_mutex_unlock(ws
->bo_handles_mutex
);
873 pb_reference(&b
, &old_bo
->base
);
877 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
878 pipe_mutex_unlock(ws
->bo_handles_mutex
);
881 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
883 return (struct pb_buffer
*)bo
;
886 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
887 struct winsys_handle
*whandle
,
891 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
892 struct radeon_bo
*bo
;
897 if (!offset
&& whandle
->offset
!= 0) {
898 fprintf(stderr
, "attempt to import unsupported winsys offset %u\n",
903 /* We must maintain a list of pairs <handle, bo>, so that we always return
904 * the same BO for one particular handle. If we didn't do that and created
905 * more than one BO for the same handle and then relocated them in a CS,
906 * we would hit a deadlock in the kernel.
908 * The list of pairs is guarded by a mutex, of course. */
909 pipe_mutex_lock(ws
->bo_handles_mutex
);
911 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
912 /* First check if there already is an existing bo for the handle. */
913 bo
= util_hash_table_get(ws
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
914 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
915 /* We must first get the GEM handle, as fds are unreliable keys */
916 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
919 bo
= util_hash_table_get(ws
->bo_handles
, (void*)(uintptr_t)handle
);
921 /* Unknown handle type */
926 /* Increase the refcount. */
927 struct pb_buffer
*b
= NULL
;
928 pb_reference(&b
, &bo
->base
);
932 /* There isn't, create a new one. */
933 bo
= CALLOC_STRUCT(radeon_bo
);
938 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
939 struct drm_gem_open open_arg
= {};
940 memset(&open_arg
, 0, sizeof(open_arg
));
942 open_arg
.name
= whandle
->handle
;
943 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
947 handle
= open_arg
.handle
;
948 size
= open_arg
.size
;
949 bo
->flink_name
= whandle
->handle
;
950 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
951 size
= lseek(whandle
->handle
, 0, SEEK_END
);
953 * Could check errno to determine whether the kernel is new enough, but
954 * it doesn't really matter why this failed, just that it failed.
956 if (size
== (off_t
)-1) {
960 lseek(whandle
->handle
, 0, SEEK_SET
);
966 pipe_reference_init(&bo
->base
.reference
, 1);
967 bo
->base
.alignment
= 0;
968 bo
->base
.size
= (unsigned) size
;
969 bo
->base
.vtbl
= &radeon_bo_vtbl
;
972 pipe_mutex_init(bo
->map_mutex
);
975 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
977 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
980 pipe_mutex_unlock(ws
->bo_handles_mutex
);
983 *stride
= whandle
->stride
;
985 *offset
= whandle
->offset
;
987 if (ws
->info
.has_virtual_memory
&& !bo
->va
) {
988 struct drm_radeon_gem_va va
;
990 bo
->va
= radeon_bomgr_find_va(ws
, bo
->base
.size
, 1 << 20);
992 va
.handle
= bo
->handle
;
993 va
.operation
= RADEON_VA_MAP
;
996 va
.flags
= RADEON_VM_PAGE_READABLE
|
997 RADEON_VM_PAGE_WRITEABLE
|
998 RADEON_VM_PAGE_SNOOPED
;
1000 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
1001 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
1002 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
1003 radeon_bo_destroy(&bo
->base
);
1006 pipe_mutex_lock(ws
->bo_handles_mutex
);
1007 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1008 struct pb_buffer
*b
= &bo
->base
;
1009 struct radeon_bo
*old_bo
=
1010 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
1012 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1013 pb_reference(&b
, &old_bo
->base
);
1017 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
1018 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1021 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
1023 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1024 ws
->allocated_vram
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
1025 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1026 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->info
.gart_page_size
);
1028 return (struct pb_buffer
*)bo
;
1031 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1035 static bool radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1036 unsigned stride
, unsigned offset
,
1037 unsigned slice_size
,
1038 struct winsys_handle
*whandle
)
1040 struct drm_gem_flink flink
;
1041 struct radeon_bo
*bo
= radeon_bo(buffer
);
1042 struct radeon_drm_winsys
*ws
= bo
->rws
;
1044 memset(&flink
, 0, sizeof(flink
));
1046 bo
->use_reusable_pool
= false;
1048 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1049 if (!bo
->flink_name
) {
1050 flink
.handle
= bo
->handle
;
1052 if (ioctl(ws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1056 bo
->flink_name
= flink
.name
;
1058 pipe_mutex_lock(ws
->bo_handles_mutex
);
1059 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1060 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1062 whandle
->handle
= bo
->flink_name
;
1063 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1064 whandle
->handle
= bo
->handle
;
1065 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1066 if (drmPrimeHandleToFD(ws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1070 whandle
->stride
= stride
;
1071 whandle
->offset
= offset
;
1072 whandle
->offset
+= slice_size
* whandle
->layer
;
1077 static bool radeon_winsys_bo_is_user_ptr(struct pb_buffer
*buf
)
1079 return ((struct radeon_bo
*)buf
)->user_ptr
!= NULL
;
1082 static uint64_t radeon_winsys_bo_va(struct pb_buffer
*buf
)
1084 return ((struct radeon_bo
*)buf
)->va
;
1087 void radeon_drm_bo_init_functions(struct radeon_drm_winsys
*ws
)
1089 ws
->base
.buffer_set_metadata
= radeon_bo_set_metadata
;
1090 ws
->base
.buffer_get_metadata
= radeon_bo_get_metadata
;
1091 ws
->base
.buffer_map
= radeon_bo_map
;
1092 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1093 ws
->base
.buffer_wait
= radeon_bo_wait
;
1094 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1095 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1096 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1097 ws
->base
.buffer_is_user_ptr
= radeon_winsys_bo_is_user_ptr
;
1098 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1099 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1100 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;