2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "util/list.h"
33 #include "os/os_thread.h"
34 #include "os/os_mman.h"
35 #include "os/os_time.h"
37 #include "state_tracker/drm_driver.h"
39 #include <sys/ioctl.h>
45 static const struct pb_vtbl radeon_bo_vtbl
;
47 static INLINE
struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
49 assert(bo
->vtbl
== &radeon_bo_vtbl
);
50 return (struct radeon_bo
*)bo
;
53 struct radeon_bo_va_hole
{
54 struct list_head list
;
61 struct pb_manager base
;
64 struct radeon_drm_winsys
*rws
;
66 /* List of buffer GEM names. Protected by bo_handles_mutex. */
67 struct util_hash_table
*bo_names
;
68 /* List of buffer handles. Protectded by bo_handles_mutex. */
69 struct util_hash_table
*bo_handles
;
70 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
71 struct util_hash_table
*bo_vas
;
72 pipe_mutex bo_handles_mutex
;
73 pipe_mutex bo_va_mutex
;
75 /* is virtual address supported */
78 struct list_head va_holes
;
81 static INLINE
struct radeon_bomgr
*radeon_bomgr(struct pb_manager
*mgr
)
83 return (struct radeon_bomgr
*)mgr
;
86 static struct radeon_bo
*get_radeon_bo(struct pb_buffer
*_buf
)
88 struct radeon_bo
*bo
= NULL
;
90 if (_buf
->vtbl
== &radeon_bo_vtbl
) {
93 struct pb_buffer
*base_buf
;
95 pb_get_base_buffer(_buf
, &base_buf
, &offset
);
97 if (base_buf
->vtbl
== &radeon_bo_vtbl
)
98 bo
= radeon_bo(base_buf
);
104 static void radeon_bo_wait(struct pb_buffer
*_buf
, enum radeon_bo_usage usage
)
106 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
107 struct drm_radeon_gem_wait_idle args
= {0};
109 while (p_atomic_read(&bo
->num_active_ioctls
)) {
113 args
.handle
= bo
->handle
;
114 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
115 &args
, sizeof(args
)) == -EBUSY
);
118 static boolean
radeon_bo_is_busy(struct pb_buffer
*_buf
,
119 enum radeon_bo_usage usage
)
121 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
122 struct drm_radeon_gem_busy args
= {0};
124 if (p_atomic_read(&bo
->num_active_ioctls
)) {
128 args
.handle
= bo
->handle
;
129 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
130 &args
, sizeof(args
)) != 0;
133 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
135 /* Zero domains the driver doesn't understand. */
136 domain
&= RADEON_DOMAIN_VRAM_GTT
;
138 /* If no domain is set, we must set something... */
140 domain
= RADEON_DOMAIN_VRAM_GTT
;
145 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
146 struct radeon_winsys_cs_handle
*buf
)
148 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
149 struct drm_radeon_gem_op args
;
151 if (bo
->rws
->info
.drm_minor
< 38)
152 return RADEON_DOMAIN_VRAM_GTT
;
154 memset(&args
, 0, sizeof(args
));
155 args
.handle
= bo
->handle
;
156 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
158 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
159 &args
, sizeof(args
));
161 /* GEM domains and winsys domains are defined the same. */
162 return get_valid_domain(args
.value
);
165 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr
, uint64_t size
, uint64_t alignment
)
167 struct radeon_bo_va_hole
*hole
, *n
;
168 uint64_t offset
= 0, waste
= 0;
170 alignment
= MAX2(alignment
, 4096);
171 size
= align(size
, 4096);
173 pipe_mutex_lock(mgr
->bo_va_mutex
);
174 /* first look for a hole */
175 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &mgr
->va_holes
, list
) {
176 offset
= hole
->offset
;
177 waste
= offset
% alignment
;
178 waste
= waste
? alignment
- waste
: 0;
180 if (offset
>= (hole
->offset
+ hole
->size
)) {
183 if (!waste
&& hole
->size
== size
) {
184 offset
= hole
->offset
;
185 list_del(&hole
->list
);
187 pipe_mutex_unlock(mgr
->bo_va_mutex
);
190 if ((hole
->size
- waste
) > size
) {
192 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
194 n
->offset
= hole
->offset
;
195 list_add(&n
->list
, &hole
->list
);
197 hole
->size
-= (size
+ waste
);
198 hole
->offset
+= size
+ waste
;
199 pipe_mutex_unlock(mgr
->bo_va_mutex
);
202 if ((hole
->size
- waste
) == size
) {
204 pipe_mutex_unlock(mgr
->bo_va_mutex
);
209 offset
= mgr
->va_offset
;
210 waste
= offset
% alignment
;
211 waste
= waste
? alignment
- waste
: 0;
213 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
216 list_add(&n
->list
, &mgr
->va_holes
);
219 mgr
->va_offset
+= size
+ waste
;
220 pipe_mutex_unlock(mgr
->bo_va_mutex
);
224 static void radeon_bomgr_free_va(struct radeon_bomgr
*mgr
, uint64_t va
, uint64_t size
)
226 struct radeon_bo_va_hole
*hole
;
228 size
= align(size
, 4096);
230 pipe_mutex_lock(mgr
->bo_va_mutex
);
231 if ((va
+ size
) == mgr
->va_offset
) {
233 /* Delete uppermost hole if it reaches the new top */
234 if (!LIST_IS_EMPTY(&mgr
->va_holes
)) {
235 hole
= container_of(mgr
->va_holes
.next
, hole
, list
);
236 if ((hole
->offset
+ hole
->size
) == va
) {
237 mgr
->va_offset
= hole
->offset
;
238 list_del(&hole
->list
);
243 struct radeon_bo_va_hole
*next
;
245 hole
= container_of(&mgr
->va_holes
, hole
, list
);
246 LIST_FOR_EACH_ENTRY(next
, &mgr
->va_holes
, list
) {
247 if (next
->offset
< va
)
252 if (&hole
->list
!= &mgr
->va_holes
) {
253 /* Grow upper hole if it's adjacent */
254 if (hole
->offset
== (va
+ size
)) {
257 /* Merge lower hole if it's adjacent */
258 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
259 (next
->offset
+ next
->size
) == va
) {
260 next
->size
+= hole
->size
;
261 list_del(&hole
->list
);
268 /* Grow lower hole if it's adjacent */
269 if (next
!= hole
&& &next
->list
!= &mgr
->va_holes
&&
270 (next
->offset
+ next
->size
) == va
) {
275 /* FIXME on allocation failure we just lose virtual address space
276 * maybe print a warning
278 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
282 list_add(&next
->list
, &hole
->list
);
286 pipe_mutex_unlock(mgr
->bo_va_mutex
);
289 static void radeon_bo_destroy(struct pb_buffer
*_buf
)
291 struct radeon_bo
*bo
= radeon_bo(_buf
);
292 struct radeon_bomgr
*mgr
= bo
->mgr
;
293 struct drm_gem_close args
;
295 memset(&args
, 0, sizeof(args
));
297 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
298 util_hash_table_remove(bo
->mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
299 if (bo
->flink_name
) {
300 util_hash_table_remove(bo
->mgr
->bo_names
,
301 (void*)(uintptr_t)bo
->flink_name
);
303 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
306 os_munmap(bo
->ptr
, bo
->base
.size
);
309 if (bo
->rws
->va_unmap_working
) {
310 struct drm_radeon_gem_va va
;
312 va
.handle
= bo
->handle
;
314 va
.operation
= RADEON_VA_UNMAP
;
315 va
.flags
= RADEON_VM_PAGE_READABLE
|
316 RADEON_VM_PAGE_WRITEABLE
|
317 RADEON_VM_PAGE_SNOOPED
;
320 if (drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_VA
, &va
,
322 va
.operation
== RADEON_VA_RESULT_ERROR
) {
323 fprintf(stderr
, "radeon: Failed to deallocate virtual address for buffer:\n");
324 fprintf(stderr
, "radeon: size : %d bytes\n", bo
->base
.size
);
325 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
329 radeon_bomgr_free_va(mgr
, bo
->va
, bo
->base
.size
);
333 args
.handle
= bo
->handle
;
334 drmIoctl(bo
->rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
336 pipe_mutex_destroy(bo
->map_mutex
);
338 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
339 bo
->rws
->allocated_vram
-= align(bo
->base
.size
, 4096);
340 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
341 bo
->rws
->allocated_gtt
-= align(bo
->base
.size
, 4096);
345 void *radeon_bo_do_map(struct radeon_bo
*bo
)
347 struct drm_radeon_gem_mmap args
= {0};
350 /* If the buffer is created from user memory, return the user pointer. */
354 /* Return the pointer if it's already mapped. */
358 /* Map the buffer. */
359 pipe_mutex_lock(bo
->map_mutex
);
360 /* Return the pointer if it's already mapped (in case of a race). */
362 pipe_mutex_unlock(bo
->map_mutex
);
365 args
.handle
= bo
->handle
;
367 args
.size
= (uint64_t)bo
->base
.size
;
368 if (drmCommandWriteRead(bo
->rws
->fd
,
372 pipe_mutex_unlock(bo
->map_mutex
);
373 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
378 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
379 bo
->rws
->fd
, args
.addr_ptr
);
380 if (ptr
== MAP_FAILED
) {
381 pipe_mutex_unlock(bo
->map_mutex
);
382 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
386 pipe_mutex_unlock(bo
->map_mutex
);
391 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
392 struct radeon_winsys_cs
*rcs
,
393 enum pipe_transfer_usage usage
)
395 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
396 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
398 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
399 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
400 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
401 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
402 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
405 * Since we are mapping for read, we don't need to wait
406 * if the GPU is using the buffer for read too
407 * (neither one is changing it).
409 * Only check whether the buffer is being used for write. */
410 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
411 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
415 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
416 RADEON_USAGE_WRITE
)) {
420 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
421 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
425 if (radeon_bo_is_busy((struct pb_buffer
*)bo
,
426 RADEON_USAGE_READWRITE
)) {
431 uint64_t time
= os_time_get_nano();
433 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
436 * Since we are mapping for read, we don't need to wait
437 * if the GPU is using the buffer for read too
438 * (neither one is changing it).
440 * Only check whether the buffer is being used for write. */
441 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
442 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
444 radeon_bo_wait((struct pb_buffer
*)bo
,
447 /* Mapping for write. */
449 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
450 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
452 /* Try to avoid busy-waiting in radeon_bo_wait. */
453 if (p_atomic_read(&bo
->num_active_ioctls
))
454 radeon_drm_cs_sync_flush(rcs
);
458 radeon_bo_wait((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
);
461 bo
->mgr
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
465 return radeon_bo_do_map(bo
);
468 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
473 static void radeon_bo_get_base_buffer(struct pb_buffer
*buf
,
474 struct pb_buffer
**base_buf
,
481 static enum pipe_error
radeon_bo_validate(struct pb_buffer
*_buf
,
482 struct pb_validate
*vl
,
489 static void radeon_bo_fence(struct pb_buffer
*buf
,
490 struct pipe_fence_handle
*fence
)
494 static const struct pb_vtbl radeon_bo_vtbl
= {
496 NULL
, /* never called */
497 NULL
, /* never called */
500 radeon_bo_get_base_buffer
,
503 #ifndef RADEON_GEM_GTT_WC
504 #define RADEON_GEM_GTT_WC (1 << 2)
506 #ifndef RADEON_GEM_CPU_ACCESS
507 /* BO is expected to be accessed by the CPU */
508 #define RADEON_GEM_CPU_ACCESS (1 << 3)
510 #ifndef RADEON_GEM_NO_CPU_ACCESS
511 /* CPU access is not expected to work for this BO */
512 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
515 static struct pb_buffer
*radeon_bomgr_create_bo(struct pb_manager
*_mgr
,
517 const struct pb_desc
*desc
)
519 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
520 struct radeon_drm_winsys
*rws
= mgr
->rws
;
521 struct radeon_bo
*bo
;
522 struct drm_radeon_gem_create args
;
523 struct radeon_bo_desc
*rdesc
= (struct radeon_bo_desc
*)desc
;
526 memset(&args
, 0, sizeof(args
));
528 assert(rdesc
->initial_domains
);
529 assert((rdesc
->initial_domains
&
530 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
533 args
.alignment
= desc
->alignment
;
534 args
.initial_domain
= rdesc
->initial_domains
;
537 if (rdesc
->flags
& RADEON_FLAG_GTT_WC
)
538 args
.flags
|= RADEON_GEM_GTT_WC
;
539 if (rdesc
->flags
& RADEON_FLAG_CPU_ACCESS
)
540 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
541 if (rdesc
->flags
& RADEON_FLAG_NO_CPU_ACCESS
)
542 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
544 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
545 &args
, sizeof(args
))) {
546 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
547 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
548 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
549 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
550 fprintf(stderr
, "radeon: flags : %d\n", args
.flags
);
554 bo
= CALLOC_STRUCT(radeon_bo
);
558 pipe_reference_init(&bo
->base
.reference
, 1);
559 bo
->base
.alignment
= desc
->alignment
;
560 bo
->base
.usage
= desc
->usage
;
561 bo
->base
.size
= size
;
562 bo
->base
.vtbl
= &radeon_bo_vtbl
;
565 bo
->handle
= args
.handle
;
567 bo
->initial_domain
= rdesc
->initial_domains
;
568 pipe_mutex_init(bo
->map_mutex
);
571 struct drm_radeon_gem_va va
;
573 bo
->va
= radeon_bomgr_find_va(mgr
, size
, desc
->alignment
);
575 va
.handle
= bo
->handle
;
577 va
.operation
= RADEON_VA_MAP
;
578 va
.flags
= RADEON_VM_PAGE_READABLE
|
579 RADEON_VM_PAGE_WRITEABLE
|
580 RADEON_VM_PAGE_SNOOPED
;
582 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
583 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
584 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
585 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
586 fprintf(stderr
, "radeon: alignment : %d bytes\n", desc
->alignment
);
587 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
588 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
589 radeon_bo_destroy(&bo
->base
);
592 pipe_mutex_lock(mgr
->bo_handles_mutex
);
593 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
594 struct pb_buffer
*b
= &bo
->base
;
595 struct radeon_bo
*old_bo
=
596 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
598 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
599 pb_reference(&b
, &old_bo
->base
);
603 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
604 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
607 if (rdesc
->initial_domains
& RADEON_DOMAIN_VRAM
)
608 rws
->allocated_vram
+= align(size
, 4096);
609 else if (rdesc
->initial_domains
& RADEON_DOMAIN_GTT
)
610 rws
->allocated_gtt
+= align(size
, 4096);
615 static void radeon_bomgr_flush(struct pb_manager
*mgr
)
620 /* This is for the cache bufmgr. */
621 static boolean
radeon_bomgr_is_buffer_busy(struct pb_manager
*_mgr
,
622 struct pb_buffer
*_buf
)
624 struct radeon_bo
*bo
= radeon_bo(_buf
);
626 if (radeon_bo_is_referenced_by_any_cs(bo
)) {
630 if (radeon_bo_is_busy((struct pb_buffer
*)bo
, RADEON_USAGE_READWRITE
)) {
637 static void radeon_bomgr_destroy(struct pb_manager
*_mgr
)
639 struct radeon_bomgr
*mgr
= radeon_bomgr(_mgr
);
640 util_hash_table_destroy(mgr
->bo_names
);
641 util_hash_table_destroy(mgr
->bo_handles
);
642 util_hash_table_destroy(mgr
->bo_vas
);
643 pipe_mutex_destroy(mgr
->bo_handles_mutex
);
644 pipe_mutex_destroy(mgr
->bo_va_mutex
);
648 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
650 static unsigned handle_hash(void *key
)
652 return PTR_TO_UINT(key
);
655 static int handle_compare(void *key1
, void *key2
)
657 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
660 struct pb_manager
*radeon_bomgr_create(struct radeon_drm_winsys
*rws
)
662 struct radeon_bomgr
*mgr
;
664 mgr
= CALLOC_STRUCT(radeon_bomgr
);
668 mgr
->base
.destroy
= radeon_bomgr_destroy
;
669 mgr
->base
.create_buffer
= radeon_bomgr_create_bo
;
670 mgr
->base
.flush
= radeon_bomgr_flush
;
671 mgr
->base
.is_buffer_busy
= radeon_bomgr_is_buffer_busy
;
674 mgr
->bo_names
= util_hash_table_create(handle_hash
, handle_compare
);
675 mgr
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
676 mgr
->bo_vas
= util_hash_table_create(handle_hash
, handle_compare
);
677 pipe_mutex_init(mgr
->bo_handles_mutex
);
678 pipe_mutex_init(mgr
->bo_va_mutex
);
680 mgr
->va
= rws
->info
.r600_virtual_address
;
681 mgr
->va_offset
= rws
->va_start
;
682 list_inithead(&mgr
->va_holes
);
687 static unsigned eg_tile_split(unsigned tile_split
)
689 switch (tile_split
) {
690 case 0: tile_split
= 64; break;
691 case 1: tile_split
= 128; break;
692 case 2: tile_split
= 256; break;
693 case 3: tile_split
= 512; break;
695 case 4: tile_split
= 1024; break;
696 case 5: tile_split
= 2048; break;
697 case 6: tile_split
= 4096; break;
702 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
704 switch (eg_tile_split
) {
716 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
717 enum radeon_bo_layout
*microtiled
,
718 enum radeon_bo_layout
*macrotiled
,
719 unsigned *bankw
, unsigned *bankh
,
720 unsigned *tile_split
,
721 unsigned *stencil_tile_split
,
725 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
726 struct drm_radeon_gem_set_tiling args
;
728 memset(&args
, 0, sizeof(args
));
730 args
.handle
= bo
->handle
;
732 drmCommandWriteRead(bo
->rws
->fd
,
733 DRM_RADEON_GEM_GET_TILING
,
737 *microtiled
= RADEON_LAYOUT_LINEAR
;
738 *macrotiled
= RADEON_LAYOUT_LINEAR
;
739 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
740 *microtiled
= RADEON_LAYOUT_TILED
;
741 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
742 *microtiled
= RADEON_LAYOUT_SQUARETILED
;
744 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
745 *macrotiled
= RADEON_LAYOUT_TILED
;
746 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
747 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
748 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
749 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
750 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
751 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
752 *tile_split
= eg_tile_split(*tile_split
);
755 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
758 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
759 struct radeon_winsys_cs
*rcs
,
760 enum radeon_bo_layout microtiled
,
761 enum radeon_bo_layout macrotiled
,
762 unsigned bankw
, unsigned bankh
,
764 unsigned stencil_tile_split
,
769 struct radeon_bo
*bo
= get_radeon_bo(_buf
);
770 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
771 struct drm_radeon_gem_set_tiling args
;
773 memset(&args
, 0, sizeof(args
));
775 /* Tiling determines how DRM treats the buffer data.
776 * We must flush CS when changing it if the buffer is referenced. */
777 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
778 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
781 while (p_atomic_read(&bo
->num_active_ioctls
)) {
785 if (microtiled
== RADEON_LAYOUT_TILED
)
786 args
.tiling_flags
|= RADEON_TILING_MICRO
;
787 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
788 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
790 if (macrotiled
== RADEON_LAYOUT_TILED
)
791 args
.tiling_flags
|= RADEON_TILING_MACRO
;
793 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
794 RADEON_TILING_EG_BANKW_SHIFT
;
795 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
796 RADEON_TILING_EG_BANKH_SHIFT
;
798 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
799 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
800 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
802 args
.tiling_flags
|= (stencil_tile_split
&
803 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
804 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
805 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
806 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
808 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
809 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
811 args
.handle
= bo
->handle
;
814 drmCommandWriteRead(bo
->rws
->fd
,
815 DRM_RADEON_GEM_SET_TILING
,
820 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
822 /* return radeon_bo. */
823 return (struct radeon_winsys_cs_handle
*)get_radeon_bo(_buf
);
826 static struct pb_buffer
*
827 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
830 boolean use_reusable_pool
,
831 enum radeon_bo_domain domain
,
832 enum radeon_bo_flag flags
)
834 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
835 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
836 struct radeon_bo_desc desc
;
837 struct pb_manager
*provider
;
838 struct pb_buffer
*buffer
;
840 memset(&desc
, 0, sizeof(desc
));
841 desc
.base
.alignment
= alignment
;
843 /* Only set one usage bit each for domains and flags, or the cache manager
844 * might consider different sets of domains / flags compatible
846 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
847 desc
.base
.usage
= 1 << 2;
849 desc
.base
.usage
= domain
>> 1;
850 assert(flags
< sizeof(desc
.base
.usage
) * 8 - 3);
851 desc
.base
.usage
|= 1 << (flags
+ 3);
853 desc
.initial_domains
= domain
;
856 /* Assign a buffer manager. */
857 if (use_reusable_pool
)
862 buffer
= provider
->create_buffer(provider
, size
, &desc
.base
);
866 pipe_mutex_lock(mgr
->bo_handles_mutex
);
867 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)get_radeon_bo(buffer
)->handle
, buffer
);
868 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
870 return (struct pb_buffer
*)buffer
;
873 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
874 void *pointer
, unsigned size
)
876 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
877 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
878 struct drm_radeon_gem_userptr args
;
879 struct radeon_bo
*bo
;
882 bo
= CALLOC_STRUCT(radeon_bo
);
886 memset(&args
, 0, sizeof(args
));
887 args
.addr
= (uintptr_t)pointer
;
888 args
.size
= align(size
, sysconf(_SC_PAGE_SIZE
));
889 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
890 RADEON_GEM_USERPTR_VALIDATE
|
891 RADEON_GEM_USERPTR_REGISTER
;
892 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
893 &args
, sizeof(args
))) {
898 pipe_mutex_lock(mgr
->bo_handles_mutex
);
901 pipe_reference_init(&bo
->base
.reference
, 1);
902 bo
->handle
= args
.handle
;
903 bo
->base
.alignment
= 0;
904 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
905 bo
->base
.size
= size
;
906 bo
->base
.vtbl
= &radeon_bo_vtbl
;
909 bo
->user_ptr
= pointer
;
911 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
912 pipe_mutex_init(bo
->map_mutex
);
914 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
916 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
919 struct drm_radeon_gem_va va
;
921 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
923 va
.handle
= bo
->handle
;
924 va
.operation
= RADEON_VA_MAP
;
927 va
.flags
= RADEON_VM_PAGE_READABLE
|
928 RADEON_VM_PAGE_WRITEABLE
|
929 RADEON_VM_PAGE_SNOOPED
;
931 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
932 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
933 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
934 radeon_bo_destroy(&bo
->base
);
937 pipe_mutex_lock(mgr
->bo_handles_mutex
);
938 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
939 struct pb_buffer
*b
= &bo
->base
;
940 struct radeon_bo
*old_bo
=
941 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
943 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
944 pb_reference(&b
, &old_bo
->base
);
948 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
949 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
952 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
954 return (struct pb_buffer
*)bo
;
957 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
958 struct winsys_handle
*whandle
,
961 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
962 struct radeon_bo
*bo
;
963 struct radeon_bomgr
*mgr
= radeon_bomgr(ws
->kman
);
968 /* We must maintain a list of pairs <handle, bo>, so that we always return
969 * the same BO for one particular handle. If we didn't do that and created
970 * more than one BO for the same handle and then relocated them in a CS,
971 * we would hit a deadlock in the kernel.
973 * The list of pairs is guarded by a mutex, of course. */
974 pipe_mutex_lock(mgr
->bo_handles_mutex
);
976 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
977 /* First check if there already is an existing bo for the handle. */
978 bo
= util_hash_table_get(mgr
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
979 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
980 /* We must first get the GEM handle, as fds are unreliable keys */
981 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
984 bo
= util_hash_table_get(mgr
->bo_handles
, (void*)(uintptr_t)handle
);
986 /* Unknown handle type */
991 /* Increase the refcount. */
992 struct pb_buffer
*b
= NULL
;
993 pb_reference(&b
, &bo
->base
);
997 /* There isn't, create a new one. */
998 bo
= CALLOC_STRUCT(radeon_bo
);
1003 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1004 struct drm_gem_open open_arg
= {};
1005 memset(&open_arg
, 0, sizeof(open_arg
));
1007 open_arg
.name
= whandle
->handle
;
1008 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
1012 handle
= open_arg
.handle
;
1013 size
= open_arg
.size
;
1014 bo
->flink_name
= whandle
->handle
;
1015 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1016 size
= lseek(whandle
->handle
, 0, SEEK_END
);
1018 * Could check errno to determine whether the kernel is new enough, but
1019 * it doesn't really matter why this failed, just that it failed.
1021 if (size
== (off_t
)-1) {
1025 lseek(whandle
->handle
, 0, SEEK_SET
);
1028 bo
->handle
= handle
;
1030 /* Initialize it. */
1031 pipe_reference_init(&bo
->base
.reference
, 1);
1032 bo
->base
.alignment
= 0;
1033 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
1034 bo
->base
.size
= (unsigned) size
;
1035 bo
->base
.vtbl
= &radeon_bo_vtbl
;
1039 pipe_mutex_init(bo
->map_mutex
);
1042 util_hash_table_set(mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1044 util_hash_table_set(mgr
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
1047 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1050 *stride
= whandle
->stride
;
1052 if (mgr
->va
&& !bo
->va
) {
1053 struct drm_radeon_gem_va va
;
1055 bo
->va
= radeon_bomgr_find_va(mgr
, bo
->base
.size
, 1 << 20);
1057 va
.handle
= bo
->handle
;
1058 va
.operation
= RADEON_VA_MAP
;
1061 va
.flags
= RADEON_VM_PAGE_READABLE
|
1062 RADEON_VM_PAGE_WRITEABLE
|
1063 RADEON_VM_PAGE_SNOOPED
;
1065 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
1066 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
1067 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
1068 radeon_bo_destroy(&bo
->base
);
1071 pipe_mutex_lock(mgr
->bo_handles_mutex
);
1072 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
1073 struct pb_buffer
*b
= &bo
->base
;
1074 struct radeon_bo
*old_bo
=
1075 util_hash_table_get(mgr
->bo_vas
, (void*)(uintptr_t)va
.offset
);
1077 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1078 pb_reference(&b
, &old_bo
->base
);
1082 util_hash_table_set(mgr
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
1083 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1086 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
1088 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1089 ws
->allocated_vram
+= align(bo
->base
.size
, 4096);
1090 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1091 ws
->allocated_gtt
+= align(bo
->base
.size
, 4096);
1093 return (struct pb_buffer
*)bo
;
1096 pipe_mutex_unlock(mgr
->bo_handles_mutex
);
1100 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1102 struct winsys_handle
*whandle
)
1104 struct drm_gem_flink flink
;
1105 struct radeon_bo
*bo
= get_radeon_bo(buffer
);
1107 memset(&flink
, 0, sizeof(flink
));
1109 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1110 if (!bo
->flink_name
) {
1111 flink
.handle
= bo
->handle
;
1113 if (ioctl(bo
->rws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1117 bo
->flink_name
= flink
.name
;
1119 pipe_mutex_lock(bo
->mgr
->bo_handles_mutex
);
1120 util_hash_table_set(bo
->mgr
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1121 pipe_mutex_unlock(bo
->mgr
->bo_handles_mutex
);
1123 whandle
->handle
= bo
->flink_name
;
1124 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1125 whandle
->handle
= bo
->handle
;
1126 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1127 if (drmPrimeHandleToFD(bo
->rws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1131 whandle
->stride
= stride
;
1135 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1137 return ((struct radeon_bo
*)buf
)->va
;
1140 void radeon_bomgr_init_functions(struct radeon_drm_winsys
*ws
)
1142 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1143 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1144 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1145 ws
->base
.buffer_map
= radeon_bo_map
;
1146 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1147 ws
->base
.buffer_wait
= radeon_bo_wait
;
1148 ws
->base
.buffer_is_busy
= radeon_bo_is_busy
;
1149 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1150 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1151 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1152 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1153 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1154 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;