2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #include "radeon_drm_cs.h"
29 #include "util/u_hash_table.h"
30 #include "util/u_memory.h"
31 #include "util/simple_list.h"
32 #include "os/os_thread.h"
33 #include "os/os_mman.h"
34 #include "os/os_time.h"
36 #include "state_tracker/drm_driver.h"
38 #include <sys/ioctl.h>
44 static inline struct radeon_bo
*radeon_bo(struct pb_buffer
*bo
)
46 return (struct radeon_bo
*)bo
;
49 struct radeon_bo_va_hole
{
50 struct list_head list
;
55 static bool radeon_bo_is_busy(struct radeon_bo
*bo
)
57 struct drm_radeon_gem_busy args
= {0};
59 args
.handle
= bo
->handle
;
60 return drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_BUSY
,
61 &args
, sizeof(args
)) != 0;
64 static void radeon_bo_wait_idle(struct radeon_bo
*bo
)
66 struct drm_radeon_gem_wait_idle args
= {0};
68 args
.handle
= bo
->handle
;
69 while (drmCommandWrite(bo
->rws
->fd
, DRM_RADEON_GEM_WAIT_IDLE
,
70 &args
, sizeof(args
)) == -EBUSY
);
73 static bool radeon_bo_wait(struct pb_buffer
*_buf
, uint64_t timeout
,
74 enum radeon_bo_usage usage
)
76 struct radeon_bo
*bo
= radeon_bo(_buf
);
79 /* No timeout. Just query. */
81 return !bo
->num_active_ioctls
&& !radeon_bo_is_busy(bo
);
83 abs_timeout
= os_time_get_absolute_timeout(timeout
);
85 /* Wait if any ioctl is being submitted with this buffer. */
86 if (!os_wait_until_zero_abs_timeout(&bo
->num_active_ioctls
, abs_timeout
))
89 /* Infinite timeout. */
90 if (abs_timeout
== PIPE_TIMEOUT_INFINITE
) {
91 radeon_bo_wait_idle(bo
);
95 /* Other timeouts need to be emulated with a loop. */
96 while (radeon_bo_is_busy(bo
)) {
97 if (os_time_get_nano() >= abs_timeout
)
105 static enum radeon_bo_domain
get_valid_domain(enum radeon_bo_domain domain
)
107 /* Zero domains the driver doesn't understand. */
108 domain
&= RADEON_DOMAIN_VRAM_GTT
;
110 /* If no domain is set, we must set something... */
112 domain
= RADEON_DOMAIN_VRAM_GTT
;
117 static enum radeon_bo_domain
radeon_bo_get_initial_domain(
118 struct radeon_winsys_cs_handle
*buf
)
120 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
121 struct drm_radeon_gem_op args
;
123 if (bo
->rws
->info
.drm_minor
< 38)
124 return RADEON_DOMAIN_VRAM_GTT
;
126 memset(&args
, 0, sizeof(args
));
127 args
.handle
= bo
->handle
;
128 args
.op
= RADEON_GEM_OP_GET_INITIAL_DOMAIN
;
130 drmCommandWriteRead(bo
->rws
->fd
, DRM_RADEON_GEM_OP
,
131 &args
, sizeof(args
));
133 /* GEM domains and winsys domains are defined the same. */
134 return get_valid_domain(args
.value
);
137 static uint64_t radeon_bomgr_find_va(struct radeon_drm_winsys
*rws
,
138 uint64_t size
, uint64_t alignment
)
140 struct radeon_bo_va_hole
*hole
, *n
;
141 uint64_t offset
= 0, waste
= 0;
143 /* All VM address space holes will implicitly start aligned to the
144 * size alignment, so we don't need to sanitize the alignment here
146 size
= align(size
, rws
->size_align
);
148 pipe_mutex_lock(rws
->bo_va_mutex
);
149 /* first look for a hole */
150 LIST_FOR_EACH_ENTRY_SAFE(hole
, n
, &rws
->va_holes
, list
) {
151 offset
= hole
->offset
;
152 waste
= offset
% alignment
;
153 waste
= waste
? alignment
- waste
: 0;
155 if (offset
>= (hole
->offset
+ hole
->size
)) {
158 if (!waste
&& hole
->size
== size
) {
159 offset
= hole
->offset
;
160 list_del(&hole
->list
);
162 pipe_mutex_unlock(rws
->bo_va_mutex
);
165 if ((hole
->size
- waste
) > size
) {
167 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
169 n
->offset
= hole
->offset
;
170 list_add(&n
->list
, &hole
->list
);
172 hole
->size
-= (size
+ waste
);
173 hole
->offset
+= size
+ waste
;
174 pipe_mutex_unlock(rws
->bo_va_mutex
);
177 if ((hole
->size
- waste
) == size
) {
179 pipe_mutex_unlock(rws
->bo_va_mutex
);
184 offset
= rws
->va_offset
;
185 waste
= offset
% alignment
;
186 waste
= waste
? alignment
- waste
: 0;
188 n
= CALLOC_STRUCT(radeon_bo_va_hole
);
191 list_add(&n
->list
, &rws
->va_holes
);
194 rws
->va_offset
+= size
+ waste
;
195 pipe_mutex_unlock(rws
->bo_va_mutex
);
199 static void radeon_bomgr_free_va(struct radeon_drm_winsys
*rws
,
200 uint64_t va
, uint64_t size
)
202 struct radeon_bo_va_hole
*hole
;
204 size
= align(size
, rws
->size_align
);
206 pipe_mutex_lock(rws
->bo_va_mutex
);
207 if ((va
+ size
) == rws
->va_offset
) {
209 /* Delete uppermost hole if it reaches the new top */
210 if (!LIST_IS_EMPTY(&rws
->va_holes
)) {
211 hole
= container_of(rws
->va_holes
.next
, hole
, list
);
212 if ((hole
->offset
+ hole
->size
) == va
) {
213 rws
->va_offset
= hole
->offset
;
214 list_del(&hole
->list
);
219 struct radeon_bo_va_hole
*next
;
221 hole
= container_of(&rws
->va_holes
, hole
, list
);
222 LIST_FOR_EACH_ENTRY(next
, &rws
->va_holes
, list
) {
223 if (next
->offset
< va
)
228 if (&hole
->list
!= &rws
->va_holes
) {
229 /* Grow upper hole if it's adjacent */
230 if (hole
->offset
== (va
+ size
)) {
233 /* Merge lower hole if it's adjacent */
234 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
235 (next
->offset
+ next
->size
) == va
) {
236 next
->size
+= hole
->size
;
237 list_del(&hole
->list
);
244 /* Grow lower hole if it's adjacent */
245 if (next
!= hole
&& &next
->list
!= &rws
->va_holes
&&
246 (next
->offset
+ next
->size
) == va
) {
251 /* FIXME on allocation failure we just lose virtual address space
252 * maybe print a warning
254 next
= CALLOC_STRUCT(radeon_bo_va_hole
);
258 list_add(&next
->list
, &hole
->list
);
262 pipe_mutex_unlock(rws
->bo_va_mutex
);
265 void radeon_bo_destroy(struct pb_buffer
*_buf
)
267 struct radeon_bo
*bo
= radeon_bo(_buf
);
268 struct radeon_drm_winsys
*rws
= bo
->rws
;
269 struct drm_gem_close args
;
271 memset(&args
, 0, sizeof(args
));
273 pipe_mutex_lock(rws
->bo_handles_mutex
);
274 util_hash_table_remove(rws
->bo_handles
, (void*)(uintptr_t)bo
->handle
);
275 if (bo
->flink_name
) {
276 util_hash_table_remove(rws
->bo_names
,
277 (void*)(uintptr_t)bo
->flink_name
);
279 pipe_mutex_unlock(rws
->bo_handles_mutex
);
282 os_munmap(bo
->ptr
, bo
->base
.size
);
284 if (rws
->info
.r600_virtual_address
) {
285 if (rws
->va_unmap_working
) {
286 struct drm_radeon_gem_va va
;
288 va
.handle
= bo
->handle
;
290 va
.operation
= RADEON_VA_UNMAP
;
291 va
.flags
= RADEON_VM_PAGE_READABLE
|
292 RADEON_VM_PAGE_WRITEABLE
|
293 RADEON_VM_PAGE_SNOOPED
;
296 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
,
298 va
.operation
== RADEON_VA_RESULT_ERROR
) {
299 fprintf(stderr
, "radeon: Failed to deallocate virtual address for buffer:\n");
300 fprintf(stderr
, "radeon: size : %d bytes\n", bo
->base
.size
);
301 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
305 radeon_bomgr_free_va(rws
, bo
->va
, bo
->base
.size
);
309 args
.handle
= bo
->handle
;
310 drmIoctl(rws
->fd
, DRM_IOCTL_GEM_CLOSE
, &args
);
312 pipe_mutex_destroy(bo
->map_mutex
);
314 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
315 rws
->allocated_vram
-= align(bo
->base
.size
, rws
->size_align
);
316 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
317 rws
->allocated_gtt
-= align(bo
->base
.size
, rws
->size_align
);
321 static void radeon_bo_destroy_or_cache(struct pb_buffer
*_buf
)
323 struct radeon_bo
*bo
= radeon_bo(_buf
);
325 if (bo
->use_reusable_pool
)
326 pb_cache_add_buffer(&bo
->cache_entry
);
328 radeon_bo_destroy(_buf
);
331 void *radeon_bo_do_map(struct radeon_bo
*bo
)
333 struct drm_radeon_gem_mmap args
= {0};
336 /* If the buffer is created from user memory, return the user pointer. */
340 /* Map the buffer. */
341 pipe_mutex_lock(bo
->map_mutex
);
342 /* Return the pointer if it's already mapped. */
345 pipe_mutex_unlock(bo
->map_mutex
);
348 args
.handle
= bo
->handle
;
350 args
.size
= (uint64_t)bo
->base
.size
;
351 if (drmCommandWriteRead(bo
->rws
->fd
,
355 pipe_mutex_unlock(bo
->map_mutex
);
356 fprintf(stderr
, "radeon: gem_mmap failed: %p 0x%08X\n",
361 ptr
= os_mmap(0, args
.size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
,
362 bo
->rws
->fd
, args
.addr_ptr
);
363 if (ptr
== MAP_FAILED
) {
364 pipe_mutex_unlock(bo
->map_mutex
);
365 fprintf(stderr
, "radeon: mmap failed, errno: %i\n", errno
);
370 pipe_mutex_unlock(bo
->map_mutex
);
375 static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf
,
376 struct radeon_winsys_cs
*rcs
,
377 enum pipe_transfer_usage usage
)
379 struct radeon_bo
*bo
= (struct radeon_bo
*)buf
;
380 struct radeon_drm_cs
*cs
= (struct radeon_drm_cs
*)rcs
;
382 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
383 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
384 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
385 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
386 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
389 * Since we are mapping for read, we don't need to wait
390 * if the GPU is using the buffer for read too
391 * (neither one is changing it).
393 * Only check whether the buffer is being used for write. */
394 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
395 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
399 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
400 RADEON_USAGE_WRITE
)) {
404 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
405 cs
->flush_cs(cs
->flush_data
, RADEON_FLUSH_ASYNC
, NULL
);
409 if (!radeon_bo_wait((struct pb_buffer
*)bo
, 0,
410 RADEON_USAGE_READWRITE
)) {
415 uint64_t time
= os_time_get_nano();
417 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
420 * Since we are mapping for read, we don't need to wait
421 * if the GPU is using the buffer for read too
422 * (neither one is changing it).
424 * Only check whether the buffer is being used for write. */
425 if (cs
&& radeon_bo_is_referenced_by_cs_for_write(cs
, bo
)) {
426 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
428 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
431 /* Mapping for write. */
433 if (radeon_bo_is_referenced_by_cs(cs
, bo
)) {
434 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
436 /* Try to avoid busy-waiting in radeon_bo_wait. */
437 if (p_atomic_read(&bo
->num_active_ioctls
))
438 radeon_drm_cs_sync_flush(rcs
);
442 radeon_bo_wait((struct pb_buffer
*)bo
, PIPE_TIMEOUT_INFINITE
,
443 RADEON_USAGE_READWRITE
);
446 bo
->rws
->buffer_wait_time
+= os_time_get_nano() - time
;
450 return radeon_bo_do_map(bo
);
453 static void radeon_bo_unmap(struct radeon_winsys_cs_handle
*_buf
)
455 struct radeon_bo
*bo
= (struct radeon_bo
*)_buf
;
460 pipe_mutex_lock(bo
->map_mutex
);
462 pipe_mutex_unlock(bo
->map_mutex
);
463 return; /* it's not been mapped */
466 assert(bo
->map_count
);
467 if (--bo
->map_count
) {
468 pipe_mutex_unlock(bo
->map_mutex
);
469 return; /* it's been mapped multiple times */
472 os_munmap(bo
->ptr
, bo
->base
.size
);
474 pipe_mutex_unlock(bo
->map_mutex
);
477 static const struct pb_vtbl radeon_bo_vtbl
= {
478 radeon_bo_destroy_or_cache
479 /* other functions are never called */
482 #ifndef RADEON_GEM_GTT_WC
483 #define RADEON_GEM_GTT_WC (1 << 2)
485 #ifndef RADEON_GEM_CPU_ACCESS
486 /* BO is expected to be accessed by the CPU */
487 #define RADEON_GEM_CPU_ACCESS (1 << 3)
489 #ifndef RADEON_GEM_NO_CPU_ACCESS
490 /* CPU access is not expected to work for this BO */
491 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
494 static struct radeon_bo
*radeon_create_bo(struct radeon_drm_winsys
*rws
,
495 unsigned size
, unsigned alignment
,
497 unsigned initial_domains
,
500 struct radeon_bo
*bo
;
501 struct drm_radeon_gem_create args
;
504 memset(&args
, 0, sizeof(args
));
506 assert(initial_domains
);
507 assert((initial_domains
&
508 ~(RADEON_GEM_DOMAIN_GTT
| RADEON_GEM_DOMAIN_VRAM
)) == 0);
511 args
.alignment
= alignment
;
512 args
.initial_domain
= initial_domains
;
515 if (flags
& RADEON_FLAG_GTT_WC
)
516 args
.flags
|= RADEON_GEM_GTT_WC
;
517 if (flags
& RADEON_FLAG_CPU_ACCESS
)
518 args
.flags
|= RADEON_GEM_CPU_ACCESS
;
519 if (flags
& RADEON_FLAG_NO_CPU_ACCESS
)
520 args
.flags
|= RADEON_GEM_NO_CPU_ACCESS
;
522 if (drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_CREATE
,
523 &args
, sizeof(args
))) {
524 fprintf(stderr
, "radeon: Failed to allocate a buffer:\n");
525 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
526 fprintf(stderr
, "radeon: alignment : %d bytes\n", alignment
);
527 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
528 fprintf(stderr
, "radeon: flags : %d\n", args
.flags
);
532 bo
= CALLOC_STRUCT(radeon_bo
);
536 pipe_reference_init(&bo
->base
.reference
, 1);
537 bo
->base
.alignment
= alignment
;
538 bo
->base
.usage
= usage
;
539 bo
->base
.size
= size
;
540 bo
->base
.vtbl
= &radeon_bo_vtbl
;
542 bo
->handle
= args
.handle
;
544 bo
->initial_domain
= initial_domains
;
545 pipe_mutex_init(bo
->map_mutex
);
546 pb_cache_init_entry(&rws
->bo_cache
, &bo
->cache_entry
, &bo
->base
);
548 if (rws
->info
.r600_virtual_address
) {
549 struct drm_radeon_gem_va va
;
551 bo
->va
= radeon_bomgr_find_va(rws
, size
, alignment
);
553 va
.handle
= bo
->handle
;
555 va
.operation
= RADEON_VA_MAP
;
556 va
.flags
= RADEON_VM_PAGE_READABLE
|
557 RADEON_VM_PAGE_WRITEABLE
|
558 RADEON_VM_PAGE_SNOOPED
;
560 r
= drmCommandWriteRead(rws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
561 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
562 fprintf(stderr
, "radeon: Failed to allocate virtual address for buffer:\n");
563 fprintf(stderr
, "radeon: size : %d bytes\n", size
);
564 fprintf(stderr
, "radeon: alignment : %d bytes\n", alignment
);
565 fprintf(stderr
, "radeon: domains : %d\n", args
.initial_domain
);
566 fprintf(stderr
, "radeon: va : 0x%016llx\n", (unsigned long long)bo
->va
);
567 radeon_bo_destroy(&bo
->base
);
570 pipe_mutex_lock(rws
->bo_handles_mutex
);
571 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
572 struct pb_buffer
*b
= &bo
->base
;
573 struct radeon_bo
*old_bo
=
574 util_hash_table_get(rws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
576 pipe_mutex_unlock(rws
->bo_handles_mutex
);
577 pb_reference(&b
, &old_bo
->base
);
581 util_hash_table_set(rws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
582 pipe_mutex_unlock(rws
->bo_handles_mutex
);
585 if (initial_domains
& RADEON_DOMAIN_VRAM
)
586 rws
->allocated_vram
+= align(size
, rws
->size_align
);
587 else if (initial_domains
& RADEON_DOMAIN_GTT
)
588 rws
->allocated_gtt
+= align(size
, rws
->size_align
);
593 bool radeon_bo_can_reclaim(struct pb_buffer
*_buf
)
595 struct radeon_bo
*bo
= radeon_bo(_buf
);
597 if (radeon_bo_is_referenced_by_any_cs(bo
))
600 return radeon_bo_wait(_buf
, 0, RADEON_USAGE_READWRITE
);
603 static unsigned eg_tile_split(unsigned tile_split
)
605 switch (tile_split
) {
606 case 0: tile_split
= 64; break;
607 case 1: tile_split
= 128; break;
608 case 2: tile_split
= 256; break;
609 case 3: tile_split
= 512; break;
611 case 4: tile_split
= 1024; break;
612 case 5: tile_split
= 2048; break;
613 case 6: tile_split
= 4096; break;
618 static unsigned eg_tile_split_rev(unsigned eg_tile_split
)
620 switch (eg_tile_split
) {
632 static void radeon_bo_get_tiling(struct pb_buffer
*_buf
,
633 enum radeon_bo_layout
*microtiled
,
634 enum radeon_bo_layout
*macrotiled
,
635 unsigned *bankw
, unsigned *bankh
,
636 unsigned *tile_split
,
637 unsigned *stencil_tile_split
,
641 struct radeon_bo
*bo
= radeon_bo(_buf
);
642 struct drm_radeon_gem_set_tiling args
;
644 memset(&args
, 0, sizeof(args
));
646 args
.handle
= bo
->handle
;
648 drmCommandWriteRead(bo
->rws
->fd
,
649 DRM_RADEON_GEM_GET_TILING
,
653 *microtiled
= RADEON_LAYOUT_LINEAR
;
654 *macrotiled
= RADEON_LAYOUT_LINEAR
;
655 if (args
.tiling_flags
& RADEON_TILING_MICRO
)
656 *microtiled
= RADEON_LAYOUT_TILED
;
657 else if (args
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
658 *microtiled
= RADEON_LAYOUT_SQUARETILED
;
660 if (args
.tiling_flags
& RADEON_TILING_MACRO
)
661 *macrotiled
= RADEON_LAYOUT_TILED
;
662 if (bankw
&& tile_split
&& stencil_tile_split
&& mtilea
&& tile_split
) {
663 *bankw
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
664 *bankh
= (args
.tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
665 *tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
666 *stencil_tile_split
= (args
.tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
667 *mtilea
= (args
.tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
668 *tile_split
= eg_tile_split(*tile_split
);
671 *scanout
= bo
->rws
->gen
>= DRV_SI
&& !(args
.tiling_flags
& RADEON_TILING_R600_NO_SCANOUT
);
674 static void radeon_bo_set_tiling(struct pb_buffer
*_buf
,
675 struct radeon_winsys_cs
*rcs
,
676 enum radeon_bo_layout microtiled
,
677 enum radeon_bo_layout macrotiled
,
678 unsigned pipe_config
,
679 unsigned bankw
, unsigned bankh
,
681 unsigned stencil_tile_split
,
682 unsigned mtilea
, unsigned num_banks
,
686 struct radeon_bo
*bo
= radeon_bo(_buf
);
687 struct radeon_drm_cs
*cs
= radeon_drm_cs(rcs
);
688 struct drm_radeon_gem_set_tiling args
;
690 memset(&args
, 0, sizeof(args
));
692 /* Tiling determines how DRM treats the buffer data.
693 * We must flush CS when changing it if the buffer is referenced. */
694 if (cs
&& radeon_bo_is_referenced_by_cs(cs
, bo
)) {
695 cs
->flush_cs(cs
->flush_data
, 0, NULL
);
698 os_wait_until_zero(&bo
->num_active_ioctls
, PIPE_TIMEOUT_INFINITE
);
700 if (microtiled
== RADEON_LAYOUT_TILED
)
701 args
.tiling_flags
|= RADEON_TILING_MICRO
;
702 else if (microtiled
== RADEON_LAYOUT_SQUARETILED
)
703 args
.tiling_flags
|= RADEON_TILING_MICRO_SQUARE
;
705 if (macrotiled
== RADEON_LAYOUT_TILED
)
706 args
.tiling_flags
|= RADEON_TILING_MACRO
;
708 args
.tiling_flags
|= (bankw
& RADEON_TILING_EG_BANKW_MASK
) <<
709 RADEON_TILING_EG_BANKW_SHIFT
;
710 args
.tiling_flags
|= (bankh
& RADEON_TILING_EG_BANKH_MASK
) <<
711 RADEON_TILING_EG_BANKH_SHIFT
;
713 args
.tiling_flags
|= (eg_tile_split_rev(tile_split
) &
714 RADEON_TILING_EG_TILE_SPLIT_MASK
) <<
715 RADEON_TILING_EG_TILE_SPLIT_SHIFT
;
717 args
.tiling_flags
|= (stencil_tile_split
&
718 RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
) <<
719 RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
;
720 args
.tiling_flags
|= (mtilea
& RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
) <<
721 RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
;
723 if (bo
->rws
->gen
>= DRV_SI
&& !scanout
)
724 args
.tiling_flags
|= RADEON_TILING_R600_NO_SCANOUT
;
726 args
.handle
= bo
->handle
;
729 drmCommandWriteRead(bo
->rws
->fd
,
730 DRM_RADEON_GEM_SET_TILING
,
735 static struct radeon_winsys_cs_handle
*radeon_drm_get_cs_handle(struct pb_buffer
*_buf
)
737 /* return radeon_bo. */
738 return (struct radeon_winsys_cs_handle
*)radeon_bo(_buf
);
741 static struct pb_buffer
*
742 radeon_winsys_bo_create(struct radeon_winsys
*rws
,
745 boolean use_reusable_pool
,
746 enum radeon_bo_domain domain
,
747 enum radeon_bo_flag flags
)
749 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
750 struct radeon_bo
*bo
;
753 /* Align size to page size. This is the minimum alignment for normal
754 * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
755 * like constant/uniform buffers, can benefit from better and more reuse.
757 size
= align(size
, ws
->size_align
);
759 /* Only set one usage bit each for domains and flags, or the cache manager
760 * might consider different sets of domains / flags compatible
762 if (domain
== RADEON_DOMAIN_VRAM_GTT
)
766 assert(flags
< sizeof(usage
) * 8 - 3);
767 usage
|= 1 << (flags
+ 3);
769 if (use_reusable_pool
) {
770 bo
= pb_cache_reclaim_buffer(&ws
->bo_cache
, size
, alignment
, usage
);
775 bo
= radeon_create_bo(ws
, size
, alignment
, usage
, domain
, flags
);
779 bo
->use_reusable_pool
= use_reusable_pool
;
781 pipe_mutex_lock(ws
->bo_handles_mutex
);
782 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
783 pipe_mutex_unlock(ws
->bo_handles_mutex
);
788 static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys
*rws
,
789 void *pointer
, unsigned size
)
791 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
792 struct drm_radeon_gem_userptr args
;
793 struct radeon_bo
*bo
;
796 bo
= CALLOC_STRUCT(radeon_bo
);
800 memset(&args
, 0, sizeof(args
));
801 args
.addr
= (uintptr_t)pointer
;
802 args
.size
= align(size
, sysconf(_SC_PAGE_SIZE
));
803 args
.flags
= RADEON_GEM_USERPTR_ANONONLY
|
804 RADEON_GEM_USERPTR_VALIDATE
|
805 RADEON_GEM_USERPTR_REGISTER
;
806 if (drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_USERPTR
,
807 &args
, sizeof(args
))) {
812 pipe_mutex_lock(ws
->bo_handles_mutex
);
815 pipe_reference_init(&bo
->base
.reference
, 1);
816 bo
->handle
= args
.handle
;
817 bo
->base
.alignment
= 0;
818 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
819 bo
->base
.size
= size
;
820 bo
->base
.vtbl
= &radeon_bo_vtbl
;
822 bo
->user_ptr
= pointer
;
824 bo
->initial_domain
= RADEON_DOMAIN_GTT
;
825 pipe_mutex_init(bo
->map_mutex
);
827 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
829 pipe_mutex_unlock(ws
->bo_handles_mutex
);
831 if (ws
->info
.r600_virtual_address
) {
832 struct drm_radeon_gem_va va
;
834 bo
->va
= radeon_bomgr_find_va(rws
, bo
->base
.size
, 1 << 20);
836 va
.handle
= bo
->handle
;
837 va
.operation
= RADEON_VA_MAP
;
840 va
.flags
= RADEON_VM_PAGE_READABLE
|
841 RADEON_VM_PAGE_WRITEABLE
|
842 RADEON_VM_PAGE_SNOOPED
;
844 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
845 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
846 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
847 radeon_bo_destroy(&bo
->base
);
850 pipe_mutex_lock(ws
->bo_handles_mutex
);
851 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
852 struct pb_buffer
*b
= &bo
->base
;
853 struct radeon_bo
*old_bo
=
854 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
856 pipe_mutex_unlock(ws
->bo_handles_mutex
);
857 pb_reference(&b
, &old_bo
->base
);
861 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
862 pipe_mutex_unlock(ws
->bo_handles_mutex
);
865 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->size_align
);
867 return (struct pb_buffer
*)bo
;
870 static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys
*rws
,
871 struct winsys_handle
*whandle
,
874 struct radeon_drm_winsys
*ws
= radeon_drm_winsys(rws
);
875 struct radeon_bo
*bo
;
880 /* We must maintain a list of pairs <handle, bo>, so that we always return
881 * the same BO for one particular handle. If we didn't do that and created
882 * more than one BO for the same handle and then relocated them in a CS,
883 * we would hit a deadlock in the kernel.
885 * The list of pairs is guarded by a mutex, of course. */
886 pipe_mutex_lock(ws
->bo_handles_mutex
);
888 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
889 /* First check if there already is an existing bo for the handle. */
890 bo
= util_hash_table_get(ws
->bo_names
, (void*)(uintptr_t)whandle
->handle
);
891 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
892 /* We must first get the GEM handle, as fds are unreliable keys */
893 r
= drmPrimeFDToHandle(ws
->fd
, whandle
->handle
, &handle
);
896 bo
= util_hash_table_get(ws
->bo_handles
, (void*)(uintptr_t)handle
);
898 /* Unknown handle type */
903 /* Increase the refcount. */
904 struct pb_buffer
*b
= NULL
;
905 pb_reference(&b
, &bo
->base
);
909 /* There isn't, create a new one. */
910 bo
= CALLOC_STRUCT(radeon_bo
);
915 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
916 struct drm_gem_open open_arg
= {};
917 memset(&open_arg
, 0, sizeof(open_arg
));
919 open_arg
.name
= whandle
->handle
;
920 if (drmIoctl(ws
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
)) {
924 handle
= open_arg
.handle
;
925 size
= open_arg
.size
;
926 bo
->flink_name
= whandle
->handle
;
927 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
928 size
= lseek(whandle
->handle
, 0, SEEK_END
);
930 * Could check errno to determine whether the kernel is new enough, but
931 * it doesn't really matter why this failed, just that it failed.
933 if (size
== (off_t
)-1) {
937 lseek(whandle
->handle
, 0, SEEK_SET
);
943 pipe_reference_init(&bo
->base
.reference
, 1);
944 bo
->base
.alignment
= 0;
945 bo
->base
.usage
= PB_USAGE_GPU_WRITE
| PB_USAGE_GPU_READ
;
946 bo
->base
.size
= (unsigned) size
;
947 bo
->base
.vtbl
= &radeon_bo_vtbl
;
950 pipe_mutex_init(bo
->map_mutex
);
953 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
955 util_hash_table_set(ws
->bo_handles
, (void*)(uintptr_t)bo
->handle
, bo
);
958 pipe_mutex_unlock(ws
->bo_handles_mutex
);
961 *stride
= whandle
->stride
;
963 if (ws
->info
.r600_virtual_address
&& !bo
->va
) {
964 struct drm_radeon_gem_va va
;
966 bo
->va
= radeon_bomgr_find_va(rws
, bo
->base
.size
, 1 << 20);
968 va
.handle
= bo
->handle
;
969 va
.operation
= RADEON_VA_MAP
;
972 va
.flags
= RADEON_VM_PAGE_READABLE
|
973 RADEON_VM_PAGE_WRITEABLE
|
974 RADEON_VM_PAGE_SNOOPED
;
976 r
= drmCommandWriteRead(ws
->fd
, DRM_RADEON_GEM_VA
, &va
, sizeof(va
));
977 if (r
&& va
.operation
== RADEON_VA_RESULT_ERROR
) {
978 fprintf(stderr
, "radeon: Failed to assign virtual address space\n");
979 radeon_bo_destroy(&bo
->base
);
982 pipe_mutex_lock(ws
->bo_handles_mutex
);
983 if (va
.operation
== RADEON_VA_RESULT_VA_EXIST
) {
984 struct pb_buffer
*b
= &bo
->base
;
985 struct radeon_bo
*old_bo
=
986 util_hash_table_get(ws
->bo_vas
, (void*)(uintptr_t)va
.offset
);
988 pipe_mutex_unlock(ws
->bo_handles_mutex
);
989 pb_reference(&b
, &old_bo
->base
);
993 util_hash_table_set(ws
->bo_vas
, (void*)(uintptr_t)bo
->va
, bo
);
994 pipe_mutex_unlock(ws
->bo_handles_mutex
);
997 bo
->initial_domain
= radeon_bo_get_initial_domain((void*)bo
);
999 if (bo
->initial_domain
& RADEON_DOMAIN_VRAM
)
1000 ws
->allocated_vram
+= align(bo
->base
.size
, ws
->size_align
);
1001 else if (bo
->initial_domain
& RADEON_DOMAIN_GTT
)
1002 ws
->allocated_gtt
+= align(bo
->base
.size
, ws
->size_align
);
1004 return (struct pb_buffer
*)bo
;
1007 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1011 static boolean
radeon_winsys_bo_get_handle(struct pb_buffer
*buffer
,
1013 struct winsys_handle
*whandle
)
1015 struct drm_gem_flink flink
;
1016 struct radeon_bo
*bo
= radeon_bo(buffer
);
1017 struct radeon_drm_winsys
*ws
= bo
->rws
;
1019 memset(&flink
, 0, sizeof(flink
));
1021 bo
->use_reusable_pool
= false;
1023 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
1024 if (!bo
->flink_name
) {
1025 flink
.handle
= bo
->handle
;
1027 if (ioctl(ws
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
)) {
1031 bo
->flink_name
= flink
.name
;
1033 pipe_mutex_lock(ws
->bo_handles_mutex
);
1034 util_hash_table_set(ws
->bo_names
, (void*)(uintptr_t)bo
->flink_name
, bo
);
1035 pipe_mutex_unlock(ws
->bo_handles_mutex
);
1037 whandle
->handle
= bo
->flink_name
;
1038 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
1039 whandle
->handle
= bo
->handle
;
1040 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
1041 if (drmPrimeHandleToFD(ws
->fd
, bo
->handle
, DRM_CLOEXEC
, (int*)&whandle
->handle
))
1045 whandle
->stride
= stride
;
1049 static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle
*buf
)
1051 return ((struct radeon_bo
*)buf
)->va
;
1054 void radeon_drm_bo_init_functions(struct radeon_drm_winsys
*ws
)
1056 ws
->base
.buffer_get_cs_handle
= radeon_drm_get_cs_handle
;
1057 ws
->base
.buffer_set_tiling
= radeon_bo_set_tiling
;
1058 ws
->base
.buffer_get_tiling
= radeon_bo_get_tiling
;
1059 ws
->base
.buffer_map
= radeon_bo_map
;
1060 ws
->base
.buffer_unmap
= radeon_bo_unmap
;
1061 ws
->base
.buffer_wait
= radeon_bo_wait
;
1062 ws
->base
.buffer_create
= radeon_winsys_bo_create
;
1063 ws
->base
.buffer_from_handle
= radeon_winsys_bo_from_handle
;
1064 ws
->base
.buffer_from_ptr
= radeon_winsys_bo_from_ptr
;
1065 ws
->base
.buffer_get_handle
= radeon_winsys_bo_get_handle
;
1066 ws
->base
.buffer_get_virtual_address
= radeon_winsys_bo_va
;
1067 ws
->base
.buffer_get_initial_domain
= radeon_bo_get_initial_domain
;